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HS

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IRQEN

TRIM

PWMSRCSEL

CTRL

IRQS

IRQCLR


IRQEN

High Side Driver Interrupt Enable Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQEN IRQEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HS1_OT_IEN HS1_OL_IEN HS1_OC_IEN

HS1_OT_IEN : High Side 1 Overtemperature Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : disabled

None

0b1 : enable

None

End of enumeration elements list.

HS1_OL_IEN : High Side 1 Open Load Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.

HS1_OC_IEN : High Side 1 Overcurrent Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : disable

None

0b1 : enable

None

End of enumeration elements list.


TRIM

High Side Driver 1 TRIM
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TRIM TRIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HS1_OL_BTFILT_SEL HS1_OC_OT_BTFILT_SEL

HS1_OL_BTFILT_SEL : Blanking Time Filter Select for HS1 open Load detection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0b00 : 4_us

4 us filter time

0b01 : 8_us

8 us filter time

0b10 : 16_us

16 us filter time

0b11 : 32_us

32 us filter time

End of enumeration elements list.

HS1_OC_OT_BTFILT_SEL : Blanking Time Filter Select for HS1 overcurrent / overtemperature detection
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0b00 : 4_us

4 us filter time

0b01 : 8_us

8 us filter time

0b10 : 16_us

16 us filter time

0b11 : 32_us

32 us filter time

End of enumeration elements list.


PWMSRCSEL

High Side PWM Source Selection Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PWMSRCSEL PWMSRCSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HS1_SRC_SEL

HS1_SRC_SEL : HS1 PWM Source Selection
bits : 3 - 4 (2 bit)
access : read-write

Enumeration:

0b000 : CC60

PWM output of CCU6

0b001 : CC61

PWM output of CCU6

0b010 : CC62

PWM output of CCU6

0b011 : COUT60

PWM output of CCU6

0b100 : COUT61

PWM output of CCU6

0b101 : COUT62

PWM output of CCU6

0b110 : T3OUT

PWM output of GPT12

End of enumeration elements list.


CTRL

High Side Driver Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HS1_EN HS1_PWM HS1_ON HS1_OL_EN HS1_SR_CTRL_SEL HS1_OC_SEL

HS1_EN : High Side 1 Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

HS circuit power off

0b1 : ENABLE

HS circuit power on

End of enumeration elements list.

HS1_PWM : High Side 1 PWM Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

disables control by PWM input

0b1 : ENABLE

enables control by PWM input

End of enumeration elements list.

HS1_ON : High Side 1 On
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : OFF

HS driver off

0b1 : ON

HS driver on

End of enumeration elements list.

HS1_OL_EN : High Side 1 Open Load Detection Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

disable open load detection

0b1 : ENABLE

enable open load detection

End of enumeration elements list.

HS1_SR_CTRL_SEL : High Side 1 Slew Rate Control select
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0b00 : Slew Rate 1

Slow Slew Rate 3V/us is enabled

0b01 : Slew Rate 2

Fast Slew Rate 40V/us is enabled

0b10 : Slew Rate 3

Low EMC Slew Rate 1V/us is enabled (for low EMC emissions)

End of enumeration elements list.

HS1_OC_SEL : High Side 1 Overcurrent Threshold Selection
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

0x0 : IOCTH0

25 mA min.

0x1 : IOCTH1

50 mA min.

0x2 : IOCTH2

100 mA min.

0x3 : IOCTH3

150 mA min.

End of enumeration elements list.


IRQS

High Side Driver Interrupt Status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQS IRQS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HS1_OT_IS HS1_OL_IS HS1_OC_IS HS1_OT_STS HS1_OL_STS

HS1_OT_IS : High Side 1 Overtemperature Interrupt Status
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : no Overtemperature

no overtemperature occurred.

0b1 : Overtemperature

overtemperature occurred switch is automatically shutdown. Write sets status

End of enumeration elements list.

HS1_OL_IS : High Side 1 Open Load Interrupt Status
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : NORMAL

normal load

0b1 : OPEN LOAD

open load detected, write sets status

End of enumeration elements list.

HS1_OC_IS : High Side 1 Overcurrent Interrupt Status
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : no Overcurrent

no overcurrent Condition occurred.

0b1 : Overcurrent

overcurrent occurred switch is automatically shutdown. Write sets status.

End of enumeration elements list.

HS1_OT_STS : High Side 1 Overtemperature Status
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : no Overtemperature

no overtemperature occurred.

0b1 : Overtemperature

overtemperature occurred switch is automatically shutdown. Write sets status.

End of enumeration elements list.

HS1_OL_STS : High Side 1 Open Load Status
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : no Open Load

no open load Condition occurred.

0b1 : Open Load

open load occurred switch is not automatically shutdown. Write sets status.

End of enumeration elements list.


IRQCLR

High Side Driver Interrupt Status Clear Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IRQCLR IRQCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HS1_OT_ISC HS1_OL_ISC HS1_OC_ISC HS1_OT_SC HS1_OL_SC

HS1_OT_ISC : High Side 1 Overtemperature Interrupt Status Clear
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

HS1_OL_ISC : High Side 1 Open Load Interrupt Status Clear
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

HS1_OC_ISC : High Side 1 Overcurrent Interrupt Status Clear
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

HS1_OT_SC : High Side 1 Overtemperature Status Clear
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.

HS1_OL_SC : High Side 1 Open Load Status Clear
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

0b0 : no Clear

None

0b1 : Clear

None

End of enumeration elements list.



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