\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Event Flag Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVEOC : Divider End of Calculation Event Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : no EOC
Divider end of calculation event has not been detected.
0b1 : EOC
Divider end of calculation event has been detected.
End of enumeration elements list.
DIVERR : Divider Error Event Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : no Error
Divider error event has not been detected
0b1 : Error
Divider error event has been detected
End of enumeration elements list.
Event Flag Set Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVEOCS : Divider End of Calculation Event Flag Set
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : no effect
No effect.
0b1 : Set
Sets the Divider end of calculation event flag in EVFR register. Interrupt will be generated if enabled in EVIER register.
End of enumeration elements list.
DIVERRS : Divider Error Event Flag Set
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : no effect
No effect.
0b1 : Set
Sets the Divider error event flag in EVFR register. Interrupt will be generated if enabled in EVIER register.
End of enumeration elements list.
Event Flag Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVEOCC : Divider End of Calculation Event Flag Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : no effect
No effect.
0b1 : clear
Clears the Divider end of calculation event flag in EVFR register.
End of enumeration elements list.
DIVERRC : Divider Error Event Flag Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : no effect
No effect.
0b1 : clear
Clears the Divider error event flag in EVFR register.
End of enumeration elements list.
Dividend Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Dividend Value
bits : 0 - 30 (31 bit)
access : read-write
Divisor Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Divisor Value
bits : 0 - 30 (31 bit)
access : read-write
Quotient Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Quotient Value
bits : 0 - 30 (31 bit)
access : read-only
Remainder Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Remainder Value
bits : 0 - 30 (31 bit)
access : read-only
Divider Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSY : Busy Indication
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : finish
Divider is not running any division operation.
0b1 : busy
Divider is still running a division operation.
End of enumeration elements list.
Divider Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ST : Start Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : no effect
No effect
0b1 : Start
Start the division operation when STMODE=1#
End of enumeration elements list.
STMODE : Start Mode
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : Auto
Calculation is automatically started with a write to DVS register
0b1 : Manual
Calculation is started by setting the ST bit to 1
End of enumeration elements list.
USIGN : Unsigned Division Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : signed
Signed division is selected
0b1 : unsigned
Unsigned division is selected
End of enumeration elements list.
DIVMODE : Division Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0b00 : 32-32
32-bit divide by 32-bit
0b01 : 32-16
32-bit divide by 16-bit
0b10 : 16-16
16-bit divide by 16-bit
End of enumeration elements list.
QSCNT : Quotient Shift Count
bits : 8 - 11 (4 bit)
access : read-write
QSDIR : Quotient Shift Direction
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
0b0 : Left shift
Left shift
0b1 : Right Shift
Right shift
End of enumeration elements list.
DVDSLC : Dividend Shift Left Count
bits : 16 - 19 (4 bit)
access : read-write
DVSSRC : Divisor Shift Right Count
bits : 24 - 27 (4 bit)
access : read-write
Global Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVDRC : Dividend Register Result Chaining
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : disabled
No result chaining is selected
0b01 : QUOT
QUOT register is the selected source
0b10 : RMD
RMD register is the selected source
End of enumeration elements list.
DVSRC : Divisor Register Result Chaining
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
0b00 : disabled
No result chaining is selected
0b01 : QUOT
QUOT register is the selected source
0b10 : RMD
RMD register is the selected source
End of enumeration elements list.
SUSCFG : Suspend Mode Configuration
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
0b00 : no suspend
Suspend mode is never entered.
0b01 : hard suspend
Hard suspend mode will be entered when CPU is halted.
0b10 : soft suspend
Soft suspend mode will be entered when CPU is halted.
End of enumeration elements list.
MATH_EN : Enable Math Module
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
0b1 : Enable
Math module is enabled
0b0 : Disable
Math module is disabled
End of enumeration elements list.
Module Identification Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_REV : Module Revision Number
bits : 0 - 6 (7 bit)
access : read-only
MOD_TYPE : Module Type
bits : 8 - 14 (7 bit)
access : read-only
MOD_NUMBER : Module Number Value
bits : 16 - 30 (15 bit)
access : read-only
Event Interupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVEOCIEN : Divider End of Calculation Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Divider end of calculation interrupt generation is disabled.
0b1 : Enable
Divider end of calculation interrupt generation is enabled.
End of enumeration elements list.
DIVERRIEN : Divider Error Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Divider error interrupt generation is disabled
0b1 : Enable
Divider error interrupt generation is enabled
End of enumeration elements list.
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.