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MATH

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

EVFR

EVSFR

EVFCR

DVD

DVS

QUOT

RMD

DIVST

DIVCON

GLBCON

ID

EVIER


EVFR

Event Flag Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVFR EVFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVEOC DIVERR

DIVEOC : Divider End of Calculation Event Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : no EOC

Divider end of calculation event has not been detected.

0b1 : EOC

Divider end of calculation event has been detected.

End of enumeration elements list.

DIVERR : Divider Error Event Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b0 : no Error

Divider error event has not been detected

0b1 : Error

Divider error event has been detected

End of enumeration elements list.


EVSFR

Event Flag Set Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVSFR EVSFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVEOCS DIVERRS

DIVEOCS : Divider End of Calculation Event Flag Set
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b0 : no effect

No effect.

0b1 : Set

Sets the Divider end of calculation event flag in EVFR register. Interrupt will be generated if enabled in EVIER register.

End of enumeration elements list.

DIVERRS : Divider Error Event Flag Set
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b0 : no effect

No effect.

0b1 : Set

Sets the Divider error event flag in EVFR register. Interrupt will be generated if enabled in EVIER register.

End of enumeration elements list.


EVFCR

Event Flag Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVFCR EVFCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVEOCC DIVERRC

DIVEOCC : Divider End of Calculation Event Flag Clear
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b0 : no effect

No effect.

0b1 : clear

Clears the Divider end of calculation event flag in EVFR register.

End of enumeration elements list.

DIVERRC : Divider Error Event Flag Clear
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b0 : no effect

No effect.

0b1 : clear

Clears the Divider error event flag in EVFR register.

End of enumeration elements list.


DVD

Dividend Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVD DVD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Dividend Value
bits : 0 - 30 (31 bit)
access : read-write


DVS

Divisor Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVS DVS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Divisor Value
bits : 0 - 30 (31 bit)
access : read-write


QUOT

Quotient Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QUOT QUOT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Quotient Value
bits : 0 - 30 (31 bit)
access : read-only


RMD

Remainder Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RMD RMD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Remainder Value
bits : 0 - 30 (31 bit)
access : read-only


DIVST

Divider Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIVST DIVST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BSY

BSY : Busy Indication
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : finish

Divider is not running any division operation.

0b1 : busy

Divider is still running a division operation.

End of enumeration elements list.


DIVCON

Divider Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIVCON DIVCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST STMODE USIGN DIVMODE QSCNT QSDIR DVDSLC DVSSRC

ST : Start Bit
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : no effect

No effect

0b1 : Start

Start the division operation when STMODE=1#

End of enumeration elements list.

STMODE : Start Mode
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : Auto

Calculation is automatically started with a write to DVS register

0b1 : Manual

Calculation is started by setting the ST bit to 1

End of enumeration elements list.

USIGN : Unsigned Division Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : signed

Signed division is selected

0b1 : unsigned

Unsigned division is selected

End of enumeration elements list.

DIVMODE : Division Mode
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0b00 : 32-32

32-bit divide by 32-bit

0b01 : 32-16

32-bit divide by 16-bit

0b10 : 16-16

16-bit divide by 16-bit

End of enumeration elements list.

QSCNT : Quotient Shift Count
bits : 8 - 11 (4 bit)
access : read-write

QSDIR : Quotient Shift Direction
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : Left shift

Left shift

0b1 : Right Shift

Right shift

End of enumeration elements list.

DVDSLC : Dividend Shift Left Count
bits : 16 - 19 (4 bit)
access : read-write

DVSSRC : Divisor Shift Right Count
bits : 24 - 27 (4 bit)
access : read-write


GLBCON

Global Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GLBCON GLBCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DVDRC DVSRC SUSCFG MATH_EN

DVDRC : Dividend Register Result Chaining
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0b00 : disabled

No result chaining is selected

0b01 : QUOT

QUOT register is the selected source

0b10 : RMD

RMD register is the selected source

End of enumeration elements list.

DVSRC : Divisor Register Result Chaining
bits : 3 - 3 (1 bit)
access : read-write

Enumeration:

0b00 : disabled

No result chaining is selected

0b01 : QUOT

QUOT register is the selected source

0b10 : RMD

RMD register is the selected source

End of enumeration elements list.

SUSCFG : Suspend Mode Configuration
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

0b00 : no suspend

Suspend mode is never entered.

0b01 : hard suspend

Hard suspend mode will be entered when CPU is halted.

0b10 : soft suspend

Soft suspend mode will be entered when CPU is halted.

End of enumeration elements list.

MATH_EN : Enable Math Module
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

0b1 : Enable

Math module is enabled

0b0 : Disable

Math module is disabled

End of enumeration elements list.


ID

Module Identification Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ID ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOD_REV MOD_TYPE MOD_NUMBER

MOD_REV : Module Revision Number
bits : 0 - 6 (7 bit)
access : read-only

MOD_TYPE : Module Type
bits : 8 - 14 (7 bit)
access : read-only

MOD_NUMBER : Module Number Value
bits : 16 - 30 (15 bit)
access : read-only


EVIER

Event Interupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EVIER EVIER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVEOCIEN DIVERRIEN

DIVEOCIEN : Divider End of Calculation Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : Disable

Divider end of calculation interrupt generation is disabled.

0b1 : Enable

Divider end of calculation interrupt generation is enabled.

End of enumeration elements list.

DIVERRIEN : Divider Error Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : Disable

Divider error interrupt generation is disabled

0b1 : Enable

Divider error interrupt generation is enabled

End of enumeration elements list.



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