Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
NMI Status Clear Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FNMIWDTC : Watchdog Timer NMI Flag
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
FNMIPLLC : PLL NMI Flag
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
FNMIOWDC : Oscillator Watchdog NMI Flag
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
FNMIMAPC : NVM Map Error NMI Flag
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
Interrupt Request Register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIR2 : Error Interrupt Flag for SSC2
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
TIR2 : Transmit Interrupt Flag for SSC2
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
RIR2 : Receive Interrupt Flag for SSC2
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
Peripheral Input Select Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL12EN : Pins XTAL1/2 Enable Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Pins XTAL1/2 is not available. This setting overrides the .XPD setting.
0b1 : Enable
Pins XTAL1/2 are available
End of enumeration elements list.
XTALHYSEN : XTAL Hysteresis Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Hysteresis is disabled
0b1 : Enable
Hysteresis is enabled
End of enumeration elements list.
XTALHYSCTRL : XTAL Hysteresis Control
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0b00 : XHYST_0
400mV nom.
0b01 : XHYST_1
300mV nom.
0b10 : XHYST_2
200mV nom.
0b11 : XHYST_3
100mV nom.
End of enumeration elements list.
Error Detection and Correction Status Clear Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDBEC : RAM Double Bit Error Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
A double bit error on RAM is not cleared.
0b1 : Cleared
A double bit error on RAM is cleared.
End of enumeration elements list.
NVMDBEC : NVM Double Bit Error Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
A double bit error on NVM is not cleared.
0b1 : Cleared
A double bit error on NVM is cleared.
End of enumeration elements list.
RSBEC : RAM Single Bit Error Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : Not cleared
A single bit error on RAM is not cleared.
0b1 : Cleared
A single bit error on RAM is cleared.
End of enumeration elements list.
Stack Overflow Status Clear Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOF_STSC : Clear Stack Overflow Status
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
stack overflow not cleared.
0b1 : Cleared
stack overflow cleared.
End of enumeration elements list.
Interrupt Request Register 4
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCU6SR0 : Interrupt Flag 1 for CCU6
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
CCU6SR1 : Interrupt Flag 1 for CCU6
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
CCU6SR2 : Interrupt Flag 1 for CCU6
bits : 16 - 15 (0 bit)
access : read-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
CCU6SR3 : Interrupt Flag 1 for CCU6
bits : 20 - 19 (0 bit)
access : read-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
Stack Overflow Control Register
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOF_EN : Stack Overflow Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
stack overflow detection disabled.
0b1 : Enable
stack overflow detection enabled
End of enumeration elements list.
Stack Overflow Control Register
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOF_ADDR_OFF_L : Stack Overflow Low Address Offset
bits : 2 - 10 (9 bit)
access : read-write
STOF_ADDR_OFF_H : Stack Overflow High Address Offset
bits : 18 - 26 (9 bit)
access : read-write
Stack Overflow Status Register
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STOF_STS : Stack Overflow Status
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : No Error
No stack overflow detected.
0b1 : Error
stack overflow detected.
End of enumeration elements list.
ADC1 Peripheral Clock Register
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRDRV_CLK_DIV : Analog Module Clock Factorf
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : div 1
Divide by 1
0b01 : div 2
Divide by 2
0b10 : div 3
Divide by 3
0b11 : div 4
Divide by 4
End of enumeration elements list.
BRDRV_TFILT_DIV : Slow Down Clock Divider for TFILT_CLK Generation
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0b00000 : div 1
fsys
0b00001 : div 2
fsys/2
0b00010 : div 3
fsys/3
0b00011 : div 4
fsys/4
0b00100 : div 5
fsys/5
0b00101 : div 6
fsys/6
0b00110 : div 7
fsys/7
0b00111 : div 8
fsys/8
0b01000 : div 9
fsys/9
0b01001 : div 10
fsys/10
0b01010 : div 11
fsys/11
0b01011 : div 12
fsys/12
0b11110 : div 31
fsys/31
0b11111 : div 32
fsys/32
End of enumeration elements list.
General Purpose Timer 12 Interrupt Enable Register
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T2IE : General Purpose Timer 12 T2 Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
disabled
0b1 : Enable
enabled
End of enumeration elements list.
T3IE : General Purpose Timer 12 T3 Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
disabled
0b1 : Enable
enabled
End of enumeration elements list.
T4IE : General Purpose Timer 12 T4 Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
disabled
0b1 : Enable
enabled
End of enumeration elements list.
T5IE : General Purpose Timer 12 T5 Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
disabled
0b1 : Enable
enabled
End of enumeration elements list.
T6IE : General Purpose Timer 12 T6 Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
disabled
0b1 : Enable
enabled
End of enumeration elements list.
CRIE : General Purpose Timer 12 Capture and Reload Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
disabled
0b1 : Enable
enabled
End of enumeration elements list.
Timer and Counter Control/Status Register
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPT1T2 : GPT Module 1 Timer 2 Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
No Timer 2 Interrupt has occurred.
0b1 : Int
Timer 2 Interrupt has occurred.
End of enumeration elements list.
GPT1T3 : GPT Module 1 Timer3 Interrupt Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
No Timer 3 Interrupt has occurred.
0b1 : Int
Timer 3 Interrupt has occurred.
End of enumeration elements list.
GPT1T4 : GPT Module 1 Timer4 Interrupt Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
No Timer 4 Interrupt has occurred.
0b1 : Int
Timer 4 Interrupt has occurred.
End of enumeration elements list.
GPT2T5 : GPT Module 2 Timer5 Interrupt Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
No Timer 5 Interrupt has occurred.
0b1 : Int
Timer 5 Interrupt has occurred.
End of enumeration elements list.
GPT2T6 : GPT Module 2Timer6 Interrupt Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
No Timer 6 Interrupt has occurred.
0b1 : Int
Timer 6 Interrupt has occurred.
End of enumeration elements list.
GPT12CR : GPT Module 1 Capture Reload Interrupt Status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
No Capture Reload Interrupt has occurred.
0b1 : Int
Capture Reload Interrupt has occurred.
End of enumeration elements list.
Interrupt Request 0 Clear Register
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXINT0RC : Interrupt Flag for External Interrupt 0x on rising edge
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : not cleared
Interrupt event is not cleared.
0b1 : cleared
Interrupt event is cleared
End of enumeration elements list.
EXINT0FC : Interrupt Flag for External Interrupt 0x on falling edge
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : not cleared
Interrupt event is not cleared.
0b1 : cleared
Interrupt event is cleared
End of enumeration elements list.
EXINT1RC : Interrupt Flag for External Interrupt 1x on rising edge
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
0b0 : not cleared
Interrupt event is not cleared.
0b1 : cleared
Interrupt event is cleared
End of enumeration elements list.
EXINT1FC : Interrupt Flag for External Interrupt 1x on falling edge
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
0b0 : not cleared
Interrupt event is not cleared.
0b1 : cleared
Interrupt event is cleared
End of enumeration elements list.
EXINT2RC : Interrupt Flag for External Interrupt 2x on rising edge
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : not cleared
Interrupt event is not cleared.
0b1 : cleared
Interrupt event is cleared
End of enumeration elements list.
EXINT2FC : Interrupt Flag for External Interrupt 2x on falling edge
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
0b0 : not cleared
Interrupt event is not cleared.
0b1 : cleared
Interrupt event is cleared
End of enumeration elements list.
Interrupt Request 1 Clear Register
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MON1RC : Interrupt Flag for MON1x on rising edge
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
MON1FC : Interrupt Flag for MON1x on falling edge
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
MON2RC : Interrupt Flag for MON2x on rising edge
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
MON2FC : Interrupt Flag for MON2x on falling edge
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
MON3RC : Interrupt Flag for MON3x on rising edge
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
MON3FC : Interrupt Flag for MON3x on falling edge
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
MON4RC : Interrupt Flag for MON4x on rising edge
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
MON4FC : Interrupt Flag for MON4x on falling edge
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
NMI Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FNMIWDT : Watchdog Timer NMI Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : no Int
No watchdog NMI has occurred.
0b1 : Int
WDT prewarning has occurred.
End of enumeration elements list.
FNMIPLL : PLL NMI Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : no Int
No PLL NMI has occurred.
0b1 : Int
PLL loss-of-lock to the external crystal has occurred.
End of enumeration elements list.
FNMIOT : Overtemperature NMI Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : no Int
No OT NMI has occurred.
0b1 : Int
OT NMI event has occurred.
End of enumeration elements list.
FNMIOWD : Oscillator Watchdog NMI Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : no Int
No oscillator watchdog NMI has occurred.
0b1 : Int
Oscillator watchdog event has occurred.
End of enumeration elements list.
FNMIMAP : NVM Map Error NMI Flag
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : no Int
No NVM Map Error NMI has occurred.
0b1 : Int
NVM Map Error has occurred.
End of enumeration elements list.
FNMIECC : ECC Error NMI Flag
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
0b0 : no Int
No uncorrectable ECC error has occurred on NVM, XRAM.
0b1 : Int
Uncorrectable ECC error has occurred on NVM, RAM.
End of enumeration elements list.
FNMISUP : Supply Prewarning NMI Flag
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
0b0 : no Int
No supply prewarning NMI has occurred.
0b1 : Int
Supply prewarning has occurred.
End of enumeration elements list.
FNMISTOF : Stack Overflow NMI Flag
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
0b0 : no Int
No supply prewarning NMI has occurred.
0b1 : Int
Supply prewarning has occurred.
End of enumeration elements list.
Timer and Counter Control/Status Clear Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPT1T2C : GPT Module 1 Timer 2 Interrupt Status
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
GPT1T3C : GPT Module 1 Timer3 Interrupt Status
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
GPT1T4C : GPT Module 1 Timer4 Interrupt Status
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
GPT2T5C : GPT Module 2 Timer5 Interrupt Status
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
GPT2T6C : GPT Module 2Timer6 Interrupt Status
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
GPT12CRC : GPT Module 1 Capture Reload Interrupt Status
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
Monitoring Input Interrupt Enable Register
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MON1IE : MON 1 Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
disabled
0b1 : Enable
enabled
End of enumeration elements list.
MON2IE : MON 2 Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
disabled
0b1 : Enable
enabled
End of enumeration elements list.
MON3IE : MON 3 Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
disabled
0b1 : Enable
enabled
End of enumeration elements list.
MON4IE : MON 4 Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
disabled
0b1 : Enable
enabled
End of enumeration elements list.
Interrupt Request 2 Clear Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIR1C : Error Interrupt Flag for SSC1
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
TIR1C : Transmit Interrupt Flag for SSC1
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
RIR1C : Receive Interrupt Flag for SSC1
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
Interrupt Request 3 Clear Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIR2C : Error Interrupt Flag for SSC2
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
TIR2C : Transmit Interrupt Flag for SSC2
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
RIR2C : Receive Interrupt Flag for SSC2
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
Interrupt Request 4 Clear Register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCU6SR0C : Interrupt Flag 1 for CCU6
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
CCU6SR1C : Interrupt Flag 1 for CCU6
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
CCU6SR2C : Interrupt Flag 1 for CCU6
bits : 16 - 15 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
CCU6SR3C : Interrupt Flag 1 for CCU6
bits : 20 - 19 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
Interrupt Request 5 Clear Register
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEUPC : Clear Flag for Wakeup Interrupt
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
Interrupt Enable Register 0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Global Interrupt Mask
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
0b0 : disable
All pending interrupt requests (except NMI) are blocked from the core.
0b1 : enable
Pending interrupt requests are not blocked from the core.
End of enumeration elements list.
Vector Table Reallocation Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VTOR_BYP : Vector Table Bypass Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : ROM
VTOR is not remapped (ROM)
0b01 : RAM
VTOR is remapped to RAM
0b10 : NVM_BSL
VTOR is remapped to NVM
0b11 : NVM_LIN
VTOR is remapped to NVM
End of enumeration elements list.
NMI Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMIWDT : Watchdog Timer NMI Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : disable
WDT NMI is disabled.
0b1 : enable
WDT NMI is enabled.
End of enumeration elements list.
NMIPLL : PLL Loss of Lock NMI Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : disable
PLL Loss of Lock NMI is disabled.
0b1 : enable
PLL Loss of Lock NMI is enabled.
End of enumeration elements list.
NMIOT : NMI OT Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : disable
NMI OT is disabled.
0b1 : enable
NMI OT is enabled.
End of enumeration elements list.
NMIOWD : Oscillator Watchdog NMI Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : disable
Oscillator watchdog NMI is disabled.
0b1 : enable
Oscillator watchdog NMI is enabled.
End of enumeration elements list.
NMIMAP : NVM Map Error NMI Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : disable
NVM Map Error NMI is disabled.
0b1 : enable
NVM Map Error NMI is enabled.
End of enumeration elements list.
NMIECC : ECC Error NMI Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : disable
ECC Error NMI is disabled.
0b1 : enable
ECC Error NMI is enabled.
End of enumeration elements list.
NMISUP : Supply Prewarning NMI Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : disable
Supply NMI is disabled.
0b1 : enable
Supply NMI is enabled.
End of enumeration elements list.
NMISTOF : Stack Overflow NMI Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : disable
Stack overflow NMI is disabled.
0b1 : enable
Stack overflow NMI is enabled.
End of enumeration elements list.
External Interrupt Control Register 0
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXINT0 : External Interrupt 0 Trigger Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : enable
Interrupt disabled.
0b01 : rising
Interrupt on rising edge.
0b10 : falling
Interrupt on falling edge.
0b11 : both
Interrupt on both rising and falling edge.
End of enumeration elements list.
EXINT1 : External Interrupt 1 Trigger Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0b00 : disable
Interrupt disabled.
0b01 : rising
Interrupt on rising edge.
0b10 : falling
Interrupt on falling edge.
0b11 : both
Interrupt on both rising and falling edge.
End of enumeration elements list.
EXINT2 : External Interrupt 2 Trigger Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0b00 : disable
Interrupt disabled.
0b01 : rising
Interrupt on rising edge.
0b10 : falling
Interrupt on falling edge.
0b11 : both
Interrupt on both rising and falling edge.
End of enumeration elements list.
External Interrupt Control Register 1
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MON1 : MON1 Input Trigger Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : disable
external interrupt MON is disabled.
0b01 : rising
Interrupt on rising edge.
0b10 : falling
Interrupt on falling edge.
0b11 : both
Interrupt on both rising and falling edge.
End of enumeration elements list.
MON2 : MON2 Input Trigger Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0b00 : disable
external interrupt MON is disabled.
0b01 : rising
Interrupt on rising edge.
0b10 : falling
Interrupt on falling edge.
0b11 : both
Interrupt on both rising and falling edge.
End of enumeration elements list.
MON3 : MON3 Input Trigger Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0b00 : disable
external interrupt MON is disabled.
0b01 : rising
Interrupt on rising edge.
0b10 : falling
Interrupt on falling edge.
0b11 : both
Interrupt on both rising and falling edge.
End of enumeration elements list.
MON4 : MON4 Input Trigger Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0b00 : disable
external interrupt MON is disabled.
0b01 : rising
Interrupt on rising edge.
0b10 : falling
Interrupt on falling edge.
0b11 : both
Interrupt on both rising and falling edge.
End of enumeration elements list.
Peripheral Interrupt Enable Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIREN1 : SSC 1 Error Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Error interrupt is disabled
0b1 : Enable
Error interrupt is enabled
End of enumeration elements list.
TIREN1 : SSC 1 Transmit Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Transmit interrupt is disabled
0b1 : Enable
Transmit interrupt is enabled
End of enumeration elements list.
RIREN1 : SSC 1 Receive Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Receive interrupt is disabled
0b1 : Enable
Receive interrupt is enabled
End of enumeration elements list.
EIREN2 : SSC 2 Error Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Error interrupt is disabled
0b1 : Enable
Error interrupt is enabled
End of enumeration elements list.
TIREN2 : SSC 2 Transmit Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Transmit interrupt is disabled
0b1 : Enable
Transmit interrupt is enabled
End of enumeration elements list.
RIREN2 : SSC 2 Receive Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Receive interrupt is disabled
0b1 : Enable
Receive interrupt is enabled
End of enumeration elements list.
Peripheral Interrupt Enable Register 2
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIEN1 : UART 1 Receive Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Receive interrupt is disabled
0b1 : Enable
Receive interrupt is enabled
End of enumeration elements list.
TIEN1 : UART 1 Transmit Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Transmit interrupt is disabled
0b1 : Enable
Transmit interrupt is enabled
End of enumeration elements list.
EXINT2_EN : External Interrupt 2 Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
External interrupt is disabled
0b1 : Enable
External interrupt is enabled
End of enumeration elements list.
RIEN2 : UART 2 Receive Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Receive interrupt is disabled
0b1 : Enable
Receive interrupt is enabled
End of enumeration elements list.
TIEN2 : UART 2 Transmit Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Transmit interrupt is disabled
0b1 : Enable
Transmit interrupt is enabled
End of enumeration elements list.
Peripheral Interrupt Enable Register 3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IE0 : External Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
disabled
0b1 : Enable
enabled
End of enumeration elements list.
Peripheral Interrupt Enable Register 4
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IE1 : External Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
disabled
0b1 : Enable
enabled
End of enumeration elements list.
Interrupt Request Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXINT0R : Interrupt Flag for External Interrupt 0x on rising edge
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : Int
Interrupt on rising edge event has not occurred.
0b1 : no Int
Interrupt on rising edge event has occurred.
End of enumeration elements list.
EXINT0F : Interrupt Flag for External Interrupt 0x on falling edge
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : Int
Interrupt on falling edge event has not occurred.
0b1 : no Int
Interrupt on falling edge event has occurred.
End of enumeration elements list.
EXINT1R : Interrupt Flag for External Interrupt 1x on rising edge
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : Int
Interrupt on rising edge event has not occurred.
0b1 : no Int
Interrupt on rising edge event has occurred.
End of enumeration elements list.
EXINT1F : Interrupt Flag for External Interrupt 1x on falling edge
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : Int
Interrupt on falling edge event has not occurred.
0b1 : no Int
Interrupt on falling edge event has occurred.
End of enumeration elements list.
EXINT2R : Interrupt Flag for External Interrupt 2x on rising edge
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : Int
Interrupt on rising edge event has not occurred.
0b1 : no Int
Interrupt on rising edge event has occurred.
End of enumeration elements list.
EXINT2F : Interrupt Flag for External Interrupt 2x on falling edge
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : Int
Interrupt on falling edge event has not occurred.
0b1 : no Int
Interrupt on falling edge event has occurred.
End of enumeration elements list.
Power Mode Control Register 0
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_ON : OSC_HP Operation in Power Down Mode
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : PD
OSC_HP (XTAL) will be put to Power Down mode by hardware in power save mode.
0b1 : ON
OSC_HP (XTAL) continues to operate in Power Down mode, if enabled by SCU_OSC_CON.XPD.
End of enumeration elements list.
SL : Sleep Mode Enable. Active High.
bits : 1 - 0 (0 bit)
access : read-write
PD : Power Down Mode Enable. Active High.
bits : 2 - 1 (0 bit)
access : read-write
SD : Slow Down Mode Enable. Active High.
bits : 3 - 2 (0 bit)
access : read-write
PLL Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : PLL Lock Status Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : Not Locked
The frequency difference of fREF and fDIV is greater than allowed. The VCO part of the PLL can not lock on a target frequency.
0b1 : Locked
The frequency difference of fREF and fDIV is small enough to enable a stable VCO operation.
End of enumeration elements list.
RESLD : Restart Lock Detection
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : No reset
No effect.
0b1 : reset
Reset lock flag and restart lock detection.
End of enumeration elements list.
OSCDISC : Oscillator Disconnect
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : Connect
Oscillator is connected to the PLL
0b1 : Disconnect
Oscillator is disconnected to the PLL.
End of enumeration elements list.
VCOBYP : PLL VCO Bypass Mode Select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : Normal
Normal (or freerunning) operation (default)
0b1 : Prescaler
Prescaler Mode VCO is bypassed (PLL output clock is derived from input clock divided by K1-divider)
End of enumeration elements list.
NDIV : PLL N-Divider
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
00 : 0
N = 39, ...
38 : 38
N = 39
39 : 39
N = 39, ...
80 : 80
N = 80 (default), ...
200 : 200
N = 200
201 : 201
N = 200, ...
255 : 255
N = 200
End of enumeration elements list.
UNPROT_OSCDISC : Unprotect write access of OSC_DISC
bits : 18 - 17 (0 bit)
access : write-only
UNPROT_VCOBYP : Unprotect write access of VCO_BYP
bits : 19 - 18 (0 bit)
access : write-only
Clock Control Register 1
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKREL : Slow Down Clock Divider for fCCLK Generation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0b0000 : div 1
fsys
0b0001 : div 2
fsys/2
0b0010 : div 3
fsys/3
0b0011 : div 4
fsys/4
0b0100 : div 8
fsys/8
0b0101 : div 16
fsys/16
0b0110 : div 24
fsys/24
0b0111 : div 32
fsys/32
0b1000 : div 48
fsys/48
0b1001 : div 64
fsys/64
0b1010 : div 96
fsys/96
0b1011 : div 128
fsys/128
0b1100 : div 192
fsys/192
0b1101 : div 256
fsys/256
0b1110 : div 384
fsys/384
0b1111 : div 512
fsys/512
End of enumeration elements list.
K2DIV : PLL K2-Divider
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0x0 : div 2
K2 = 2 (default)
0x1 : div 3
K2 = 3
0x2 : div 4
K2 = 4
0x3 : div 5
K2 = 5
0x4 : div 6
K2 = 6
0x5 : div 7
K2 = 7
0x6 : div 8
K2 = 8
0x7 : div 9
K2 = 9
End of enumeration elements list.
K1DIV : PLL K1-Divider
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : div 2
K1 = 2
0b1 : div 1
K1 = 1
End of enumeration elements list.
PDIV : PLL PDIV-Divider:
bits : 8 - 12 (5 bit)
access : read-write
Enumeration:
0 : 0
P = 4
1 : 1
P = 4
2 : 2
P = 4
3 : 3
P = 4
4 : 4
P = 4
5 : 5
P = 5 (default)
6 : 6
P = 6, ...
50 : 50
P = 50
51 : 51
P = 50, ...
63 : 63
P = 50
End of enumeration elements list.
Clock Control Register 2
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBA0CLKREL : PBA0 Clock Divider
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : div 1
divide by 1
0b1 : div 2
divide by 2
End of enumeration elements list.
Watchdog Timer Control Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTIN : Watchdog Timer Input Frequency Selection
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : DIV 2
Input frequency is fPCLK/2
0b1 : DIV 128
Input frequency is fPCLK/128
End of enumeration elements list.
WDTRS : WDT Refresh Start
bits : 1 - 0 (0 bit)
access : read-write
WDTEN : WDT Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
WDT is disabled
0b1 : Enable
WDT is enabled
End of enumeration elements list.
WDTPR : Watchdog Prewarning Mode Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : Normal
Normal mode (default after reset)
0b1 : Prewarn
The Watchdog is operating in Prewarning Mode
End of enumeration elements list.
WINBEN : Watchdog Window-Boundary Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Watchdog Window-Boundary feature is disabled. (default)
0b1 : Enable
Watchdog Window-Boundary feature is enabled.
End of enumeration elements list.
Analog Peripheral Clock Control Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APCLK_SET : Set and Overtake Flag for Clock Settings
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : ignore
Clock Settings are ignored (previous values are held)
0b1 : update
Clock Settings are overtaken
End of enumeration elements list.
CLKWDT_IE : Clock Watchdog Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : disabled
Interrupt disabled
0b1 : enabled
Interrupt enabled
End of enumeration elements list.
Analog Peripheral Clock Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APCLK1FAC : Analog Module Clock Factor
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : div 1
Divide by 1
0b01 : div 2
Divide by 2
0b10 : div 3
Divide by 3
0b11 : div 4
Divide by 4
End of enumeration elements list.
APCLK2FAC : Slow Down Clock Divider for TFILT_CLK Generation
bits : 8 - 11 (4 bit)
access : read-write
Enumeration:
0b00000 : div 1
fsys
0b00001 : div 2
fsys/2
0b00010 : div 3
fsys/3
0b00011 : div 4
fsys/4
0b00100 : div 5
fsys/5
0b00101 : div 6
fsys/6
0b00110 : div 7
fsys/7
0b00111 : div 8
fsys/8
0b01000 : div 9
fsys/9
0b01001 : div 10
fsys/10
0b01010 : div 11
fsys/11
0b01011 : div 12
fsys/12
0b11110 : div 31
fsys/31
0b11111 : div 32
fsys/32
End of enumeration elements list.
BGCLK_SEL : Bandgap Clock Selection
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
0b0 : LP_CLK
LP_CLK is selected
0b1 : f_sys
fsys is selected
End of enumeration elements list.
BGCLK_DIV : Bandgap Clock Divider
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
0b0 : div 2
divide by 2
0b1 : div 1
divide by 1
End of enumeration elements list.
CPCLK_SEL : Charge Pump Clock Selection
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
0b0 : LP_CLK
LP_CLK is selected
0b1 : f_sys
fsys is selected
End of enumeration elements list.
CPCLK_DIV : Charge Pump Clock Divider
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
0b0 : div 2
divide by 2
0b1 : div 1
divide by 1
End of enumeration elements list.
Analog Peripheral Clock Status Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APCLK1STS : Analog Peripherals Clock Status
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
0b00 : OK
The MI_CLK clock is in the required range
0b01 : too high
The MI_CLK clock exceeds the higher limit
0b10 : too low
The MI_CLK clock exceeds the lower limit
0b11 : out of limit
The MI_CLK clock is not inside the specified limit.
End of enumeration elements list.
APCLK_ERR_STS : APCLK Error Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : no Error
no Error writing was not blocked
0b1 : Error
Error writing was blocked
End of enumeration elements list.
APCLK2STS : Analog Peripherals Clock Status
bits : 8 - 8 (1 bit)
access : read-only
Enumeration:
0b00 : OK
The TFILT_CLK clock is in the required range
0b01 : Too high
The TFILT_CLK clock exceeds the higher limit
0b10 : Too low
The TFILT_CLK clock exceeds the lower limit
0b11 : Out of Limit
The TFILT_CLK clock is not inside the specified limit.
End of enumeration elements list.
APCLK3STS : Loss of Clock Status
bits : 16 - 15 (0 bit)
access : read-only
Enumeration:
0b0 : no loss
No loss of clock
0b1 : loss
Loss of clock occurred
End of enumeration elements list.
BRDRV_CLK_ERR_STS : BRDRV CLK Error Status
bits : 20 - 19 (0 bit)
access : read-only
Enumeration:
0b0 : no Error
no Error writing was not blocked
0b1 : Error
Error writing was blocked
End of enumeration elements list.
PLL_LOCK : PLL LOCK Status
bits : 24 - 23 (0 bit)
access : read-only
Enumeration:
0b0 : no lock
PLL has not locked
0b1 : lock
PLL has locked
End of enumeration elements list.
Peripheral Management Control Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1_DIS : ADC1 Disable Request. Active high.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
ADC1 is in normal operation. (default)
0b1 : Disable
Request to disable the ADC.
End of enumeration elements list.
SSC1_DIS : SSC Disable Request. Active high.
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
SSC is in normal operation. (default)
0b1 : Disable
Request to disable the SSC.
End of enumeration elements list.
CCU_DIS : CCU Disable Request. Active high.
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
CCU is in normal operation. (default)
0b1 : Disabel
Request to disable the CCU.
End of enumeration elements list.
T2_DIS : T2 Disable Request. Active high.
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
T2 is in normal operation. (default)
0b1 : Disable
Request to disable the T2.
End of enumeration elements list.
GPT12_DIS : General Purpose Timer 12 Disable Request. Active high.
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
GPT12 is in normal operation. (default)
0b1 : Disable
Request to disable the GPT12.
End of enumeration elements list.
SSC2_DIS : SSC Disable Request. Active high.
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
SSC is in normal operation. (default)
0b1 : Disable
Request to disable the SSC.
End of enumeration elements list.
T21_DIS : T21 Disable Request. Active high.
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
T21 is in normal operation. (default)
0b1 : Disable
Request to disable the T21.
End of enumeration elements list.
Analog Peripheral Clock Status Clear Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APCLK1SCLR : Analog Peripherals Clock Status Clear
bits : 0 - -1 (0 bit)
access : write-only
APCLK2SCLR : Analog Peripherals Clock Status Clear
bits : 8 - 7 (0 bit)
access : write-only
APCLK3SCLR : Analog Peripherals Clock 3 Status Clear
bits : 16 - 15 (0 bit)
access : write-only
Reset Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKUP : Lockup Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : disable
Lockup Status not active.
0b1 : enable
Lockup Status active.
End of enumeration elements list.
LOCKUP_EN : Lockup Reset Enable Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : disable
Lockup is disabled.
0b1 : enable
Lockup is enabled.
End of enumeration elements list.
ADC1 Peripheral Clock Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1_CLK_DIV : ADC1 Clock divider
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0b0000 : div 1
Divide by 1
0b0001 : div 2
Divide by 2
0b0010 : div 3
Divide by 3
0b0011 : div 4
Divide by 4
0b0100 : div 5
Divide by 5
0b0101 : div 6
Divide by 6
0b0110 : div 7
Divide by 7
0b0111 : div 8
Divide by 8
0b1110 : div 15
Divide by 15
0b1111 : div 16
Divide by 16
End of enumeration elements list.
DPP1_CLK_DIV : ADC1 Post processing clock divider
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0b00 : div 1
Divide by 1
0b01 : div 2
Divide by 2
0b10 : div 3
Divide by 3
0b11 : div 4
Divide by 4
End of enumeration elements list.
System Control Register 0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVMCLKFAC : NVM Access Clock Factor
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0b00 : div 1
Divide by 1
0b01 : div 2
Divide by 2
0b10 : div 3
Divide by 3
0b11 : div 4
Divide by 4
End of enumeration elements list.
SYSCLKSEL : System Clock Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0b00 : f_pll
The PLL clock output signal fPLL is used
0b01 : f_osc
The direct clock input from fOSC is used
0b10 : f_lpclk
The direct low-precision clock input from fLP_CLK is used.
0b11 : f_int
The direct input from internal oscillator fINTOSC is used
End of enumeration elements list.
System Startup Status Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_LOCK_STS : PLL LOCK STATUS
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : No Fail
None
0b1 : Fail
None
End of enumeration elements list.
MRAMINITSTS : Map RAM Initialisation Status
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : No Fail
Map RAM initialisation was successfull
0b1 : Fail
Map RAM initialisation was not successfull
End of enumeration elements list.
PG100TP_CHKS_ERR : 100 TP Page Checksum Error
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : OK
initialisation of trimming parameters from NVM was successfull (checksum was correct)
0b1 : Not OK
initialisation of trimming parameter from NVM was not successfull (checksum was not correct). As a backup default values form Boot-ROM are used
End of enumeration elements list.
Watchdog Timer Reload Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTREL : Watchdog Timer Reload Value
bits : 0 - 6 (7 bit)
access : read-write
Watchdog Window-Boundary Count
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTWINB : Watchdog Window-Boundary Count Value
bits : 0 - 6 (7 bit)
access : read-write
Interrupt Request Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MON1R : Interrupt Flag for MON1x on rising edge
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
Interrupt on rising edge event has not occurred.
0b1 : Int
Interrupt on rising edge event has occurred.
End of enumeration elements list.
MON1F : Interrupt Flag for MON1x on falling edge
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
Interrupt on falling edge event has not occurred.
0b1 : Int
Interrupt on falling edge event has occurred.
End of enumeration elements list.
MON2R : Interrupt Flag for MON2x on rising edge
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
Interrupt on rising edge event has not occurred.
0b1 : Int
Interrupt on rising edge event has occurred.
End of enumeration elements list.
MON2F : Interrupt Flag for MON2x on falling edge
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
Interrupt on falling edge event has not occurred.
0b1 : Int
Interrupt on falling edge event has occurred.
End of enumeration elements list.
MON3R : Interrupt Flag for MON3x on rising edge
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
Interrupt on rising edge event has not occurred.
0b1 : Int
Interrupt on rising edge event has occurred.
End of enumeration elements list.
MON3F : Interrupt Flag for MON3x on falling edge
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
Interrupt on falling edge event has not occurred.
0b1 : Int
Interrupt on falling edge event has occurred.
End of enumeration elements list.
MON4R : Interrupt Flag for MON4x on rising edge
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
Interrupt on rising edge event has not occurred.
0b1 : Int
Interrupt on rising edge event has occurred.
End of enumeration elements list.
MON4F : Interrupt Flag for MON4x on falling edge
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
0b0 : No Int
Interrupt on falling edge event has not occurred.
0b1 : Int
Interrupt on falling edge event has occurred.
End of enumeration elements list.
Watchdog Timer
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT : Watchdog Timer Current Value
bits : 0 - 14 (15 bit)
access : read-only
Baud Rate Control Register 1
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BR1_R : Baud Rate Generator Run Control Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Baud-rate generator disabled.
0b1 : Enable
Baud-rate generator enabled.
End of enumeration elements list.
BR1_PRE : Prescaler Bit
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0b000 : div 1
fDIV = fPCLK
0b001 : div 2
fDIV = fPCLK/2
0b010 : div 4
fDIV = fPCLK/4
0b011 : div 8
fDIV = fPCLK/8
0b100 : div 16
fDIV = fPCLK/16
0b101 : div 32
fDIV = fPCLK/32
End of enumeration elements list.
Baud Rate Timer/Reload Register, Low Byte 1
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BG1_FD_SEL : Fractional Divider Selection
bits : 0 - 3 (4 bit)
access : read-write
Baud Rate Timer/Reload Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BG1_BR_VALUE : Baud Rate Reload Value
bits : 0 - 9 (10 bit)
access : read-write
Enumeration:
0x000 : Bypass
Baud-rate timer is bypassed.
0x001 : 1
None
0x002 : 2
None
0x7FE : 2046
None
0x7FF : 2047
None
End of enumeration elements list.
BG1_TIM_VALUE : Baud Rate Timer Value
bits : 16 - 25 (10 bit)
access : read-only
Enumeration:
0x000 : Bypassed
Baud-rate timer is bypassed.
0x001 : 1
None
0x002 : 2
None
0x7FE : 2046
None
0x7FF : 2047
None
End of enumeration elements list.
LIN Status Register
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRDIS : Baud Rate Detection Disable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Break/Synch detection is enabled.
0b1 : Enable
Break/Synch detection is disabled.
End of enumeration elements list.
BGSEL : Baud Rate Select for Detection
bits : 1 - 1 (1 bit)
access : read-write
BRK : Break Field Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : Disable
Break Field is not detected.
0b1 : Enable
Break Field is detected.
End of enumeration elements list.
EOFSYN : End of SYN Byte Interrupt Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : Disable
End of SYN Byte is not detected.
0b1 : Enable
End of SYN Byte is detected.
End of enumeration elements list.
ERRSYN : SYN Byte Error Interrupt Flag
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : Disable
Error is not detected in SYN Byte.
0b1 : Enable
Error is detected in SYN Byte.
End of enumeration elements list.
SYNEN : End of SYN Byte and SYN Byte Error Interrupts Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
End of SYN Byte and SYN Byte Error Interrupts are not enabled.
0b1 : Enable
End of SYN Byte and SYN Byte Error Interrupts are enabled.
End of enumeration elements list.
Baud Rate Control Register 2
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BR2_R : Baud Rate Generator Run Control Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Baud-rate generator disabled.
0b1 : Enable
Baud-rate generator enabled.
End of enumeration elements list.
BR2_PRE : Prescaler Bit
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0b000 : div 1
fDIV = fPCLK
0b001 : div 2
fDIV = fPCLK/2
0b010 : div 4
fDIV = fPCLK/4
0b011 : div 8
fDIV = fPCLK/8
0b100 : div 16
fDIV = fPCLK/16
0b101 : div 32
fDIV = fPCLK/32
End of enumeration elements list.
Baud Rate Timer/Reload Register, Low Byte 2
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BG2_FD_SEL : Fractional Divider Selection
bits : 0 - 3 (4 bit)
access : read-write
Baud Rate Timer/Reload Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BG2_BR_VALUE : Baud Rate Reload Value
bits : 0 - 9 (10 bit)
access : read-write
Enumeration:
0x000 : Bypass
Baud-rate timer is bypassed.
0x001 : 1
None
0x002 : 2
None
0x7FE : 2046
None
0x7FF : 2047
None
End of enumeration elements list.
BG2_TIM_VALUE : Baud Rate Timer Value
bits : 16 - 25 (10 bit)
access : read-only
Enumeration:
0x000 : Bypassed
Baud-rate timer is bypassed.
0x001 : 1
None
0x002 : 2
None
0x7FE : 2046
None
0x7FF : 2047
None
End of enumeration elements list.
LIN Status Clear Register
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKC : Break Field Flag Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
0b0 : Not cleared
Break Field is not cleared.
0b1 : Cleared
Break Field is cleared.
End of enumeration elements list.
EOFSYNC : End of SYN Byte Interrupt Flag Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : Not cleared
End of SYN Byte is not cleared.
0b1 : Cleared
End of SYN Byte is cleared.
End of enumeration elements list.
ERRSYNC : SYN Byte Error Interrupt Flag
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
0b0 : Not cleared
Error in SYN Byte not cleared.
0b1 : Cleared
Error in SYN Byte cleared.
End of enumeration elements list.
Identity Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VERID : Version ID
bits : 0 - 1 (2 bit)
access : read-only
PRODID : Product ID
bits : 3 - 6 (4 bit)
access : read-only
Password Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PW_MODE : Bit-Protection Scheme Control Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : Disable
Scheme Disabled
0b11 : Enable
Scheme Enabled (default)
End of enumeration elements list.
PROTECT_S : Bit-Protection Signal Status Bit
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : Not protected
Software is able to write to all protected bits.
0b1 : Protected
Software is unable to write to any protected bits.
End of enumeration elements list.
PASS : Password Bits
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0b11000 : Enable
Enables writing of the bit field MODE.
0b10011 : Open
Opens access to writing of all protected bits.
0b10101 : Close
Closes access to writing of all protected bits.
End of enumeration elements list.
OSC Control Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSCSS : Oscillator Source Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : f_int_sync
PLL internal oscillator OSC_PLL (fINT) is selected synchronously as fR.
0b01 : Xtal_sync
XTAL (fOSC from OSC_HP) is selected synchronously as fR.
0b10 : f_int_async
PLL internal oscillator OSC_PLL (fINT) is selected asynchronously as fR.
End of enumeration elements list.
OSCWDTRST : Oscillator Watchdog Reset
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : No Reset
No effect.
0b1 : Reset
Reset OSC2L flag and restart the oscillator watchdog of the PLL.
End of enumeration elements list.
OSC2L : OSC-Too-Low Condition Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : OSC OK
fOSC is above threshold.
0b1 : OSC too low
fOSC is below threshold.
End of enumeration elements list.
XPD : XTAL (OSC_HP) Power Down Control
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : Enabled
XTAL (OSC_HP) is not powered down.
0b1 : Power down
XTAL (OSC_HP) is powered down.
End of enumeration elements list.
Clock Output Control Register
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COREL : Clock Output Divider
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0b0000 : div 1
fsys
0b0001 : div 2
fsys/2
0b0010 : div 3
fsys/3
0b0011 : div 4
fsys/4
0b0100 : div 6
fsys/6
0b0101 : div 8
fsys/8
0b0110 : div 10
fsys/10
0b0111 : div 12
fsys/12
0b1000 : div 14
fsys/14
0b1001 : div 16
fsys/16
0b1010 : div 18
fsys/18
0b1011 : div 20
fsys/20
0b1100 : div 24
fsys/24
0b1101 : div 32
fsys/32
0b1110 : div 36
fsys/36
0b1111 : div 40
fsys/40
End of enumeration elements list.
COUTS0 : Clock Out Source Select Bit 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : Osc
Oscillator output frequency is selected.
0b1 : COREL
Clock output frequency is chosen by the bit field COREL.
End of enumeration elements list.
TLEN : Toggle Latch Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : disable
Toggle Latch is disabled. Clock output frequency is chosen by the bit field COREL.
0b1 : enable
Toggle Latch is enabled. Clock output frequency is half of the frequency that is chosen by the bit field COREL. The resulting output frequency has 50 percent duty cycle.
End of enumeration elements list.
COUTS1 : Clock Out Source Select Bit 1
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : f_cclk
fCCLK is selected.
0b1 : COUTS0
Based on setting of COUTS0.
End of enumeration elements list.
EN : CLKOUT Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : disable
No external clock signal is provided
0b1 : enable
The configured external clock signal is provided
End of enumeration elements list.
Peripheral Input Select Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXINT0IS : External Interrupt 0 Input Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : EXINT0_0
External Interrupt Input EXINT0_0 is selected.
0b01 : EXINT0_1
External Interrupt Input EXINT0_1 is selected.
0b10 : EXINT0_2
External Interrupt Input EXINT0_2 is selected.
0b11 : EXINT0_3
External Interrupt Input EXINT0_3 is selected.
End of enumeration elements list.
EXINT1IS : External Interrupt 1 Input Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0b00 : EXINT1_0
External Interrupt Input EXINT1_0 is selected.
0b01 : EXINT1_1
External Interrupt Input EXINT1_1 is selected.
0b10 : EXINT1_2
External Interrupt Input EXINT1_2 is selected.
0b11 : EXINT1_3
External Interrupt Input EXINT1_3 is selected.
End of enumeration elements list.
EXINT2IS : External Interrupt 2 Input Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0b00 : EXINT2_0
External Interrupt Input EXINT2_0 is selected.
0b01 : EXINT2_1
External Interrupt Input EXINT2_1 is selected.
0b10 : EXINT2_2
External Interrupt Input EXINT2_2 is selected.
0b11 : EXINT2_3
External Interrupt Input EXINT2_3 is selected.
End of enumeration elements list.
URIOS1 : UART1 Input/Output Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
UART1 Receiver Input RXD1_0 (Connection to LIN is available).
0b1 : Disable
UART1 Receiver Input RXD1_1 (Connection to LIN is not available).
End of enumeration elements list.
U_TX_CONDIS : UART1 TxD Connection Disable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
UART1-TX-Output -LIN Transmitter TX Input Connection available.
0b1 : Disable
UART1-TX-Output -LIN Transmitter TX Input Connection not available (can be stimulated by external port pin).
End of enumeration elements list.
SSC12_M_SCK_OUTSEL : Output selection for SSC12_M_SCK
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
0b0 : SSC1
SSC1_M_SCK
0b1 : SSC2
SSC2_M_SCK
End of enumeration elements list.
SSC12_M_MTSR_OUTSEL : Output selection for SSC12_M_MTSR
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
0b0 : SSC1
SSC1_M_MTSR
0b1 : SSC2
SSC2_M_MTSR
End of enumeration elements list.
SSC12_S_MRST_OUTSEL : Output selection for SSC12_S_MRST
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
0b0 : SSC1
SSC1_S_MRST
0b1 : SSC2
SSC2_S_MRST
End of enumeration elements list.
Peripheral Input Select Register 1
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T2EXCON : Timer 2 External Input Control
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : MODPISEL
Timer 2 Input T2EX is selected by bit field SCU_MODPISEL2.T2EXIS.
0b1 : CCU
Timer 2 Input T2EX is connected to signal from CCU6 (Output >cc6_cout60).
End of enumeration elements list.
T21EXCON : Timer 21 External Input Control
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : MODPISEL
Timer 21 Input T21EX is selected by bit field SCU_MODPISEL2.T21EXIS.
0b1 : CCU6
Timer 21 Input T21EX is connected to signal from CCU6 (Output >cc6_ch0).
End of enumeration elements list.
Interrupt Request Register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIR1 : Error Interrupt Flag for SSC1
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
TIR1 : Transmit Interrupt Flag for SSC1
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
RIR1 : Receive Interrupt Flag for SSC1
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
Peripheral Input Select Register 2
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T2IS : Timer 2 Input Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : T2_0
Timer 2 Input T2_0 is selected.
0b01 : T2_1
Timer 2 Input T2_1 is selected.
0b10 : T2_2
Timer 2 Input T2_2 is selected.
End of enumeration elements list.
T21IS : Timer 21 Input Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0b00 : T21_0
Timer 21 Input T21_0 is selected.
0b01 : T21_1
Timer 21 Input T21_1 is selected.
0b10 : T21_2
Timer 21 Input T21_2 is selected.
End of enumeration elements list.
T2EXIS : Timer 2 External Input Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0b00 : value0
Timer 2 Input T2EX_0 or MON1 is selected.
0b01 : value1
Timer 2 Input T2EX_1 or MON2 is selected.
0b10 : value2
Timer 2 Input T2EX_2 or MON3 is selected.
0b11 : value3
Timer 2 Input T2EX_3 or MON4 is selected.
End of enumeration elements list.
T21EXIS : Timer 21 External Input Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0b00 : value0
Timer 21 Input T21EX_0 or MON1 is selected.
0b01 : value1
Timer 21 Input T21EX_1 or MON2 is selected.
0b10 : value2
Timer 21 Input T21EX_2 or MON3 is selected.
0b11 : value3
Timer 21 Input T21EX_3 or MON4 is selected.
End of enumeration elements list.
T2EXISCNF : Timer 2 External Input Select Configuration
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0b00 : T2EX_x
Timer 2 Input T2EX_x is selected.
0b01 : MONx
MONx Input is selected.
0b10 : T2EX_y
Timer 2 Input T2EX_x is selected.
0b11 : MONy
MONx Input is selected.
End of enumeration elements list.
T21EXISCNF : Timer 21 External Input Select Configuration
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0b00 : T21EX_x
Timer 21 Input T21EX_x is selected.
0b01 : MONx
MONx Input is selected.
0b10 : T21EX_y
Timer 21 Input T21EX_x is selected..
0b11 : MONy
MONx Input is selected.
End of enumeration elements list.
Peripheral Input Select Register 3
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
URIOS2 : UART2 Input/Output Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : RXTX_0
UART2 Receiver Input RXD2_0 and Transmitter Output TXD2_0 is selected.
0b1 : RXTX_1
UART2 Receiver Input RXD2_1 and Transmitter Output TXD2_1 is selected.
End of enumeration elements list.
Module Suspend Control Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSUSP : SCU Watchdog Timer Debug Suspend Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : No Suspend
WDT will not be suspended.
0b1 : Suspend
WDT will be suspended.
End of enumeration elements list.
T12SUSP : Timer 12 Debug Suspend Bit
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : No Suspend
Timer 12 in Capture/Compare Unit will not be suspended.
0b1 : Suspend
Timer 12 in Capture/Compare Unit will be suspended.
End of enumeration elements list.
T13SUSP : Timer 13 Debug Suspend Bit
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : No Suspend
Timer 13 in Capture/Compare Unit will not be suspended.
0b1 : Suspend
Timer 13 in Capture/Compare Unit will be suspended.
End of enumeration elements list.
T2_SUSP : Timer2 Debug Suspend Bit
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : No Suspend
Timer2 will not be suspended.
0b1 : Suspend
Timer2 will be suspended.
End of enumeration elements list.
GPT12_SUSP : GPT12 Debug Suspend Bit
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : No Suspend
GPT12 will not be suspended.
0b1 : Suspend
GPT12 will be suspended.
End of enumeration elements list.
T21_SUSP : Timer21 Debug Suspend Bit
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : No Suspend
Timer21 will not be suspended.
0b1 : Suspend
Timer21 will be suspended.
End of enumeration elements list.
WDT1SUSP : Watchdog Timer 1 Debug Suspend Bit
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : No Suspend
WDT1 will not be suspended.
0b1 : Suspend
WDT1 will be suspended.
End of enumeration elements list.
MU_SUSP : Measurement Unit Debug Suspend Bit
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : No Suspend
MU will not be suspended.
0b1 : Suspend
MU will be suspended.
End of enumeration elements list.
ADC1_SUSP : ADC1 Unit Debug Suspend Bit
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
0b0 : No suspend
ADC1 will not be suspended.
0b1 : Suspend
ADC1 will be suspended.
End of enumeration elements list.
GPT12 Peripheral Input Select Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPT12 : GPT12 TIN3B / TIN4D Input Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0b0000 : CC60
CC60
0b0001 : CC61
CC61
0b0010 : CC62
CC62
0b0011 : T12 ZM
T12 ZM
0b0100 : T12 PM
T12 PM
0b0101 : T12 CM0
T12 CM0
0b0110 : T12 CM1
T12 CM1
0b0111 : T12 CM2
T12 CM2
0b1000 : T13 PM
T13 PM
0b1001 : T13 ZM
T13 ZM
0b1010 : T13 CM
T13 CM
0b1011 : Edge
any pos or neg edge on CC60/61/62
End of enumeration elements list.
TRIG_CONF : CCU6 Trigger Configuration.
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : Single
Trigger is just for one measurement (default)
0b1 : Edge
Trigger is present until next input edge (selected by GPT12) - continuous measurement.
End of enumeration elements list.
GPT12_SEL : CCU6 Trigger Configuration.
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : T_21
CCU6_INT is triggered by Timer21
0b1 : GPT12
CCU6_INT is triggered by GPT12PISEL.GPT12
End of enumeration elements list.
Error Detection and Correction Control Register
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIE : RAM Double Bit ECC Error Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
No NMI is generated when a double bit ECC error occurs reading RAM.
0b1 : Enable
An NMI is generated when a double bit ECC error occurs reading RAM.
End of enumeration elements list.
NVMIE : NVM Double Bit ECC Error Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
No NMI is generated when a double bit ECC error occurs reading NVM.
0b1 : Enable
An NMI is generated when a double bit ECC error occurs reading NVM.
End of enumeration elements list.
Error Detection and Correction Status Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDBE : RAM Double Bit Error
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : No Error
No double bit error on RAM has occurred.
0b1 : Error
A double bit error on RAM has occurred.
End of enumeration elements list.
NVMDBE : NVM Double Bit Error
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : No Error
No double bit error on NVM has occurred.
0b1 : Error
A double bit error on NVM has occurred.
End of enumeration elements list.
RSBE : RAM Single Bit Error
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : No Error
No single bit error on RAM has occurred.
0b1 : Error
A single bit error on RAM has occurred.
End of enumeration elements list.
Memory Status Register
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECTORINFO : Sector Information
bits : 0 - 4 (5 bit)
access : read-write
SASTATUS : Service Algorithm Status
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0b00 : Success_1
Depending on SECTORINFO, there are two possible outcomes: For SECTORINFO = 00H, NVM initialization is successful and no SA is executed. For SECTORINFO = values other than 00H, SA execution is successful and only one map error is fixed.
0b01 : Success_2
SA execution is successful. More than one mapping error is fixed.
0b10 : Error_1
SA execution is not successful. Map error exists
0b11 : Error_2
NVM initialization failed, SA called but no page to be repaired has been found. Soft error present.
End of enumeration elements list.
NVM_VAL_KEYS : NVM valid keys
bits : 16 - 16 (1 bit)
access : read-write
NVM_DATA_MODE : NVM Data Mode
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
0b0 : 1
1 Non linearly mapped data sector
0b1 : 2
2 linearly mapped data sectors.
End of enumeration elements list.
RAM_VAL_KEYS : RAM valid keys
bits : 20 - 20 (1 bit)
access : read-write
RAM_TEST_MODE : RAM Data Mode
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
0b0 : Full
RAM test at cold reset executed on the whole RAM
0b1 : 1K
RAM test at cold reset executed only on 1st kb of RAM
End of enumeration elements list.
NVM Protection Status Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN_RD_CUS_BSL : NVM Read Protection of Data in Customer BSL Region
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : Protected
The data in region defined by NVMBSL can not be read
0b1 : Not Protected
The data in region defined by NVMBSL sectors of can be read
End of enumeration elements list.
EN_PRG_CUS_BSL : NVM Protection of Data in Customer BSL Region
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : Protected
The data in region defined by NVMBSL can not be changed
0b1 : Not Protected
The data in region defined by NVMBSL can be changed (erased or written)
End of enumeration elements list.
EN_RD_COD_LIN : NVM Read Protection of Data in Linear Code Sectors
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : Protected
The data in sectors of the linearly mapped area can not be read
0b1 : Not Protected
The data in sectors of the linearly mapped area can be read
End of enumeration elements list.
EN_PRG_COD_LIN : NVM Protection of Data in Linear Code Sectors
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : Protected
The data in sectors of the linearly mapped area can not be changed
0b1 : Not Protected
The data in sectors of the linearly mapped area can be changed (erased or written)
End of enumeration elements list.
EN_RD_DAT_LIN : NVM Read Protection of Data in Linear Data Sectors
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : Protected
The data in sectors of the linearly mapped area can not be read
0b1 : Not Protected
The data in sectors of the linearly mapped area can be read
End of enumeration elements list.
EN_PRG_DAT_LIN : NVM Protection of Data in Linear Data Sectors
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : Protected
The data in sectors of the linearly mapped area can not be changed
0b1 : Not Protected
The data in sectors of the linearly mapped area can be changed (erased or written)
End of enumeration elements list.
EN_RD_DAT_NL : NVM Read Protection of Data in Non-Linear Data Sectors
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
0b0 : Protected
The data in sectors of the non-linearly mapped area can not be read
0b1 : Not Protected
The data in sectors of the non-linearly mapped area can be read
End of enumeration elements list.
EN_PRG_DAT_NL : NVM Protection of Data in Non-Linear Data Sectors
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
0b0 : Protected
The data in sectors of the non-linearly mapped area can not be changed
0b1 : Not Protected
The data in sectors of the non-linearly mapped area can be changed (erased or written)
End of enumeration elements list.
EN_RD_S0 : NVM Read Protection for Sector 0
bits : 16 - 15 (0 bit)
access : read-only
Enumeration:
0b0 : Protected
The data in sector 0 can not be read over AHB-Lite Interface
0b1 : Not Protected
The data in sector 0 can be read over AHB-Lite Interface
End of enumeration elements list.
DIS_RDUS : Configuration of NVM Read Protection for Sector 1...n with EN_RD_* = 0
bits : 17 - 16 (0 bit)
access : read-only
Enumeration:
0b0 : Not Protected
only active when nvm_read_unsafe_i = 1 and not for nvm_read_unsafe_i = 0
0b1 : Protected
independent from nvm_read_unsafe_i Also write accesess to Sector 1...n are prevented
End of enumeration elements list.
DIS_RDUS_S0 : Configuration of NVM Read Protection for Sector 0 with EN_RD_S0 = 0
bits : 18 - 17 (0 bit)
access : read-only
Enumeration:
0b0 : Not Protected
only active when nvm_read_S0_unsafe_i = 1 and not for nvm_read_S0_unsafe_i = 0
0b1 : Protected
independent from nvm_read_S0_unsafe_i Also write accesess to Sector 0 are prevented
End of enumeration elements list.
CUS_BSL_PW : Status of CBSL Region Password / Protection
bits : 19 - 18 (0 bit)
access : read-only
Enumeration:
0b0 : Not Protected
CBSL Region Password is not installed CBSL region is not protected.
0b1 : Protected
CBSL Region Password is installed CBSL region is protected.
End of enumeration elements list.
COD_LIN_PW : Status of Linear Region Password / Protection
bits : 20 - 19 (0 bit)
access : read-only
Enumeration:
0b0 : Not Protected
Linear Region Password is not installed Linear region is not protected.
0b1 : Protected
Linear Region Password is installed Linear region is protected.
End of enumeration elements list.
DAT_LIN_PW : Status of Data linear Region Password / Protection
bits : 21 - 20 (0 bit)
access : read-only
Enumeration:
0b0 : Not protected
Non-Linear Region Password is not installed Linear region is not protected.
0b1 : Protected
Non-Linear Region Password is installed Linear region is protected.
End of enumeration elements list.
DAT_NL_PW : Status of Non-Linear Region Password / Protection
bits : 22 - 21 (0 bit)
access : read-only
Enumeration:
0b0 : Not Protected
Non-Linear Region Password is not installed Linear region is not protected.
0b1 : Protected
Non-Linear Region Password is installed Linear region is protected.
End of enumeration elements list.
CUS_BSL_SIZE : CBSL Region Size Definition
bits : 24 - 24 (1 bit)
access : read-only
Enumeration:
0b00 : 0K
CBSL Size is 0K
0b01 : 4K
CBSL Size is 4K
0b10 : 8K
CBSL Size is 8K
0b11 : 16K
CBSL Size is 16K
End of enumeration elements list.
DAT_LIN_SIZE : Data linear Region Size Definition
bits : 26 - 26 (1 bit)
access : read-only
Enumeration:
0b00 : 0K
data linear Size is 0K
0b01 : 4K
data linear Size is 4K
0b10 : 8K
data linear Size is 8K
0b11 : 12K
data linear Size is 12K
End of enumeration elements list.
Memory Access Status Register
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVM_PROT_ERR : NVM Access Protection
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : No Error
No Protection error
0b1 : Error
Protection error
End of enumeration elements list.
NVM_ADDR_ERR : NVM Address Protection
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : No Error
No Protection error
0b1 : Error
Protection error
End of enumeration elements list.
NVM_SFR_PROT_ERR : NVM SFR Access Protection
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : No Error
No Protection error
0b1 : Error
Protection error
End of enumeration elements list.
NVM_SFR_ADDR_ERR : NVM SFR Address Protection
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : No Error
No Protection error
0b1 : Error
Protection error
End of enumeration elements list.
ROM_PROT_ERR : ROM Access Protection
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : No Error
No Protection error
0b1 : Error
Protection error
End of enumeration elements list.
Port Output Control Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P0_PDM0 : P0.0 Port Driver Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0b000 : Strong-sharp
Strong driver and sharp edge mode
0b001 : Strong-med
Strong driver and medium edge mode
0b010 : Strong-soft
Strong driver and soft edge mode
0b011 : Weak
Weak driver
0b100 : Medium
Medium driver
End of enumeration elements list.
P0_PDM1 : P0.1 Port Driver Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0b000 : Strong-sharp
Strong driver and sharp edge mode
0b001 : Strong-med
Strong driver and medium edge mode
0b010 : Strong-soft
Strong driver and soft edge mode
0b011 : Weak
Weak driver
0b100 : Medium
Medium driver
End of enumeration elements list.
P0_PDM2 : P0.2 Port Driver Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0b000 : Strong-sharp
Strong driver and sharp edge mode
0b001 : Strong-med
Strong driver and medium edge mode
0b010 : Strong-soft
Strong driver and soft edge mode
0b011 : Weak
Weak driver
0b100 : Medium
Medium driver
End of enumeration elements list.
P0_PDM3 : P0.3 Port Driver Mode
bits : 12 - 13 (2 bit)
access : read-write
Enumeration:
0b000 : Strong-sharp
Strong driver and sharp edge mode
0b001 : Strong-med
Strong driver and medium edge mode
0b010 : Strong-soft
Strong driver and soft edge mode
0b011 : Weak
Weak driver
0b100 : Medium
Medium driver
End of enumeration elements list.
P0_PDM4 : P0.4 Port Driver Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0b000 : Strong-sharp
Strong driver and sharp edge mode
0b001 : Strong-med
Strong driver and medium edge mode
0b010 : Strong-soft
Strong driver and soft edge mode
0b011 : Weak
Weak driver
0b100 : Medium
Medium driver
End of enumeration elements list.
P0_PDM5 : P0.5 Port Driver Mode
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
0b000 : Strong-sharp
Strong driver and sharp edge mode
0b001 : Strong-med
Strong driver and medium edge mode
0b010 : Strong-soft
Strong driver and soft edge mode
0b011 : Weak
Weak driver
0b100 : Medium
Medium driver
End of enumeration elements list.
P0_PDM6 : P0.6 Port Driver Mode
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0b000 : Strong-sharp
Strong driver and sharp edge mode
0b001 : Strong-med
Strong driver and medium edge mode
0b010 : Strong-soft
Strong driver and soft edge mode
0b011 : Weak
Weak driver
0b100 : Medium
Medium driver
End of enumeration elements list.
Wakeup Interrupt Control Register
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEUPEN : Wakeup Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : disable
wakeup interrupt is disabled.
0b1 : enable
wakeup interrupt is enabled.
End of enumeration elements list.
Interrupt Request Register 5
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAKEUP : Interrupt Flag for Wakeup
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : Not Cleared
Interrupt event is not cleared.
0b1 : Cleared
Interrupt event is cleared
End of enumeration elements list.
Temperature Compensation Control Register
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCC : Temperature Compensation Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : T1
TJ: -40 degree C to 0 degree C
0b01 : T2
TJ: 0 degree C to 40 degree C
0b10 : T3
TJ: 40 degree C to 80 degree C
0b11 : T4
TJ: 80 degree C to 150 degree C
End of enumeration elements list.
Port Output Control Register
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
P1_PDM0 : P1.0 Port Driver Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0b011 : Weak
Weak driver
0b100 : Medium
Medium driver
End of enumeration elements list.
P1_PDM1 : P1.1 Port Driver Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0b011 : Weak
Weak driver
0b100 : Medium
Medium driver
End of enumeration elements list.
P1_PDM2 : P1.2 Port Driver Mode
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0b011 : Weak
Weak driver
0b100 : Medium
Medium driver
End of enumeration elements list.
P1_PDM4 : P1.4 Port Driver Mode
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0b000 : Strong-sharp
Strong driver and sharp edge mode
0b001 : Strong-med
Strong driver and medium edge mode
0b010 : Strong-soft
Strong driver and soft edge mode
0b011 : Weak
Weak driver
0b100 : Medium
Medium driver
End of enumeration elements list.
Peripheral Input Select Register 4
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DU1TRIGGEN : Differential Unit Trigger Enable
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0b000 : CC60
CC60 is selected.
0b001 : CC61
CC61 is selected.
0b010 : CC62
CC62 is selected.
0b011 : COUT60
COUT60 is selected.
0b100 : COUT61
COUT61 is selected.
0b101 : COUT62
COUT62 is selected.
0b110 : T3OUT
T3OUT is selected.
0b111 : COUT63
COUT63 is selected.
End of enumeration elements list.
DU2TRIGGEN : Differential Unit Trigger Enable
bits : 8 - 9 (2 bit)
access : read-write
Enumeration:
0b000 : CC60
CC60 is selected.
0b001 : CC61
CC61 is selected.
0b010 : CC62
CC62 is selected.
0b011 : COUT60
COUT60 is selected.
0b100 : COUT61
COUT61 is selected.
0b101 : COUT62
COUT62 is selected.
0b110 : T3OUT
T3OUT is selected.
0b111 : COUT63
COUT63 is selected.
End of enumeration elements list.
DU3TRIGGEN : Differential Unit Trigger Enable
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
0b000 : CC60
CC60 is selected.
0b001 : CC61
CC61 is selected.
0b010 : CC62
CC62 is selected.
0b011 : COUT60
COUT60 is selected.
0b100 : COUT61
COUT61 is selected.
0b101 : COUT62
COUT62 is selected.
0b110 : T3OUT
T3OUT is selected.
0b111 : COUT63
COUT63 is selected.
End of enumeration elements list.
DU4TRIGGEN : Differential Unit Trigger Enable
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
0b000 : CC60
CC60 is selected.
0b001 : CC61
CC61 is selected.
0b010 : CC62
CC62 is selected.
0b011 : COUT60
COUT60 is selected.
0b100 : COUT61
COUT61 is selected.
0b101 : COUT62
COUT62 is selected.
0b110 : T3OUT
T3OUT is selected.
0b111 : COUT63
COUT63 is selected.
End of enumeration elements list.
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