Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Analog Module Clock Frequency Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AMCLK1_FREQ : Current frequency of Analog Module Clock System Clock (MI_CLK)
bits : 0 - 4 (5 bit)
access : read-only
AMCLK2_FREQ : Current frequency of Analog Module Clock 2 (TFILT_CLK)
bits : 8 - 12 (5 bit)
access : read-only
System Interrupt Status Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYS_OTWARN_ISC : System Overtemperature Prewarning Interrupt Status Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
0b0 : No clear
None
0b1 : Clear
None
End of enumeration elements list.
SYS_OT_ISC : System Overtemperature Shutdown Interrupt Status Clear
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
0b0 : No clear
None
0b1 : Clear
None
End of enumeration elements list.
VREF1V2_UV_ISC : 8 Bit ADC2 Reference Undervoltage Interrupt Status Clear
bits : 12 - 11 (0 bit)
access : write-only
Enumeration:
0b0 : No clear
None
0b1 : Clear
None
End of enumeration elements list.
VREF1V2_OV_ISC : 8 Bit ADC2 Reference Overvoltage Interrupt Status Clear
bits : 13 - 12 (0 bit)
access : write-only
Enumeration:
0b0 : No clear
None
0b1 : Clear
None
End of enumeration elements list.
SYS_OTWARN_SC : System Overtemperature Prewarning Status Clear
bits : 24 - 23 (0 bit)
access : write-only
Enumeration:
0b0 : No clear
None
0b1 : Clear
None
End of enumeration elements list.
SYS_OT_SC : System Overtemperature Shutdown Status Clear
bits : 25 - 24 (0 bit)
access : write-only
Enumeration:
0b0 : No clear
None
0b1 : Clear
None
End of enumeration elements list.
VREF1V2_UV_SC : 8 Bit ADC2 Reference Undervoltage Status Clear
bits : 28 - 27 (0 bit)
access : write-only
Enumeration:
0b0 : No clear
None
0b1 : Clear
None
End of enumeration elements list.
VREF1V2_OV_SC : 8 Bit ADC2 Reference Overvoltage Status Clear
bits : 29 - 28 (0 bit)
access : write-only
Enumeration:
0b0 : No clear
None
0b1 : Clear
None
End of enumeration elements list.
System Interrupt Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LIN_FAIL_IS : LIN Fail Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : OK
no status set
0b1 : FAIL
at least one status set
End of enumeration elements list.
CP_FAIL_IS : Charge Pump Fail Interrupt Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : OK
no status set
0b1 : FAIL
at least one status set
End of enumeration elements list.
DRV_FAIL_IS : Gate Driver Fail Interrupt Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : OK
no status set
0b1 : FAIL
at least one status set
End of enumeration elements list.
HS_FAIL_IS : High Side Driver Fail Interrupt Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : OK
no status set
0b1 : FAIL
at least one status set
End of enumeration elements list.
SYS_OTWARN_IS : System Overtemperature Prewarning (ADC2, Channel 8) interrupt status
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : OK
no interrupt status set
0b1 : FAIL
at least one interrupt status set
End of enumeration elements list.
SYS_OT_IS : System Overtemperature Shutdown (ADC2, Channel 8) interrupt status
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : OK
no interrupt status set
0b1 : FAIL
at least one interrupt status set
End of enumeration elements list.
CLKWDT_IS : Clock Watchdog Interrupt Status
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
0b0 : OK
no interrupt status set
0b1 : FAIL
at least one interrupt status set
End of enumeration elements list.
VREF1V2_UV_IS : 8 Bit ADC2 Reference Undervoltage (ADC2, Channel 5) interrupt status
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : OK
no interrupt status set
0b1 : FAIL
at least one interrupt status set
End of enumeration elements list.
VREF1V2_OV_IS : 8 Bit ADC2 Reference Overvoltage (ADC2, Channel 5) interrupt status
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
0b0 : OK
no interrupt status set
0b1 : FAIL
at least one interrupt status set
End of enumeration elements list.
SYS_SUPPLY_IS : System Supply Interrupt Status
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
0b0 : OK
no interrupt status set
0b1 : FAIL
at least one interrupt status set
End of enumeration elements list.
LIN_FAIL_STS : LIN Fail Status
bits : 16 - 15 (0 bit)
access : read-only
Enumeration:
0b0 : OK
no status set
0b1 : FAIL
at least one status set
End of enumeration elements list.
CP_FAIL_STS : Charge Pump Fail Status
bits : 17 - 16 (0 bit)
access : read-only
Enumeration:
0b0 : OK
no status set
0b1 : FAIL
at least one status set
End of enumeration elements list.
DRV_FAIL_STS : Gate Driver Fail Status
bits : 18 - 17 (0 bit)
access : read-only
Enumeration:
0b0 : OK
no status set
0b1 : FAIL
at least one status set
End of enumeration elements list.
HS_FAIL_STS : High Side Driver Fail Status
bits : 19 - 18 (0 bit)
access : read-only
Enumeration:
0b0 : OK
no status set
0b1 : FAIL
at least one status set
End of enumeration elements list.
SYS_OTWARN_STS : System Overtemperature Prewarning (ADC2, Channel 6) status
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
0b0 : OK
no status set
0b1 : FAIL
at least one status set
End of enumeration elements list.
SYS_OT_STS : System Overtemperature Shutdown (ADC2, Channel 6) status
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
0b0 : OK
no status set
0b1 : FAIL
at least one status set
End of enumeration elements list.
VREF1V2_UV_STS : 8 Bit ADC2 Reference Undervoltage (ADC2, Channel 5) interrstatus
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
0b0 : OK
no interrupt status set
0b1 : FAIL
at least one interrupt status set
End of enumeration elements list.
VREF1V2_OV_STS : 8 Bit ADC2 Reference Overvoltage (ADC2, Channel 5) interrupt status
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
0b0 : OK
no interrupt status set
0b1 : FAIL
at least one interrupt status set
End of enumeration elements list.
SYS_SUPPLY_STS : System Supply Status
bits : 30 - 29 (0 bit)
access : read-only
Enumeration:
0b0 : OK
no status set
0b1 : FAIL
at least one status set
End of enumeration elements list.
System Supply Interrupt Status Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VS_UV_IS : VS Undervoltage Interrupt Status (ADC2 channel 0)
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : No Undervoltage Interrupt
occurred
0b1 : Undervoltage Interrupt
occurred
End of enumeration elements list.
VDDEXT_UV_IS : VDDEXT Undervoltage Interrupt Status (ADC2 channel 3)
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : No Undervoltage Interrupt
occurred
0b1 : Undervoltage Interrupt
occurred
End of enumeration elements list.
VDD5V_UV_IS : VDDP Undervoltage Interrupt Status (ADC2 channel 4)
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : No Undervoltage Interrupt
occurred
0b1 : Undervoltage Interrupt
occurred
End of enumeration elements list.
VDD1V5_UV_IS : VDDC Undervoltage Interrupt Status (ADC2 channel 6)
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : No Undervoltage Interrupt
occurred
0b1 : Undervoltage Interrupt
occurred
End of enumeration elements list.
VS_OV_IS : VS Overvoltage Interrupt Status (ADC2 channel 0)
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : No Overvoltage Interrupt
occurred
0b1 : Overvoltage Interrupt
occurred
End of enumeration elements list.
VDDEXT_OV_IS : VDDEXT Overvoltage Interrupt Status (ADC2 channel 3)
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
0b0 : No Overvoltage Interrupt
occurred
0b1 : Overvoltage Interrupt
occurred
End of enumeration elements list.
VDD5V_OV_IS : VDDP Overvoltage Interrupt Status (ADC2 channel 4)
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : No Overvoltage Interrupt
occurred
0b1 : Overvoltage Interrupt
occurred
End of enumeration elements list.
VDD1V5_OV_IS : VDDC Overvoltage Interrupt Status (ADC2 channel 6)
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
0b0 : No Overvoltage Interrupt
occurred
0b1 : Overvoltage Interrupt
occurred
End of enumeration elements list.
VS_UV_STS : VS Undervoltage Status (ADC2 channel 0)
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
0b0 : No Undervoltage
occurred
0b1 : Undervoltage
occurred
End of enumeration elements list.
VDDEXT_UV_STS : VDDEXT Undervoltage Status (ADC2 channel 3)
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
0b0 : No Undervoltage
occurred
0b1 : Undervoltage
occurred
End of enumeration elements list.
VDD5V_UV_STS : VDDP Undervoltage Status (ADC2 channel 4)
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
0b0 : No Undervoltage
occurred
0b1 : Undervoltage
occurred
End of enumeration elements list.
VDD1V5_UV_STS : VDDC Undervoltage Status (ADC2 channel 6)
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
0b0 : No Undervoltage
occurred
0b1 : Undervoltage
occurred
End of enumeration elements list.
VS_OV_STS : VS Overvoltage Status (ADC2 channel 0)
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
0b0 : No Overvoltage
occurred
0b1 : Overvoltage
occurred
End of enumeration elements list.
VDDEXT_OV_STS : VDDEXT Overvoltage Status (ADC2 channel 3)
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
0b0 : No Overvoltage
occurred
0b1 : Overvoltage
occurred
End of enumeration elements list.
VDD5V_OV_STS : VDDP Overvoltage Status (ADC2 channel 4)
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
0b0 : No Overvoltage
occurred
0b1 : Overvoltage
occurred
End of enumeration elements list.
VDD1V5_OV_STS : VDDC Overvoltage Status (ADC2 channel 6)
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
0b0 : No Overvoltage
occurred
0b1 : Overvoltage
occurred
End of enumeration elements list.
System Supply Interrupt Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VS_UV_IE : VS Undervoltage Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Interrupt is disabled
0b1 : Enable
Interrupt is enabled
End of enumeration elements list.
VDDEXT_UV_IE : VDDEXT Undervoltage Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Interrupt is disabled
0b1 : Enable
Interrupt is enabled
End of enumeration elements list.
VDD5V_UV_IE : VDDP Undervoltage Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Interrupt is disabled
0b1 : Enable
Interrupt is enabled
End of enumeration elements list.
VDD1V5_UV_IE : VDDC Undervoltage Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Interrupt is disabled
0b1 : Enable
Interrupt is enabled
End of enumeration elements list.
VS_OV_IE : VS Overvoltage Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Interrupt is disabled
0b1 : Enable
Interrupt is enabled
End of enumeration elements list.
VDDEXT_OV_IE : VDDEXT Overvoltage Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Interrupt is disabled
0b1 : Enable
Interrupt is enabled
End of enumeration elements list.
VDD5V_OV_IE : VDDP Overvoltage Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Interrupt is disabled
0b1 : Enable
Interrupt is enabled
End of enumeration elements list.
VDD1V5_OV_IE : VDDC Overvoltage Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
0b0 : Disable
Interrupt is disabled
0b1 : Enable
Interrupt is enabled
End of enumeration elements list.
System Supply Interrupt Status Clear Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VS_UV_ISC : VS Undervoltage Interrupt Status clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VDDEXT_UV_ISC : VDDEXT Undervoltage Interrupt Status clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VDD5V_UV_ISC : VDDP Undervoltage Interrupt Status clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VDD1V5_UV_ISC : VDDC Undervoltage Interrupt Status clear
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VS_OV_ISC : VS Overvoltage Interrupt Status clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VDDEXT_OV_ISC : VDDEXT Overvoltage Interrupt Status clear
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VDD5V_OV_ISC : VDDP Overvoltage Interrupt Status clear
bits : 12 - 11 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VDD1V5_OV_ISC : VDDC Overvoltage Interrupt Status clear
bits : 14 - 13 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VS_UV_SC : VS Undervoltage Status clear
bits : 16 - 15 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VDDEXT_UV_SC : VDDEXT Undervoltage Status clear
bits : 19 - 18 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VDD5V_UV_SC : VDDP Undervoltage Status clear
bits : 20 - 19 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VDD1V5_UV_SC : VDDC Undervoltage Status clear
bits : 22 - 21 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VS_OV_SC : VS Overvoltage Status clear
bits : 24 - 23 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VDDEXT_OV_SC : VDDEXT Overvoltage Status clear
bits : 27 - 26 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VDD5V_OV_SC : VDDP Overvoltage Status clear
bits : 28 - 27 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
VDD1V5_OV_SC : VDDC Overvoltage Status clear
bits : 30 - 29 (0 bit)
access : write-only
Enumeration:
0b0 : No Clear
None
0b1 : Clear
None
End of enumeration elements list.
System Interrupt Control Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYS_OTWARN_IE : System Overtemperature Prewarning Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : Interrupt is disabled
None
0b1 : Interrupt is enabled
None
End of enumeration elements list.
SYS_OT_IE : System Overtemperature Shutdown Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : Interrupt is disabled
None
0b1 : Interrupt is enabled
None
End of enumeration elements list.
VREF1V2_UV_IE : 8 Bit ADC2 Reference Undervoltage Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : Interrupt is disabled
None
0b1 : Interrupt is enabled
None
End of enumeration elements list.
VREF1V2_OV_IE : 8 Bit ADC2 Reference Overvoltage Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
0b0 : Interrupt is disabled
None
0b1 : Interrupt is enabled
None
End of enumeration elements list.
Power Control Unit Control Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKWDT_SD_DIS : Power Modules Clock Watchdog Shutdown Disable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : Shutdown Enable
Power Devices will be switched off when Clock Watchdog.
0b1 : Shutdown Disable
Power Devices will not be shutdown when Clock Watchdog occurs
End of enumeration elements list.
FAIL_PS_DIS : Disable LIN Tx and HS and because of Overtemperature Warning or VS OV/UV
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : Switch off Enabled
LIN Tx andHS will be turned off when Overtemperature Warning occurs
0b1 : Switch off Disabled
LIN Tx andHS will be kept on when Overtemperature Warning occurs
End of enumeration elements list.
LIN_VS_UV_SD_DIS : LIN Module VS Undervoltage Transmitter Shutdown
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
Automatic Shutdown for Power modules in case of VS Undervoltage enabled
0b1 : Disable
Automatic Shutdown for Power modules in case of VS Undervoltage disabled
End of enumeration elements list.
SYS_VS_UV_SLM_DIS : VS Undervoltage Shutdown for Peripherals Disable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
Automatic Shutdown for Power modules in case of VS Undervoltage enabled
0b1 : Disable
Automatic Shutdown for Power modules in case of VS Undervoltage disabled
End of enumeration elements list.
SYS_VS_OV_SLM_DIS : VS Overvoltage Shutdown for Peripherals Disable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
Automatic Shutdown for Power modules in case of VS Overvoltage enabled
0b1 : Disable
Automatic Shutdown for Power modules in case of VS Overvoltage disabled
End of enumeration elements list.
SYS_OTWARN_PS_DIS : System Overtemperature Warning Power Switches Shutdown Disable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
Automatic Shutdown Signal for Power Switches in case of system overtemperature warning enable
0b1 : Disable
Automatic Shutdown Signal for Power Switches in case of system overtemperature warning enable
End of enumeration elements list.
CLKLOSS_SD_DIS : System Loss of Clock Shutdown Disable (AMCLK3)
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
Automatic Shutdown Signal for Power Switches in case of loss of clock
0b1 : Disable
Automatic Shutdown Signal for Power Switches in case of loss of clock
End of enumeration elements list.
CLKWDT_RES_SD_DIS : Clock Watchdog Reset Disable
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
Clock Watchdog Reset Enable
0b1 : Disable
Clock Watchdog Reset Disable
End of enumeration elements list.
CLKLOSS_RES_SD_DIS : Loss of Clock Reset Disable
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
0b0 : Enable
Loss of Clock Reset Enable
0b1 : Disable
Loss of Clock Reset Disable
End of enumeration elements list.
WDT1 Watchdog Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDP_SEL : Watchdog Period Selection and trigger
bits : 0 - 4 (5 bit)
access : read-write
Enumeration:
0x00 : SOW_TRIG
trigger short open window
0x01 : WP_1
Watchdog period 16 ms
0x02 : WP_2
Watchdog period 32 ms
0x03 : WP_3
Watchdog period 48 ms, ...
0x3F : WP_63
Watchdog period 1008 ms
End of enumeration elements list.
SOWCONF : Short Open Window Configuration
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0x0 : DIS
Short Open Windows disabled
0x1 : SOW1
one successive Short Open Window allowed
0x2 : SOW2
two successive Short Open Windows allowed
0x3 : SOW3
three successive Short Open Windows allowed
End of enumeration elements list.
Analog Module Clock Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKWDT_PD_N : Clock Watchdog Powerdown
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
Clock Watchdog disabled
0b1 : ENABLE
Clock Watchdog enabled
End of enumeration elements list.
System Tick Calibration Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STCALIB : System Tick Calibration
bits : 0 - 24 (25 bit)
access : read-write
Analog Module Clock Limit Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AMCLK1_UP_TH : Analog Module Clock 1 (MI_CLK) Upper Limit Threshold
bits : 0 - 4 (5 bit)
access : read-write
AMCLK1_UP_HYS : Analog Module Clock 1 (MI_CLK) Upper Hysteresis
bits : 6 - 6 (1 bit)
access : read-write
AMCLK1_LOW_TH : Analog Module Clock 1 (MI_CLK) Lower Limit Threshold
bits : 8 - 12 (5 bit)
access : read-write
AMCLK1_LOW_HYS : Analog Module Clock 1 (MI_CLK) Lower Hysteresis
bits : 14 - 14 (1 bit)
access : read-write
AMCLK2_UP_TH : Analog Module Clock 2 (TFILT_CLK) Upper Limit Threshold
bits : 16 - 20 (5 bit)
access : read-write
AMCLK2_UP_HYS : Analog Module Clock 2 (TFILT_CLK) Upper Hysteresis
bits : 22 - 22 (1 bit)
access : read-write
AMCLK2_LOW_TH : Analog Module Clock 2 (TFILT_CLK) Lower Limit Threshold
bits : 24 - 28 (5 bit)
access : read-write
AMCLK2_LOW_HYS : Analog Module Clock 2 (TFILT_CLK) Lower Hysteresis
bits : 30 - 30 (1 bit)
access : read-write
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