Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected
Port Input Select Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIS_0 : Master Mode Input Select Bit 0 (Master Mode only)
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : SSCx_M_MRST
(x = 1 or 2, dependant form current SSC), see .
0b1 : SSC12_M_MRST_x
(x=0 or 1). See .
End of enumeration elements list.
SIS : Slave Mode Input Select (Slave Mode only)
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : SSCx_S_MTSR
(x = 1 or 2, dependant form current SSC), see .
0b1 : SSC12_S_MTSR_x
(x=0 or 1). See .
End of enumeration elements list.
CIS : Clock Input Select (Slave Mode only)
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : SSCx_S_SCK
(x = 1 or 2, dependant form current SSC), see .
0b1 : SSC12_S_SCK_x
(x=0 or 1). See .
End of enumeration elements list.
MIS_1 : Master Mode Input Select Bit 1 (Master Mode only)
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Default, Inputs selected according to MIS_0.
0b1 : value2
Do not use, Connects to unused pins.
End of enumeration elements list.
GIS : Global SSC12 Input Select
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Inputs SSC12_S_SCK_0, SSC12_S_MTSR_0, and SSC12_M_MRST_0 are selected if CIS, SIS or MIS_O is 1.
0b1 : value2
Inputs SSC12_S_SCK_1, SSC12_S_MTSR_1, and SSC12_M_MRST_1 are selected if CIS, SIS or MIS_O is 1. See
End of enumeration elements list.
Baud Rate Timer Reload Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BR_VALUE : Baud Rate Timer/Reload Register Value
bits : 0 - 14 (15 bit)
access : read-write
Interrupt Status Register Clear
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TECLR : Transmit Error Flag Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
0b0 : NO
No error clear.
0b1 : CLEAR
Error clear.
End of enumeration elements list.
RECLR : Receive Error Flag Clear
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
0b0 : NO
No error clear.
0b1 : CLEAR
Error clear.
End of enumeration elements list.
PECLR : Phase Error Flag Clear
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
0b0 : NO
No error clear.
0b1 : CLEAR
Error clear.
End of enumeration elements list.
BECLR : Baud Rate Error Flag Clear
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
0b0 : NO
No error clear.
0b1 : CLEAR
Error clear.
End of enumeration elements list.
Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BM : Data Width Selection
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0b0001 : 2
Transfer Data Width is 2 (BM+1).
0b1111 : 16
Transfer Data Width is 16 bits (BM+1).
End of enumeration elements list.
HB : Heading Control
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : LSB
Transmit/Receive LSB First.
0b1 : MSB
Transmit/Receive MSB First.
End of enumeration elements list.
PH : Clock Phase Control
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : SHIFT
transmit data on the leading clock edge, latch on trailing edge.
0b1 : LATCH
receive data on leading clock edge, shift on trailing edge.
End of enumeration elements list.
PO : Clock Polarity Control
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : LOW
Idle clock line is low, leading clock edge is low-to-high transition.
0b1 : HIGH
Idle clock line is high, leading clock edge is high-to-low transition.
End of enumeration elements list.
LB : Loop Back Control
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : NORMAL
output.
0b1 : LB
Receive input is connected with transmit output (half-duplex mode).
End of enumeration elements list.
TEN : Transmit Error Enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : IGNORE
transmit errors.
0b1 : CHECK
transmit errors.
End of enumeration elements list.
REN : Receive Error Enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : IGNORE
receive errors.
0b1 : CHECK
receive errors.
End of enumeration elements list.
PEN : Phase Error Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
0b0 : IGNORE
phase errors.
0b1 : CHECK
phase errors.
End of enumeration elements list.
BEN : Baud Rate Error Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
0b0 : IGNORE
baud rate errors.
0b1 : CHECK
baud rate errors.
End of enumeration elements list.
AREN : Automatic Reset Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : N/A
No additional action upon a baud rate error.
0b1 : RESET
The SSC is automatically reset upon a baud rate error.
End of enumeration elements list.
MS : Master Select
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
0b0 : SLAVE
Mode. Operate on shift clock received via SCLK.
0b1 : MASTER
Mode. Generate shift clock and output it via SCLK.
End of enumeration elements list.
EN : Enable Bit
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
0b0 : Programming Mode
Transmission and reception disabled. Access to control bits.
0b1 : Operating Mode
Transmission and reception enabled. Access to status flags and M/S control.
End of enumeration elements list.
BC : Bit Count Field
bits : 16 - 18 (3 bit)
access : read-only
TE : Transmit Error Flag
bits : 24 - 23 (0 bit)
access : read-only
Enumeration:
0b0 : NO
error.
0b1 : ERROR
Transfer starts with the slave's transmit buffer not being updated.
End of enumeration elements list.
RE : Receive Error Flag
bits : 25 - 24 (0 bit)
access : read-only
Enumeration:
0b0 : NO
error.
0b1 : ERROR
Reception completed before the receive buffer was read.
End of enumeration elements list.
PE : Phase Error Flag
bits : 26 - 25 (0 bit)
access : read-only
Enumeration:
0b0 : NO
error.
0b1 : ERROR
Received data changes around sampling clock edge.
End of enumeration elements list.
BE : Baud Rate Error Flag
bits : 27 - 26 (0 bit)
access : read-only
Enumeration:
0b0 : NO
error.
0b1 : ERROR
More than factor 2 or 0.5 between slave's actual and expected baud rate.
End of enumeration elements list.
BSY : Busy Flag
bits : 28 - 27 (0 bit)
access : read-only
Transmitter Buffer Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TB_VALUE : Transmit Data Register Value
bits : 0 - 14 (15 bit)
access : read-write
Receiver Buffer Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RB_VALUE : Receive Data Register Value
bits : 0 - 14 (15 bit)
access : read-only
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