\n
address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
Debug System ROM ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MANUFID : Manufactory Identity
bits : 1 - 10 (10 bit)
access : read-only
PARTNO : Part Number
bits : 12 - 26 (15 bit)
access : read-only
VERSION : Product version
bits : 28 - 30 (3 bit)
access : read-only
SSW Register 0
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DAT : SSW Data
bits : 0 - 30 (31 bit)
access : read-write
Password Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Bit Protection Scheme Control Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
Scheme disabled - direct access to the protected bits is allowed.
#11 : value2
Scheme enabled - the bit field PASS has to be written with the passwords to open and close the access to the protected bits. (Default)
End of enumeration elements list.
PROTS : Bit Protection Signal Status Bit
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Software is able to write to all protected bits.
#1 : value2
Software is unable to write to any of the protected bits.
End of enumeration elements list.
PASS : Password Bits
bits : 3 - 6 (4 bit)
access : write-only
Enumeration:
#11000 : value1
Enables writing of the bit field MODE.
#10011 : value2
Opens access to writing of all protected bits.
#10101 : value3
Closes access to writing of all protected bits.
End of enumeration elements list.
CCU Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GSC40 : Global Start Control CCU40
bits : 0 - -1 (0 bit)
access : read-write
Chip ID Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IDCHIP : CHIP ID
bits : 0 - 30 (31 bit)
access : read-only
Mirror Update Status Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RTC_CTR : RTC CTR Mirror Register Update Status
bits : 0 - -1 (0 bit)
access : read-only
RTC_ATIM0 : RTC ATIM0 Mirror Register Update Status
bits : 1 - 0 (0 bit)
access : read-only
RTC_ATIM1 : RTC ATIM1 Mirror Register Update Status
bits : 2 - 1 (0 bit)
access : read-only
RTC_TIM0 : RTC TIM0 Mirror Register Update Status
bits : 3 - 2 (0 bit)
access : read-only
RTC_TIM1 : RTC TIM1 Mirror Register Update Status
bits : 4 - 3 (0 bit)
access : read-only
Parity Memory Test Select Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MTENS : Parity Test Enable Control for 16kbytes SRAM
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
standard operation
#1 : value2
generate an inverted parity bit during a write operation
End of enumeration elements list.
SCU Module ID Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_REV : Module Revision Number
bits : 0 - 6 (7 bit)
access : read-only
MOD_TYPE : Module Type
bits : 8 - 14 (7 bit)
access : read-only
MOD_NUMBER : Module Number Value
bits : 16 - 30 (15 bit)
access : read-only
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