\n
address_offset : 0x0 Bytes (0x0)
size : 0x60 byte (0x0)
mem_usage : registers
protection : not protected
Event Flag Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVEOC : Divider End of Calculation Event Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Divider end of calculation event has not been detected.
#1 : value2
Divider end of calculation event has been detected.
End of enumeration elements list.
DIVERR : Divider Error Event Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
Divider error event has not been detected
#1 : value2
Divider error event has been detected
End of enumeration elements list.
CDEOC : CORDIC End of Calculation Event Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
CORDIC end of calculation event has not been detected.
#1 : value2
CORDIC end of calculation event has been detected.
End of enumeration elements list.
CDERR : CORDIC Error Event Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
CORDIC error event has not been detected
#1 : value2
CORDIC error event has been detected
End of enumeration elements list.
Event Flag Set Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVEOCS : Divider End of Calculation Event Flag Set
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Sets the Divider end of calculation event flag in EVFR register. Interrupt will be generated if enabled in EVIER register.
End of enumeration elements list.
DIVERRS : Divider Error Event Flag Set
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Sets the Divider error event flag in EVFR register. Interrupt will be generated if enabled in EVIER register.
End of enumeration elements list.
CDEOCS : CORDIC Event Flag Set
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Sets the CORDIC end of calculation event flag in EVFR register. Interrupt will be generated if enabled in EVIER register.
End of enumeration elements list.
CDERRS : CORDIC Error Event Flag Set
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Sets the CORDIC error event flag in EVFR register. Interrupt will be generated if enabled in EVIER register.
End of enumeration elements list.
Event Flag Clear Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVEOCC : Divider End of Calculation Event Flag Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Clears the Divider end of calculation event flag in EVFR register.
End of enumeration elements list.
DIVERRC : Divider Error Event Flag Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Clears the Divider error event flag in EVFR register.
End of enumeration elements list.
CDEOCC : CORDIC End of Calculation Event Flag Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Clears the CORDIC end of calculation event flag in EVFR register.
End of enumeration elements list.
CDERRC : CORDIC Error Event Flag Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Clears the CORDIC error event flag in EVFR register.
End of enumeration elements list.
Dividend Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Dividend Value
bits : 0 - 30 (31 bit)
access : read-write
Divisor Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Divisor Value
bits : 0 - 30 (31 bit)
access : read-write
Quotient Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Quotient Value
bits : 0 - 30 (31 bit)
access : read-only
Remainder Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VAL : Remainder Value
bits : 0 - 30 (31 bit)
access : read-only
Divider Status Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSY : Busy Indication
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Divider is not running any division operation.
#1 : value2
Divider is still running a division operation.
End of enumeration elements list.
Divider Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ST : Start Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
No effect
#1 : value2
Start the division operation when STMODE=1#
End of enumeration elements list.
STMODE : Start Mode
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Calculation is automatically started with a write to DVS register
#1 : value2
Calculation is started by setting the ST bit to 1
End of enumeration elements list.
USIGN : Unsigned Division Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Signed division is selected
#1 : value2
Unsigned division is selected
End of enumeration elements list.
DIVMODE : Division Mode
bits : 3 - 3 (1 bit)
access : read-write
Enumeration:
#00 : value1
32-bit divide by 32-bit
#01 : value2
32-bit divide by 16-bit
#10 : value3
16-bit divide by 16-bit
End of enumeration elements list.
QSCNT : Quotient Shift Count
bits : 8 - 11 (4 bit)
access : read-write
QSDIR : Quotient Shift Direction
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
Left shift
#1 : value2
Right shift
End of enumeration elements list.
DVDSLC : Dividend Shift Left Count
bits : 16 - 19 (4 bit)
access : read-write
DVSSRC : Divisor Shift Right Count
bits : 24 - 27 (4 bit)
access : read-write
Global Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVDRC : Dividend Register Result Chaining
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
No result chaining is selected
#001 : value2
QUOT register is the selected source
#010 : value3
RMD register is the selected source
#011 : value4
CORRX is the selected source
#100 : value5
CORRY is the selected source
#101 : value6
CORRZ is the selected source
End of enumeration elements list.
DVSRC : Divisor Register Result Chaining
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#000 : value1
No result chaining is selected
#001 : value2
QUOT register is the selected source
#010 : value3
RMD register is the selected source
#011 : value4
CORRX is the selected source
#100 : value5
CORRY is the selected source
#101 : value6
CORRZ is the selected source
End of enumeration elements list.
CORDXRC : CORDX Register Result Chaining
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : value1
No result chaining is selected
#01 : value2
QUOT register is the selected source
#10 : value3
RMD register is the selected source
End of enumeration elements list.
CORDYRC : CORDY Register Result Chaining
bits : 9 - 9 (1 bit)
access : read-write
Enumeration:
#00 : value1
No result chaining is selected
#01 : value2
QUOT register is the selected source
#10 : value3
RMD register is the selected source
End of enumeration elements list.
CORDZRC : CORDZ Register Result Chaining
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#00 : value1
No result chaining is selected
#01 : value2
QUOT register is the selected source
#10 : value3
RMD register is the selected source
End of enumeration elements list.
SUSCFG : Suspend Mode Configuration
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : value1
Suspend mode is never entered.
#01 : value2
Hard suspend mode will be entered when CPU is halted.
#10 : value3
Soft suspend mode will be entered when CPU is halted.
End of enumeration elements list.
CORDIC Status and Data Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BSY : Busy Indication
bits : 0 - -1 (0 bit)
access : read-only
KEEPX : Last X Result as Initial Data for New Calculation
bits : 5 - 4 (0 bit)
access : read-write
KEEPY : Last Y Result as Initial Data for New Calculation
bits : 6 - 5 (0 bit)
access : read-write
KEEPZ : Last Z Result as Initial Data for New Calculation
bits : 7 - 6 (0 bit)
access : read-write
CORDIC Control Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ST : Start Calculation
bits : 0 - -1 (0 bit)
access : read-write
MODE : Operating Mode
bits : 1 - 1 (1 bit)
access : read-write
Enumeration:
#00 : value1
Linear Mode
#01 : value2
Circular Mode (default)
#11 : value4
Hyperbolic Mode
End of enumeration elements list.
ROTVEC : Rotation Vectoring Selection
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Vectoring Mode (default)
#1 : value2
Rotation Mode
End of enumeration elements list.
ST_MODE : Start Method
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Auto start of calculation after write access to X parameter data register CORDX(default).
#1 : value2
Start calculation only after bit ST is set
End of enumeration elements list.
X_USIGN : Result Data Format for X in Circular Vectoring Mode
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Signed, twos complement
#1 : value2
Unsigned (default)
End of enumeration elements list.
MPS : X and Y Magnitude Prescaler
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : value1
Divide by 1
#01 : value2
Divide by 2 (default)
#10 : value3
Divide by 4
#11 : value4
Reserved, retain the last MPS setting
End of enumeration elements list.
CORDIC X Data Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Initial X Parameter Data
bits : 8 - 30 (23 bit)
access : read-write
CORDIC Y Data Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Initial Y Parameter Data
bits : 8 - 30 (23 bit)
access : read-write
CORDIC Z Data Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Initial Z Parameter Data
bits : 8 - 30 (23 bit)
access : read-write
CORDIC X Result Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESULT : X Calculation Result
bits : 8 - 30 (23 bit)
access : read-only
CORDIC Y Result Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESULT : Y Calculation Result
bits : 8 - 30 (23 bit)
access : read-only
CORDIC Z Result Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RESULT : Z Calculation Result
bits : 8 - 30 (23 bit)
access : read-only
Module Identification Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_REV : Module Revision Number
bits : 0 - 6 (7 bit)
access : read-only
MOD_TYPE : Module Type
bits : 8 - 14 (7 bit)
access : read-only
MOD_NUMBER : Module Number Value
bits : 16 - 30 (15 bit)
access : read-only
Event Interrupt Enable Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIVEOCIEN : Divider End of Calculation Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Divider end of calculation interrupt generation is disabled.
#1 : value2
Divider end of calculation interrupt generation is enabled.
End of enumeration elements list.
DIVERRIEN : Divider Error Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Divider error interrupt generation is disabled
#1 : value2
Divider error interrupt generation is enabled
End of enumeration elements list.
CDEOCIEN : CORDIC End of Calculation Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
CORDIC end of calculation interrupt generation is disabled.
#1 : value2
CORDIC end of calculation interrupt generation is enabled.
End of enumeration elements list.
CDERRIEN : CORDIC Error Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
CORDIC error interrupt generation is disabled
#1 : value2
CORDIC error interrupt generation is enabled
End of enumeration elements list.
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