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SCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ANATSECTRL

ANATSEIH

ANATSEIL

ANATSEMON

ANAVDEL

ANAOFFSET

ANASYNC1

ANASYNC2

ANAOSCLPCTRL

ANAOSCHPCTRL


ANATSECTRL

Temperature Sensor Control Register
address_offset : 0x24 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANATSECTRL ANATSECTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSE_EN

TSE_EN : Temperature sensor enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Temperature sensor is disabled

#1 : value2

Temperature sensor is switched on

End of enumeration elements list.


ANATSEIH

Temperature Sensor High Temperature Interrupt Register
address_offset : 0x30 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANATSEIH ANATSEIH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSE_IH

TSE_IH : Counter value for high temperature interrupt
bits : 0 - 14 (15 bit)
access : read-write


ANATSEIL

Temperature Sensor Low Temperature Interrupt Register
address_offset : 0x34 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANATSEIL ANATSEIL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSE_IL

TSE_IL : Counter value for low temperature interrupt
bits : 0 - 14 (15 bit)
access : read-write


ANATSEMON

Temperature Sensor Counter2 Monitor Register
address_offset : 0x40 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANATSEMON ANATSEMON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TSE_MON

TSE_MON : Result values; loaded by TSE_DONE
bits : 0 - 14 (15 bit)
access : read-only


ANAVDEL

Voltage Detector Control Register
address_offset : 0x50 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANAVDEL ANAVDEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VDEL_SELECT VDEL_TIM_ADJ VDEL_EN

VDEL_SELECT : VDEL Range Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

2.25V

#01 : value2

3.0V

#10 : value3

4.4V

End of enumeration elements list.

VDEL_TIM_ADJ : VDEL Timing Setting
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : value1

typ 1us - slowest response time

#01 : value2

typ 500n

#10 : value3

typ 250n

#11 : value4

no delay - fastest response time.

End of enumeration elements list.

VDEL_EN : VDEL unit Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

VDEL is disabled

#1 : value2

VDEL is active

End of enumeration elements list.


ANAOFFSET

DCO1 Offset Register
address_offset : 0x6C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANAOFFSET ANAOFFSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADJL_OFFSET

ADJL_OFFSET : ADJL Offset register
bits : 0 - 5 (6 bit)
access : read-write

Enumeration:

0x00 : value1

- 3.xx%, typ.

0x3F : value2

DCO1 ADJL value is reduced by 1 step (DCO_ADJL - 1).

0x40 : value3

0, DCO_ADJL is not changed, default

0x41 : value4

DCO1 ADJL value is increased by 1 step (DCO_ADJL + 1)

0x7F : value5

+ 3.xx%, typ.

End of enumeration elements list.


ANASYNC1

DCO1 Sync Control Register 1
address_offset : 0x78 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANASYNC1 ANASYNC1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYNC_PRELOAD SYNC_DCO_EN XTAL_SEL

SYNC_PRELOAD : Counter target value, which defines the update cycle
bits : 0 - 12 (13 bit)
access : read-write

Enumeration:

0x1FFF : value1

Longest integration time = best accuracy

End of enumeration elements list.

SYNC_DCO_EN : DCO1 synchronization feature enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : value1

No DCO1 synchronization via an external clock source. This option is used for the DCO1 calibration using the temperature sensor.

#1 : value2

DCO1 gets synchronized via an external clock source.

End of enumeration elements list.

XTAL_SEL : Oscillator Source select
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : value1

OSC_LP is selected

#1 : value2

OSC_HP is selected

End of enumeration elements list.


ANASYNC2

DCO1 Sync Control Register 2
address_offset : 0x7C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANASYNC2 ANASYNC2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRESCALER SYNC_READY

PRESCALER : Prescaler value
bits : 0 - 9 (10 bit)
access : read-write

Enumeration:

0x000 : value1

Bypass: Internal sync counter frequency = crystal frequency

0x001 : value2

DIV1: Internal sync counter feed freq. = crystal frequency/1

0x002 : value3

DIV2: Internal sync counter feed freq. = crystal frequency/2

0x7FF : value4

Maximum divider value (for best accuracy, but slowest response)

End of enumeration elements list.

SYNC_READY : DCO1 frequency reached its target value
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : value1

Actual DCO1 frequency is out of targe

#1 : value2

DCO1 is synchronized to the XTAL frequency

End of enumeration elements list.


ANAOSCLPCTRL

OSC_LP Control Register
address_offset : 0x8C Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANAOSCLPCTRL ANAOSCLPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODE

MODE : OSC_LP Oscillator Mode
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Oscillator is enabled and in operation mode (OSC mode)

#01 : value2

Oscillator is enabled, shaper is bypassed

#10 : value3

Oscillator is in power down mode

#11 : value4

Oscillator is in power down mode , Pad can be used in GPIO mode

End of enumeration elements list.


ANAOSCHPCTRL

OSC_HP Control Register
address_offset : 0x90 Bytes (0x0)
size : 16 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ANAOSCHPCTRL ANAOSCHPCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SHBY GAINSEL MODE HYSCTRL

SHBY : Shaper Bypass Mode
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

The shaper is not bypassed

#1 : value2

The shaper is bypassed

End of enumeration elements list.

GAINSEL : OSC_HP Oscillator Gain Selection
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : value1

Gain control is configured for frequencies from 4 MHz to y1 MHz

#01 : value2

Gain control is configured for frequencies from 4 MHz to y2 MHz

#10 : value3

Gain control is configured for frequencies from 4 MHz to 20 MHz

End of enumeration elements list.

MODE : OSC_HP Oscillator Mode
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Oscillator is enabled and in active power mode with shaper enabled (OSC mode)

#01 : value2

Oscillator in power down mode with shaper enabled (External Clock Input Mode).

#10 : value3

Oscillator is enabled with shaper disabled. No clock output is available unless the shaper is bypass (SHBY=1)

#11 : value4

Oscillator is in power down mode with shaper disabled. Pad can be used in GPIO mode.

End of enumeration elements list.

HYSCTRL : Shaper Hystersis Mode
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

External clock frequency < 20MHz.

#1 : value2

External clock frequency > 20MHz

End of enumeration elements list.



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