\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
control register 1
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPTURE : Capture enable
bits : 0 - 0 (1 bit)
CM : Capture mode
bits : 1 - 1 (1 bit)
CROP : Crop feature
bits : 2 - 2 (1 bit)
JPEG : JPEG format
bits : 3 - 3 (1 bit)
ESS : Embedded synchronization select
bits : 4 - 4 (1 bit)
PCKPOL : Pixel clock polarity
bits : 5 - 5 (1 bit)
HSPOL : Horizontal synchronization polarity
bits : 6 - 6 (1 bit)
VSPOL : Vertical synchronization polarity
bits : 7 - 7 (1 bit)
FCRC : Frame capture rate control
bits : 8 - 9 (2 bit)
EDM : Extended data mode
bits : 10 - 11 (2 bit)
ENABLE : DCMI enable
bits : 14 - 14 (1 bit)
BSM : Byte Select mode
bits : 16 - 17 (2 bit)
OEBS : Odd/Even Byte Select (Byte Select Start)
bits : 18 - 18 (1 bit)
LSM : Line Select mode
bits : 19 - 19 (1 bit)
OELS : Odd/Even Line Select (Line Select Start)
bits : 20 - 20 (1 bit)
masked interrupt status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRAME_MIS : Capture complete masked interrupt status
bits : 0 - 0 (1 bit)
OVR_MIS : Overrun masked interrupt status
bits : 1 - 1 (1 bit)
ERR_MIS : Synchronization error masked interrupt status
bits : 2 - 2 (1 bit)
VSYNC_MIS : VSYNC masked interrupt status
bits : 3 - 3 (1 bit)
LINE_MIS : Line masked interrupt status
bits : 4 - 4 (1 bit)
interrupt clear register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
FRAME_ISC : Capture complete interrupt status clear
bits : 0 - 0 (1 bit)
OVR_ISC : Overrun interrupt status clear
bits : 1 - 1 (1 bit)
ERR_ISC : Synchronization error interrupt status clear
bits : 2 - 2 (1 bit)
VSYNC_ISC : Vertical synch interrupt status clear
bits : 3 - 3 (1 bit)
LINE_ISC : line interrupt status clear
bits : 4 - 4 (1 bit)
embedded synchronization code register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSC : Frame start delimiter code
bits : 0 - 7 (8 bit)
LSC : Line start delimiter code
bits : 8 - 15 (8 bit)
LEC : Line end delimiter code
bits : 16 - 23 (8 bit)
FEC : Frame end delimiter code
bits : 24 - 31 (8 bit)
embedded synchronization unmask register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FSU : Frame start delimiter unmask
bits : 0 - 7 (8 bit)
LSU : Line start delimiter unmask
bits : 8 - 15 (8 bit)
LEU : Line end delimiter unmask
bits : 16 - 23 (8 bit)
FEU : Frame end delimiter unmask
bits : 24 - 31 (8 bit)
crop window start
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HOFFCNT : Horizontal offset count
bits : 0 - 13 (14 bit)
VST : Vertical start line count
bits : 16 - 28 (13 bit)
crop window size
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CAPCNT : Capture count
bits : 0 - 13 (14 bit)
VLINE : Vertical line count
bits : 16 - 29 (14 bit)
data register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
Byte0 : Data byte 0
bits : 0 - 7 (8 bit)
Byte1 : Data byte 1
bits : 8 - 15 (8 bit)
Byte2 : Data byte 2
bits : 16 - 23 (8 bit)
Byte3 : Data byte 3
bits : 24 - 31 (8 bit)
status register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
HSYNC : HSYNC
bits : 0 - 0 (1 bit)
VSYNC : VSYNC
bits : 1 - 1 (1 bit)
FNE : FIFO not empty
bits : 2 - 2 (1 bit)
raw interrupt status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
FRAME_RIS : Capture complete raw interrupt status
bits : 0 - 0 (1 bit)
OVR_RIS : Overrun raw interrupt status
bits : 1 - 1 (1 bit)
ERR_RIS : Synchronization error raw interrupt status
bits : 2 - 2 (1 bit)
VSYNC_RIS : VSYNC raw interrupt status
bits : 3 - 3 (1 bit)
LINE_RIS : Line raw interrupt status
bits : 4 - 4 (1 bit)
interrupt enable register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FRAME_IE : Capture complete interrupt enable
bits : 0 - 0 (1 bit)
OVR_IE : Overrun interrupt enable
bits : 1 - 1 (1 bit)
ERR_IE : Synchronization error interrupt enable
bits : 2 - 2 (1 bit)
VSYNC_IE : VSYNC interrupt enable
bits : 3 - 3 (1 bit)
LINE_IE : Line interrupt enable
bits : 4 - 4 (1 bit)
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