Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Hibernate Domain Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPEV : Wake-up Pin Event Positive Edge
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Wake-up on positive edge pin event inactive
#1 : value2
Wake-up on positive edge pin event active
End of enumeration elements list.
ENEV : Wake-up Pin Event Negative Edge
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
Wake-up on negative edge pin event inactive
#1 : value2
Wake-up on negative edge pin event active
End of enumeration elements list.
RTCEV : RTC Event
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Wake-up on RTC event inactive
#1 : value2
Wake-up on RTC event active
End of enumeration elements list.
ULPWDG : ULP WDG Alarm Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
Watchdog alarm did not occur
#1 : value2
Watchdog alarm occurred
End of enumeration elements list.
HIBNOUT : Hibernate Control Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
Hibernate not driven active to pads
#1 : value2
Hibernate driven active to pads
End of enumeration elements list.
VBATPEV : Wake-Up on LPAC Positive Edge of VBAT Threshold Crossing
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : value1
Wake-up on rising above threshold event inactive
#1 : value2
Wake-up on rising above threshold event active
End of enumeration elements list.
VBATNEV : Wake-Up on LPAC Negative Edge of VBAT Threshold Crossing
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : value1
Wake-up on falling below threshold event inactive
#1 : value2
Wake-up on falling below threshold event active
End of enumeration elements list.
AHIBIO0PEV : Wake-Up on LPAC Positive Edge of HIB_IO_0 Threshold Crossing
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : value1
Wake-up on rising above threshold event inactive
#1 : value2
Wake-up on rising above threshold event active
End of enumeration elements list.
AHIBIO0NEV : Wake-Up on LPAC Negative Edge of HIB_IO_0 Threshold Crossing
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : value1
Wake-up on falling below threshold event inactive
#1 : value2
Wake-up on falling below threshold event active
End of enumeration elements list.
fOSI Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWD : Turn OFF the fOSI Clock Source
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Enabled
#1 : value2
Disabled
End of enumeration elements list.
OSC_ULP Status Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X1D : XTAL1 Data Value
bits : 0 - -1 (0 bit)
access : read-only
OSC_ULP Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
X1DEN : XTAL1 Data General Purpose Input Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Data input inactivated, power down
#1 : value2
Data input active
End of enumeration elements list.
MODE : Oscillator Mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
Oscillator is enabled, in operation
#01 : value2
Oscillator is enabled, in bypass mode
#10 : value3
Oscillator in power down
#11 : value4
Oscillator in power down, can be used as GPI
End of enumeration elements list.
Analog Wake-up Configuration Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CMPEN : Compare Enable for Input Selection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
Comparator permanently in power down
#001 : value2
Comparator activated for VBAT input
#010 : value3
Comparator activated for HIB_IO_0 input
#100 : value4
Comparator activated for HIB_IO_1 input
End of enumeration elements list.
TRIGSEL : Analog Compare Trigger Select
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
Sub-second interval counter
#001 : value2
RTC alarm event
#010 : value3
RTC periodic event
#011 : value4
On digital WKUP input positive edge event
#101 : value5
On digital WKUP input negative edge event
#110 : value6
Continuous measurement
#111 : value7
Single-shot on software request
End of enumeration elements list.
CONVDEL : Conversion Delay
bits : 12 - 11 (0 bit)
access : read-write
INTERVCNT : Sub-second Interval Counter
bits : 16 - 26 (11 bit)
access : read-write
SETTLECNT : LPAC Settle Time Counter
bits : 28 - 30 (3 bit)
access : read-write
LPAC Threshold Register 0
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATLO : VBAT Lower Threshold Value
bits : 0 - 4 (5 bit)
access : read-write
VBATHI : VBAT Upper Threshold Value
bits : 8 - 12 (5 bit)
access : read-write
LPAC Threshold Register 1
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHIBIO0LO : Analog HIB_IO_0 Lower Threshold Value
bits : 0 - 4 (5 bit)
access : read-write
AHIBIO0HI : Analog HIB_IO_0 Upper Threshold Value
bits : 8 - 12 (5 bit)
access : read-write
Hibernate Analog Control State Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATSCMP : Trigger VBAT Single Compare Operation Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready to start new compare operation
#1 : value2
Compare operation completed
End of enumeration elements list.
AHIBIO0SCMP : Trigger HIB_IO_0 Input Single Compare Operation Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
Ready to start new compare operation
#1 : value2
Compare operation completed
End of enumeration elements list.
VBATVAL : VBAT Compare Operation Result
bits : 16 - 15 (0 bit)
access : read-only
Enumeration:
#0 : value1
Below programmed threshold
#1 : value2
Above programmed threshold
End of enumeration elements list.
AHIBIO0VAL : HIB_IO_0 Input Compare Operation Result
bits : 17 - 16 (0 bit)
access : read-only
Enumeration:
#0 : value1
Below programmed threshold
#1 : value2
Above programmed threshold
End of enumeration elements list.
LPAC Control Clear Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATSCMP : Trigger VBAT Single Compare Operation Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the sticky bit
End of enumeration elements list.
AHIBIO0SCMP : Trigger HIB_IO_0 Input Single Compare Operation Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear the sticky bit
End of enumeration elements list.
VBATVAL : VBAT Compare Operation Initial Value Clear
bits : 16 - 15 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Below programmed threshold
End of enumeration elements list.
AHIBIO0VAL : HIB_IO_0 Input Compare Initial Value Clear
bits : 17 - 16 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Below programmed threshold
End of enumeration elements list.
LPAC Control Set Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VBATSCMP : Trigger VBAT Single Compare Operation Set
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Start compare operation
End of enumeration elements list.
AHIBIO0SCMP : Trigger HIB_IO_0 Input Single Compare Operation Set
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Start compare operation
End of enumeration elements list.
VBATVAL : VBAT Compare Operation Initial Value Set
bits : 16 - 15 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Above programmed threshold
End of enumeration elements list.
AHIBIO0VAL : HIB_IO_0 Input Compare Initial Value Set
bits : 17 - 16 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Above programmed threshold
End of enumeration elements list.
Hibernate Internal Control State Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIBNINT : Internally Controlled Hibernate Sequence Request State
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Hibernate not entered
#1 : value2
Hibernate entered
End of enumeration elements list.
FLASHOFF : VDDP Supply Switch of Flash State
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
VDDP supply of Flash switched on
#1 : value2
VDDP supply of Flash switched off
End of enumeration elements list.
FLASHPD : Flash Power Down State
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
Normal mode
#1 : value2
Power down mode effectively entered
End of enumeration elements list.
POFFD : PORST Pull-up OFF Direct Control State
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
Pull-up on
#1 : value2
Pull-up off
End of enumeration elements list.
PPODEL : Delay on PORTS Pull-up Switching OFF on Hibernate Request
bits : 16 - 16 (1 bit)
access : read-only
POFFH : PORST Pull-up OFF in Hibernate Mode State
bits : 20 - 19 (0 bit)
access : read-only
Enumeration:
#0 : value1
Pull-up on
#1 : value2
Pull-up off
End of enumeration elements list.
Hibernate Internal Control Clear Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIBNINT : Internally Controlled Hibernate Sequence Request Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Hibernate bit clear
End of enumeration elements list.
FLASHOFF : VDDP Supply Switch of Flash Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Switch on VDDP supply of Flash
End of enumeration elements list.
FLASHPD : Flash Power Down Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Flash power down mode leave request
End of enumeration elements list.
POFFD : PORST Pull-up OFF Direct Control Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Pull-up on
End of enumeration elements list.
PPODEL : Delay on PORTS Pull-up Switching OFF on Hibernate Request Clear
bits : 16 - 16 (1 bit)
access : write-only
POFFH : PORST Pull-up OFF in Hibernate Mode Clear
bits : 20 - 19 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Pull-up on
End of enumeration elements list.
Hibernate Domain Status Clear Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPEV : Wake-up Pin Event Positive Edge Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear wake-up event
End of enumeration elements list.
ENEV : Wake-up Pin Event Negative Edge Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear wake-up event
End of enumeration elements list.
RTCEV : RTC Event Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear wake-up event
End of enumeration elements list.
ULPWDG : ULP WDG Alarm Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear watchdog alarm
End of enumeration elements list.
VBATPEV : Wake-Up on LPAC Positive Edge of VBAT Threshold Crossing Clear
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear wake-up event
End of enumeration elements list.
VBATNEV : Wake-Up on LPAC Negative Edge of VBAT Threshold Crossing Clear
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear wake-up event
End of enumeration elements list.
AHIBIO0PEV : Wake-Up on LPAC Positive Edge of HIB_IO_0 Threshold Crossing Clear
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear wake-up event
End of enumeration elements list.
AHIBIO0NEV : Wake-Up on LPAC Negative Edge of HIB_IO_0 Threshold Crossing Clear
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Clear wake-up event
End of enumeration elements list.
Hibernate Internal Control Set Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HIBNINT : Internally Controlled Hibernate Sequence Request Set
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Hardware controlled hibernate sequence request active
End of enumeration elements list.
VCOREOFF : VDDC Generation off on EVR Set
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
VDDC off to EVR set
End of enumeration elements list.
FLASHOFF : VDDP Supply Switch of Flash Set
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Switch off VDDP supply of Flash
End of enumeration elements list.
FLASHPD : Flash Power Down Set
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Flash power down mode request set
End of enumeration elements list.
POFFD : PORST Pull-up OFF Direct Control Set
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Pull-up off
End of enumeration elements list.
PPODEL : Delay on PORTS Pull-up Switching OFF on Hibernate Request Set
bits : 16 - 16 (1 bit)
access : write-only
POFFH : PORST Pull-up OFF in Hibernate Mode Set
bits : 20 - 19 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Pull-up off
End of enumeration elements list.
Hibernate Domain Status Set Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPEV : Wake-up Pin Event Positive Edge Set
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Set wake-up event
End of enumeration elements list.
ENEV : Wake-up Pin Event Negative Edge Set
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Set wake-up event
End of enumeration elements list.
RTCEV : RTC Event Set
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Set wake-up event
End of enumeration elements list.
ULPWDG : ULP WDG Alarm Set
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Set watchdog alarm
End of enumeration elements list.
VBATPEV : Wake-Up on LPAC Positive Edge of VBAT Threshold Crossing Set
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Set wake-up event
End of enumeration elements list.
VBATNEV : Wake-Up on LPAC Negative Edge of VBAT Threshold Crossing Set
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Set wake-up event
End of enumeration elements list.
AHIBIO0PEV : Wake-Up on LPAC Positive Edge of HIB_IO_0 Threshold Crossing Set
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Set wake-up event
End of enumeration elements list.
AHIBIO0NEV : Wake-Up on LPAC Negative Edge of HIB_IO_0 Threshold Crossing Set
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Set wake-up event
End of enumeration elements list.
Hibernate Domain Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKPEP : Wake-Up on Pin Event Positive Edge Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Wake-up event disabled
#1 : value2
Wake-up event enabled
End of enumeration elements list.
WKPEN : Wake-up on Pin Event Negative Edge Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Wake-up event disabled
#1 : value2
Wake-up event enabled
End of enumeration elements list.
RTCE : Wake-up on RTC Event Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Wake-up event disabled
#1 : value2
Wake-up event enabled
End of enumeration elements list.
ULPWDGEN : ULP WDG Alarm Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Wake-up event disabled
#1 : value2
Wake-up event enabled
End of enumeration elements list.
HIB : Hibernate Request Value Set
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
External hibernate request inactive
#1 : value2
External hibernate request active
End of enumeration elements list.
XTALGPI1SEL : Multiplex Control for RTC_XTAL_1 Select as GPI Input
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
RTC_XTAL_1 input selected
#1 : value2
Analog comparator output for HIB_IO_1 or pre-selected digital IO input
End of enumeration elements list.
RCS : fRTC Clock Selection
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
fOSI selected
#1 : value2
fULP selected
End of enumeration elements list.
STDBYSEL : fSTDBY Clock Selection
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
fOSI selected
#1 : value2
fULP selected
End of enumeration elements list.
WKUPSEL : Wake-Up from Hibernate Trigger Input Selection
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
HIB_IO_1 pin selected
#1 : value2
HIB_IO_0 pin selected
End of enumeration elements list.
GPI0SEL : General Purpose Input 0 Selection
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#1 : value2
HIB_IO_0 pin selected
End of enumeration elements list.
HIBIO0POL : HIBIO0 Polarity Set
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
Direct value
#1 : value2
Inverted value
End of enumeration elements list.
ADIG0SEL : Select Analog Channel 0 or Digital Output Path
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
Digital input
#1 : value2
Analog comparator result for HIB_IO_0
End of enumeration elements list.
HIBIO0SEL : HIB_IO_0 Pin I/O Control (default HIBOUT)
bits : 16 - 18 (3 bit)
access : read-write
Enumeration:
#0000 : value1
Direct input, No input pull device connected
#0001 : value2
Direct input, Input pull-down device connected
#0010 : value3
Direct input, Input pull-up device connected
#1000 : value4
Push-pull HIB Control output
#1001 : value5
Push-pull WDT service output
#1010 : value6
Push-pull GPIO output
#1100 : value7
Open-drain HIB Control output
#1101 : value8
Open-drain WDT service output
#1110 : value9
Open-drain GPIO output
#1111 : value10
Analog input
End of enumeration elements list.
VBATLO : Wake-Up on VBAT Falling Below Threshold Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : value1
Wake-up event disabled
#1 : value2
Wake-up event enabled
End of enumeration elements list.
VBATHI : Wake-Up on VBAT Rising Above Threshold Enable
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : value1
Wake-up event disabled
#1 : value2
Wake-up event enabled
End of enumeration elements list.
AHIBIO0LO : Wake-Up on Analog HIB_IO_0 Falling Below Threshold Enable
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : value1
Wake-up event disabled
#1 : value2
Wake-up event enabled
End of enumeration elements list.
AHIBIO0HI : Wake-Up on Analog HIB_IO_0 Rising Above Threshold Enable
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : value1
Wake-up event disabled
#1 : value2
Wake-up event enabled
End of enumeration elements list.
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