\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
Module Identification Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODR : Module Revision
bits : 0 - 6 (7 bit)
access : read-only
MODT : Module Type
bits : 8 - 14 (7 bit)
access : read-only
MODN : Module Number
bits : 16 - 30 (15 bit)
access : read-only
DAC1 Configuration Register 1
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCALE : Scale value for up- or downscale of the DAC1 input data in steps by the power of 2 (=shift operation)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
no shift = multiplication/division by 1
#001 : value2
shift by 1 = multiplication/division by 2
#010 : value3
shift by 2 = multiplication/division by 4
#011 : value4
shift left by 3 = multiplication/division by 8
#100 : value5
shift left by 4 = multiplication/division by 16
#101 : value6
shift left by 5 = multiplication/division by 32
#110 : value7
shift left by 6 = multiplication/division by 64
#111 : value8
shift left by 7 = multiplication/division by 128
End of enumeration elements list.
MULDIV : Switch between up- and downscale of the DAC1 input data values
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
downscale = division (shift SCALE positions to the right)
#1 : value2
upscale = multiplication (shift SCALE positions to the left)
End of enumeration elements list.
OFFS : 8-bit offset value addition
bits : 4 - 10 (7 bit)
access : read-write
TRIGSEL : Selects one of the eight external trigger sources for DAC1
bits : 12 - 13 (2 bit)
access : read-write
SWTRIG : Software Trigger
bits : 16 - 15 (0 bit)
access : read-write
TRIGMOD : Select the trigger source for channel 1
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#00 : value1
internal Trigger (integer divided clock - see FREQ parameter)
#01 : value2
external Trigger (preselected trigger by TRIGSEL parameter)
#10 : value3
software Trigger (see SWTRIG parameter)
End of enumeration elements list.
ANACFG : DAC1 analog configuration/calibration parameters
bits : 19 - 22 (4 bit)
access : read-write
ANAEN : Enable analog DAC for channel 1
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : value1
DAC1 is set to standby (analog output only)
#1 : value2
enable DAC1 (analog output only)
End of enumeration elements list.
REFCFGH : Higher 4 band-gap configuration/calibration parameters
bits : 28 - 30 (3 bit)
access : read-write
DAC0 Data Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : DAC0 Data Bits
bits : 0 - 10 (11 bit)
access : read-write
DAC1 Data Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA1 : DAC1 Data Bits
bits : 0 - 10 (11 bit)
access : read-write
DAC01 Data Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA0 : DAC0 Data Bits
bits : 0 - 10 (11 bit)
access : read-write
DATA1 : DAC1 Data Bits
bits : 16 - 26 (11 bit)
access : read-write
DAC0 Lower Pattern Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAT0 : Pattern Number 0 for PATGEN of DAC0
bits : 0 - 3 (4 bit)
access : read-write
PAT1 : Pattern Number 1 for PATGEN of DAC0
bits : 5 - 8 (4 bit)
access : read-write
PAT2 : Pattern Number 2 for PATGEN of DAC0
bits : 10 - 13 (4 bit)
access : read-write
PAT3 : Pattern Number 3 for PATGEN of DAC0
bits : 15 - 18 (4 bit)
access : read-write
PAT4 : Pattern Number 4 for PATGEN of DAC0
bits : 20 - 23 (4 bit)
access : read-write
PAT5 : Pattern Number 5 for PATGEN of DAC0
bits : 25 - 28 (4 bit)
access : read-write
DAC0 Higher Pattern Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAT6 : Pattern Number 6 for PATGEN of DAC0
bits : 0 - 3 (4 bit)
access : read-write
PAT7 : Pattern Number 7 for PATGEN of DAC0
bits : 5 - 8 (4 bit)
access : read-write
PAT8 : Pattern Number 8 for PATGEN of DAC0
bits : 10 - 13 (4 bit)
access : read-write
DAC1 Lower Pattern Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAT0 : Pattern Number 0 for PATGEN of DAC1
bits : 0 - 3 (4 bit)
access : read-write
PAT1 : Pattern Number 1 for PATGEN of DAC1
bits : 5 - 8 (4 bit)
access : read-write
PAT2 : Pattern Number 2 for PATGEN of DAC1
bits : 10 - 13 (4 bit)
access : read-write
PAT3 : Pattern Number 3 for PATGEN of DAC1
bits : 15 - 18 (4 bit)
access : read-write
PAT4 : Pattern Number 4 for PATGEN of DAC1
bits : 20 - 23 (4 bit)
access : read-write
PAT5 : Pattern Number 5 for PATGEN of DAC1
bits : 25 - 28 (4 bit)
access : read-write
DAC1 Higher Pattern Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PAT6 : Pattern Number 6 for PATGEN of DAC1
bits : 0 - 3 (4 bit)
access : read-write
PAT7 : Pattern Number 7 for PATGEN of DAC1
bits : 5 - 8 (4 bit)
access : read-write
PAT8 : Pattern Number 8 for PATGEN of DAC1
bits : 10 - 13 (4 bit)
access : read-write
DAC0 Configuration Register 0
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQ : Integer Frequency Divider Value
bits : 0 - 18 (19 bit)
access : read-write
MODE : Enables and Sets the Mode for DAC0
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#000 : value1
disable/switch-off DAC
#001 : value2
Single Value Mode
#010 : value3
Data Mode
#011 : value4
Patgen Mode
#100 : value5
Noise Mode
#101 : value6
Ramp Mode
#110 : value7
na
#111 : value8
na
End of enumeration elements list.
SIGN : Selects Between Signed and Unsigned DAC0 Mode
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : value1
DAC expects unsigned input data
#1 : value2
DAC expects signed input data
End of enumeration elements list.
FIFOIND : Current write position inside the data FIFO
bits : 24 - 24 (1 bit)
access : read-only
FIFOEMP : Indicate if the FIFO is empty
bits : 26 - 25 (0 bit)
access : read-only
Enumeration:
#0 : value1
FIFO not empty
#1 : value2
FIFO empty
End of enumeration elements list.
FIFOFUL : Indicate if the FIFO is full
bits : 27 - 26 (0 bit)
access : read-only
Enumeration:
#0 : value1
FIFO not full
#1 : value2
FIFO full
End of enumeration elements list.
NEGATE : Negates the DAC0 output
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : value1
DAC output not negated
#1 : value2
DAC output negated
End of enumeration elements list.
SIGNEN : Enable Sign Output of DAC0 Pattern Generator
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
SREN : Enable DAC0 service request interrupt generation
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : value1
disable
#1 : value2
enable
End of enumeration elements list.
RUN : RUN indicates the current DAC0 operation status
bits : 31 - 30 (0 bit)
access : read-only
Enumeration:
#0 : value1
DAC0 channel disabled
#1 : value2
DAC0 channel in operation
End of enumeration elements list.
DAC0 Configuration Register 1
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCALE : Scale value for up- or downscale of the DAC0 input data in steps by the power of 2 (=shift operation)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
no shift = multiplication/division by 1
#001 : value2
shift by 1 = multiplication/division by 2
#010 : value3
shift by 2 = multiplication/division by 4
#011 : value4
shift left by 3 = multiplication/division by 8
#100 : value5
shift left by 4 = multiplication/division by 16
#101 : value6
shift left by 5 = multiplication/division by 32
#110 : value7
shift left by 6 = multiplication/division by 64
#111 : value8
shift left by 7 = multiplication/division by 128
End of enumeration elements list.
MULDIV : Switch between up- and downscale of the DAC0 input data values
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
downscale = division (shift SCALE positions to the right)
#1 : value2
upscale = multiplication (shift SCALE positions to the left)
End of enumeration elements list.
OFFS : 8-bit offset value addition
bits : 4 - 10 (7 bit)
access : read-write
TRIGSEL : Selects one of the eight external trigger sources for DAC0
bits : 12 - 13 (2 bit)
access : read-write
DATMOD : Switch between independent or simultaneous DAC mode and select the input data register for DAC0 and DAC1
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
independent data handling - process data from DATA0 register (bits 11:0) to DAC0 and data from DATA1 register (bits 11:0) to DAC1
#1 : value2
simultaneous data handling - process data from DAC01 register to both DACs (bits 11:0 to DAC0 and bits 23:12 to DAC1).
End of enumeration elements list.
SWTRIG : Software Trigger
bits : 16 - 15 (0 bit)
access : read-write
TRIGMOD : Select the trigger source for channel 0
bits : 17 - 17 (1 bit)
access : read-write
Enumeration:
#00 : value1
internal Trigger (integer divided clock - see FREQ parameter)
#01 : value2
external Trigger (preselected trigger by TRIGSEL parameter)
#10 : value3
software Trigger (see SWTRIG parameter)
End of enumeration elements list.
ANACFG : DAC0 analog configuration/calibration parameters
bits : 19 - 22 (4 bit)
access : read-write
ANAEN : Enable analog DAC for channel 0
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : value1
DAC0 is set to standby (analog output only)
#1 : value2
enable DAC0 (analog output only)
End of enumeration elements list.
REFCFGL : Lower 4 band-gap configuration/calibration parameters
bits : 28 - 30 (3 bit)
access : read-write
DAC1 Configuration Register 0
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FREQ : Integer Frequency Divider Value
bits : 0 - 18 (19 bit)
access : read-write
MODE : Enables and sets the Mode for DAC1
bits : 20 - 21 (2 bit)
access : read-write
Enumeration:
#000 : value1
disable/switch-off DAC
#001 : value2
Single Value Mode
#010 : value3
Data Mode
#011 : value4
Patgen Mode
#100 : value5
Noise Mode
#101 : value6
Ramp Mode
#110 : value7
na
#111 : value8
na
End of enumeration elements list.
SIGN : Selects between signed and unsigned DAC1 mode
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : value1
DAC expects unsigned input data
#1 : value2
DAC expects signed input data
End of enumeration elements list.
FIFOIND : Current write position inside the data FIFO
bits : 24 - 24 (1 bit)
access : read-only
FIFOEMP : Indicate if the FIFO is empty
bits : 26 - 25 (0 bit)
access : read-only
Enumeration:
#0 : value1
FIFO not empty
#1 : value2
FIFO empty
End of enumeration elements list.
FIFOFUL : Indicate if the FIFO is full
bits : 27 - 26 (0 bit)
access : read-only
Enumeration:
#0 : value1
FIFO not full
#1 : value2
FIFO full
End of enumeration elements list.
NEGATE : Negates the DAC1 output
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : value1
DAC output not negated
#1 : value2
DAC output negated
End of enumeration elements list.
SIGNEN : Enable sign output of DAC1 pattern generator
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : value1
disable
#1 : value2
enable
End of enumeration elements list.
SREN : Enable DAC1 service request interrupt generation
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : value1
disable
#1 : value2
enable
End of enumeration elements list.
RUN : RUN indicates the current DAC1 operation status
bits : 31 - 30 (0 bit)
access : read-only
Enumeration:
#0 : value1
DAC1 channel disabled
#1 : value2
DAC1 channel in operation
End of enumeration elements list.
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