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CCU4

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

GCTRL

GCSS

GCSC

GCST

GSTAT

ECRD

GIDLS

MIDR

GIDLC


GCTRL

Global Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCTRL GCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRBC PCIS SUSCFG MSE0 MSE1 MSE2 MSE3 MSDE

PRBC : Prescaler Clear Configuration
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

#000 : value1

SW only

#001 : value2

GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC40 is cleared.

#010 : value3

GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC41 is cleared.

#011 : value4

GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC42 is cleared.

#100 : value5

GSTATThe register contains the status of the prescaler and each timer slice (idle mode or running)..PRB and prescaler registers are cleared when the Run Bit of CC43 is cleared.

End of enumeration elements list.

PCIS : Prescaler Input Clock Selection
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Module clock

#01 : value2

CCU4x.ECLKA

#10 : value3

CCU4x.ECLKB

#11 : value4

CCU4x.ECLKC

End of enumeration elements list.

SUSCFG : Suspend Mode Configuration
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Suspend request ignored. The module never enters in suspend

#01 : value2

Stops all the running slices immediately. Safe stop is not applied.

#10 : value3

Stops the block immediately and clamps all the outputs to PASSIVE state. Safe stop is applied.

#11 : value4

Waits for the roll over of each slice to stop and clamp the slices outputs. Safe stop is applied.

End of enumeration elements list.

MSE0 : Slice 0 Multi Channel shadow transfer enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

Shadow transfer can only be requested by SW

#1 : value2

Shadow transfer can be requested via SW and via the CCU4x.MCSS input.

End of enumeration elements list.

MSE1 : Slice 1 Multi Channel shadow transfer enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Shadow transfer can only be requested by SW

#1 : value2

Shadow transfer can be requested via SW and via the CCU4x.MCSS input.

End of enumeration elements list.

MSE2 : Slice 2 Multi Channel shadow transfer enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : value1

Shadow transfer can only be requested by SW

#1 : value2

Shadow transfer can be requested via SW and via the CCU4x.MCSS input.

End of enumeration elements list.

MSE3 : Slice 3 Multi Channel shadow transfer enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : value1

Shadow transfer can only be requested by SW

#1 : value2

Shadow transfer can be requested via SW and via the CCU4x.MCSS input.

End of enumeration elements list.

MSDE : Multi Channel shadow transfer request configuration
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#00 : value1

Only the shadow transfer for period and compare values is requested

#01 : value2

Shadow transfer for the compare, period and prescaler compare values is requested

#11 : value4

Shadow transfer for the compare, period, prescaler and dither compare values is requested

End of enumeration elements list.


GCSS

Global Channel Set
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCSS GCSS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S0SE S0DSE S0PSE S1SE S1DSE S1PSE S2SE S2DSE S2PSE S3SE S3DSE S3PSE S0STS S1STS S2STS S3STS

S0SE : Slice 0 shadow transfer set enable
bits : 0 - -1 (0 bit)
access : write-only

S0DSE : Slice 0 Dither shadow transfer set enable
bits : 1 - 0 (0 bit)
access : write-only

S0PSE : Slice 0 Prescaler shadow transfer set enable
bits : 2 - 1 (0 bit)
access : write-only

S1SE : Slice 1 shadow transfer set enable
bits : 4 - 3 (0 bit)
access : write-only

S1DSE : Slice 1 Dither shadow transfer set enable
bits : 5 - 4 (0 bit)
access : write-only

S1PSE : Slice 1 Prescaler shadow transfer set enable
bits : 6 - 5 (0 bit)
access : write-only

S2SE : Slice 2 shadow transfer set enable
bits : 8 - 7 (0 bit)
access : write-only

S2DSE : Slice 2 Dither shadow transfer set enable
bits : 9 - 8 (0 bit)
access : write-only

S2PSE : Slice 2 Prescaler shadow transfer set enable
bits : 10 - 9 (0 bit)
access : write-only

S3SE : Slice 3 shadow transfer set enable
bits : 12 - 11 (0 bit)
access : write-only

S3DSE : Slice 3 Dither shadow transfer set enable
bits : 13 - 12 (0 bit)
access : write-only

S3PSE : Slice 3 Prescaler shadow transfer set enable
bits : 14 - 13 (0 bit)
access : write-only

S0STS : Slice 0 status bit set
bits : 16 - 15 (0 bit)
access : write-only

S1STS : Slice 1 status bit set
bits : 17 - 16 (0 bit)
access : write-only

S2STS : Slice 2 status bit set
bits : 18 - 17 (0 bit)
access : write-only

S3STS : Slice 3 status bit set
bits : 19 - 18 (0 bit)
access : write-only


GCSC

Global Channel Clear
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCSC GCSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S0SC S0DSC S0PSC S1SC S1DSC S1PSC S2SC S2DSC S2PSC S3SC S3DSC S3PSC S0STC S1STC S2STC S3STC

S0SC : Slice 0 shadow transfer clear
bits : 0 - -1 (0 bit)
access : write-only

S0DSC : Slice 0 Dither shadow transfer clear
bits : 1 - 0 (0 bit)
access : write-only

S0PSC : Slice 0 Prescaler shadow transfer clear
bits : 2 - 1 (0 bit)
access : write-only

S1SC : Slice 1 shadow transfer clear
bits : 4 - 3 (0 bit)
access : write-only

S1DSC : Slice 1 Dither shadow transfer clear
bits : 5 - 4 (0 bit)
access : write-only

S1PSC : Slice 1 Prescaler shadow transfer clear
bits : 6 - 5 (0 bit)
access : write-only

S2SC : Slice 2 shadow transfer clear
bits : 8 - 7 (0 bit)
access : write-only

S2DSC : Slice 2 Dither shadow transfer clear
bits : 9 - 8 (0 bit)
access : write-only

S2PSC : Slice 2 Prescaler shadow transfer clear
bits : 10 - 9 (0 bit)
access : write-only

S3SC : Slice 3 shadow transfer clear
bits : 12 - 11 (0 bit)
access : write-only

S3DSC : Slice 3 Dither shadow transfer clear
bits : 13 - 12 (0 bit)
access : write-only

S3PSC : Slice 3 Prescaler shadow transfer clear
bits : 14 - 13 (0 bit)
access : write-only

S0STC : Slice 0 status bit clear
bits : 16 - 15 (0 bit)
access : write-only

S1STC : Slice 1 status bit clear
bits : 17 - 16 (0 bit)
access : write-only

S2STC : Slice 2 status bit clear
bits : 18 - 17 (0 bit)
access : write-only

S3STC : Slice 3 status bit clear
bits : 19 - 18 (0 bit)
access : write-only


GCST

Global Channel Status
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GCST GCST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S0SS S0DSS S0PSS S1SS S1DSS S1PSS S2SS S2DSS S2PSS S3SS S3DSS S3PSS CC40ST CC41ST CC42ST CC43ST

S0SS : Slice 0 shadow transfer status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Shadow transfer has not been requested

#1 : value2

Shadow transfer has been requested

End of enumeration elements list.

S0DSS : Slice 0 Dither shadow transfer status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : value1

Dither shadow transfer has not been requested

#1 : value2

Dither shadow transfer has been requested

End of enumeration elements list.

S0PSS : Slice 0 Prescaler shadow transfer status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Prescaler shadow transfer has not been requested

#1 : value2

Prescaler shadow transfer has been requested

End of enumeration elements list.

S1SS : Slice 1 shadow transfer status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : value1

Shadow transfer has not been requested

#1 : value2

Shadow transfer has been requested

End of enumeration elements list.

S1DSS : Slice 1 Dither shadow transfer status
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : value1

Dither shadow transfer has not been requested

#1 : value2

Dither shadow transfer has been requested

End of enumeration elements list.

S1PSS : Slice 1 Prescaler shadow transfer status
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : value1

Prescaler shadow transfer has not been requested

#1 : value2

Prescaler shadow transfer has been requested

End of enumeration elements list.

S2SS : Slice 2 shadow transfer status
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

Shadow transfer has not been requested

#1 : value2

Shadow transfer has been requested

End of enumeration elements list.

S2DSS : Slice 2 Dither shadow transfer status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : value1

Dither shadow transfer has not been requested

#1 : value2

Dither shadow transfer has been requested

End of enumeration elements list.

S2PSS : Slice 2 Prescaler shadow transfer status
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

#0 : value1

Prescaler shadow transfer has not been requested

#1 : value2

Prescaler shadow transfer has been requested

End of enumeration elements list.

S3SS : Slice 3 shadow transfer status
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : value1

Shadow transfer has not been requested

#1 : value2

Shadow transfer has been requested

End of enumeration elements list.

S3DSS : Slice 3 Dither shadow transfer status
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

#0 : value1

Dither shadow transfer has not been requested

#1 : value2

Dither shadow transfer has been requested

End of enumeration elements list.

S3PSS : Slice 3 Prescaler shadow transfer status
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : value1

Prescaler shadow transfer has not been requested

#1 : value2

Prescaler shadow transfer has been requested

End of enumeration elements list.

CC40ST : Slice 0 status bit
bits : 16 - 15 (0 bit)
access : read-only

CC41ST : Slice 1 status bit
bits : 17 - 16 (0 bit)
access : read-only

CC42ST : Slice 2 status bit
bits : 18 - 17 (0 bit)
access : read-only

CC43ST : Slice 3 status bit
bits : 19 - 18 (0 bit)
access : read-only


GSTAT

Global Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GSTAT GSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 S0I S1I S2I S3I PRB

S0I : CC40 IDLE status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Running

#1 : value2

Idle

End of enumeration elements list.

S1I : CC41 IDLE status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : value1

Running

#1 : value2

Idle

End of enumeration elements list.

S2I : CC42 IDLE status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Running

#1 : value2

Idle

End of enumeration elements list.

S3I : CC43 IDLE status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : value1

Running

#1 : value2

Idle

End of enumeration elements list.

PRB : Prescaler Run Bit
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

Prescaler is stopped

#1 : value2

Prescaler is running

End of enumeration elements list.


ECRD

Extended Capture Mode Read
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ECRD ECRD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPV FPCV SPTR VPTR FFL

CAPV : Timer Capture Value
bits : 0 - 14 (15 bit)
access : read-only

FPCV : Prescaler Capture value
bits : 16 - 18 (3 bit)
access : read-only

SPTR : Slice pointer
bits : 20 - 20 (1 bit)
access : read-only

Enumeration:

#00 : value1

CC40

#01 : value2

CC41

#10 : value3

CC42

#11 : value4

CC43

End of enumeration elements list.

VPTR : Capture register pointer
bits : 22 - 22 (1 bit)
access : read-only

Enumeration:

#00 : value1

Capture register 0

#01 : value2

Capture register 1

#10 : value3

Capture register 2

#11 : value4

Capture register 3

End of enumeration elements list.

FFL : Full Flag
bits : 24 - 23 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new value was captured into this register

#1 : value2

A new value has been captured into this register

End of enumeration elements list.


GIDLS

Global Idle Set
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GIDLS GIDLS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS0I SS1I SS2I SS3I CPRB PSIC

SS0I : CC40 IDLE mode set
bits : 0 - -1 (0 bit)
access : write-only

SS1I : CC41 IDLE mode set
bits : 1 - 0 (0 bit)
access : write-only

SS2I : CC42 IDLE mode set
bits : 2 - 1 (0 bit)
access : write-only

SS3I : CC43 IDLE mode set
bits : 3 - 2 (0 bit)
access : write-only

CPRB : Prescaler Run Bit Clear
bits : 8 - 7 (0 bit)
access : write-only

PSIC : Prescaler clear
bits : 9 - 8 (0 bit)
access : write-only


MIDR

Module Identification
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIDR MIDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MODR MODT MODN

MODR : Module Revision
bits : 0 - 6 (7 bit)
access : read-only

MODT : Module Type
bits : 8 - 14 (7 bit)
access : read-only

MODN : Module Number
bits : 16 - 30 (15 bit)
access : read-only


GIDLC

Global Idle Clear
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GIDLC GIDLC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CS0I CS1I CS2I CS3I SPRB

CS0I : CC40 IDLE mode clear
bits : 0 - -1 (0 bit)
access : write-only

CS1I : CC41 IDLE mode clear
bits : 1 - 0 (0 bit)
access : write-only

CS2I : CC42 IDLE mode clear
bits : 2 - 1 (0 bit)
access : write-only

CS3I : CC43 IDLE mode clear
bits : 3 - 2 (0 bit)
access : write-only

SPRB : Prescaler Run Bit Set
bits : 8 - 7 (0 bit)
access : write-only



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