\n
address_offset : 0x0 Bytes (0x0)
size : 0x40000 byte (0x0)
mem_usage : registers
protection : not protected
Reset Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSftRst : Core Soft Reset
bits : 0 - -1 (0 bit)
access : read-write
RxFFlsh : RxFIFO Flush
bits : 4 - 3 (0 bit)
access : read-write
TxFFlsh : TxFIFO Flush
bits : 5 - 4 (0 bit)
access : read-write
TxFNum : TxFIFO Number
bits : 6 - 9 (4 bit)
access : read-write
Enumeration:
0x00 : value1
Tx FIFO 0 flush in device mode
0x01 : value2
Tx FIFO 1 flush in device mode
0x02 : value3
Tx FIFO 2 flush in device mode
0x0F : value4
Tx FIFO 15 flush in device mode
0x10 : value5
Flush all the transmit FIFOs in device or host mode.
End of enumeration elements list.
DMAReq : DMA Request Signal
bits : 30 - 29 (0 bit)
access : read-only
AHBIdle : AHB Master Idle
bits : 31 - 30 (0 bit)
access : read-only
Device IN Endpoint 1 Transmit FIFO Size Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPnTxFStAddr : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write
INEPnTxFDep : IN Endpoint TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write
Device IN Endpoint 2 Transmit FIFO Size Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPnTxFStAddr : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write
INEPnTxFDep : IN Endpoint TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write
Device IN Endpoint 3 Transmit FIFO Size Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPnTxFStAddr : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write
INEPnTxFDep : IN Endpoint TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write
Device IN Endpoint 4 Transmit FIFO Size Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPnTxFStAddr : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write
INEPnTxFDep : IN Endpoint TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write
Device IN Endpoint 5 Transmit FIFO Size Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPnTxFStAddr : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write
INEPnTxFDep : IN Endpoint TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write
Device IN Endpoint 6 Transmit FIFO Size Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPnTxFStAddr : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write
INEPnTxFDep : IN Endpoint TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write
Interrupt Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CurMod : Current Mode of Operation
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Device mode
End of enumeration elements list.
Sof : Start of Frame
bits : 3 - 2 (0 bit)
access : read-write
RxFLvl : RxFIFO Non-Empty
bits : 4 - 3 (0 bit)
access : read-only
GINNakEff : Global IN Non-Periodic NAK Effective
bits : 6 - 5 (0 bit)
access : read-only
GOUTNakEff : Global OUT NAK Effective
bits : 7 - 6 (0 bit)
access : read-only
ErlySusp : Early Suspend
bits : 10 - 9 (0 bit)
access : read-write
USBSusp : USB Suspend
bits : 11 - 10 (0 bit)
access : read-write
USBRst : USB Reset
bits : 12 - 11 (0 bit)
access : read-write
EnumDone : Enumeration Done
bits : 13 - 12 (0 bit)
access : read-write
ISOOutDrop : Isochronous OUT Packet Dropped Interrupt
bits : 14 - 13 (0 bit)
access : read-write
EOPF : End of Periodic Frame Interrupt
bits : 15 - 14 (0 bit)
access : read-write
IEPInt : IN Endpoints Interrupt
bits : 18 - 17 (0 bit)
access : read-only
OEPInt : OUT Endpoints Interrupt
bits : 19 - 18 (0 bit)
access : read-only
incompISOIN : Incomplete Isochronous IN Transfer
bits : 20 - 19 (0 bit)
access : read-write
incomplSOOUT : Incomplete Isochronous OUT Transfer
bits : 21 - 20 (0 bit)
access : read-write
WkUpInt : Resume/Remote Wakeup Detected Interrupt
bits : 31 - 30 (0 bit)
access : read-write
Interrupt Mask Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SofMsk : Start of Frame Mask
bits : 3 - 2 (0 bit)
access : read-write
RxFLvlMsk : Receive FIFO Non-Empty Mask
bits : 4 - 3 (0 bit)
access : read-write
GINNakEffMsk : Global Non-periodic IN NAK Effective Mask
bits : 6 - 5 (0 bit)
access : read-write
GOUTNakEffMsk : Global OUT NAK Effective Mask
bits : 7 - 6 (0 bit)
access : read-write
ErlySuspMsk : Early Suspend Mask
bits : 10 - 9 (0 bit)
access : read-write
USBSuspMsk : USB Suspend Mask
bits : 11 - 10 (0 bit)
access : read-write
USBRstMsk : USB Reset Mask
bits : 12 - 11 (0 bit)
access : read-write
EnumDoneMsk : Enumeration Done Mask
bits : 13 - 12 (0 bit)
access : read-write
ISOOutDropMsk : Isochronous OUT Packet Dropped Interrupt Mask
bits : 14 - 13 (0 bit)
access : read-write
EOPFMsk : End of Periodic Frame Interrupt Mask
bits : 15 - 14 (0 bit)
access : read-write
IEPIntMsk : IN Endpoints Interrupt Mask
bits : 18 - 17 (0 bit)
access : read-write
OEPIntMsk : OUT Endpoints Interrupt Mask
bits : 19 - 18 (0 bit)
access : read-write
incompISOINMsk : Incomplete Isochronous IN Transfer Mask
bits : 20 - 19 (0 bit)
access : read-write
incomplSOOUTMsk : Incomplete Isochronous OUT Transfer Mask
bits : 21 - 20 (0 bit)
access : read-write
WkUpIntMsk : Resume/Remote Wakeup Detected Interrupt Mask
bits : 31 - 30 (0 bit)
access : read-write
Receive Status Debug Read Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPNum : Endpoint Number
bits : 0 - 2 (3 bit)
access : read-only
BCnt : Byte Count
bits : 4 - 13 (10 bit)
access : read-only
DPID : Data PID
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#00 : value1
DATA0
#10 : value2
DATA1
#01 : value3
DATA2
#11 : value4
MDATA
End of enumeration elements list.
PktSts : Packet Status
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
#0001 : value1
Global OUT NAK (triggers an interrupt)
#0010 : value2
OUT data packet received
#0011 : value3
OUT transfer completed (triggers an interrupt)
#0100 : value4
SETUP transaction completed (triggers an interrupt)
#0110 : value5
SETUP data packet received
End of enumeration elements list.
FN : Frame Number
bits : 21 - 23 (3 bit)
access : read-only
Receive Status Read and Pop Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EPNum : Endpoint Number
bits : 0 - 2 (3 bit)
access : read-only
BCnt : Byte Count
bits : 4 - 13 (10 bit)
access : read-only
DPID : Data PID
bits : 15 - 15 (1 bit)
access : read-only
Enumeration:
#00 : value1
DATA0
#10 : value2
DATA1
#01 : value3
DATA2
#11 : value4
MDATA
End of enumeration elements list.
PktSts : Packet Status
bits : 17 - 19 (3 bit)
access : read-only
Enumeration:
#0001 : value1
Global OUT NAK (triggers an interrupt)
#0010 : value2
OUT data packet received
#0011 : value3
OUT transfer completed (triggers an interrupt)
#0100 : value4
SETUP transaction completed (triggers an interrupt)
#0110 : value5
SETUP data packet received
End of enumeration elements list.
FN : Frame Number
bits : 21 - 23 (3 bit)
access : read-only
Receive FIFO Size Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RxFDep : RxFIFO Depth
bits : 0 - 14 (15 bit)
access : read-write
Non-Periodic Transmit FIFO Size Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INEPTxF0StAddr : IN Endpoint FIFO0 Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write
INEPTxF0Dep : IN Endpoint TxFIFO 0 Depth
bits : 16 - 30 (15 bit)
access : read-write
USB Module Identification Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_REV : Module Revision
bits : 0 - 6 (7 bit)
access : read-write
MOD_TYPE : Module Type
bits : 8 - 14 (7 bit)
access : read-write
MOD_NUMBER : Module Number
bits : 16 - 30 (15 bit)
access : read-write
Global DFIFO Software Config Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GDFIFOCfg : GDFIFOCfg
bits : 0 - 14 (15 bit)
access : read-write
EPInfoBaseAddr : EPInfoBaseAddr
bits : 16 - 30 (15 bit)
access : read-write
AHB Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GlblIntrMsk : Global Interrupt Mask
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Mask the interrupt assertion to the application.
#1 : value2
Unmask the interrupt assertion to the application.
End of enumeration elements list.
HBstLen : Burst Length/Type
bits : 1 - 3 (3 bit)
access : read-write
Enumeration:
#0000 : value1
Single
#0001 : value2
INCR
#0011 : value3
INCR4
#0101 : value4
INCR8
#0111 : value5
INCR16
End of enumeration elements list.
DMAEn : DMA Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Core operates in Slave mode
#1 : value2
Core operates in a DMA mode
End of enumeration elements list.
NPTxFEmpLvl : Non-Periodic TxFIFO Empty Level
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
DIEPINTx.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty
#1 : value2
DIEPINTx.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is completely empty
End of enumeration elements list.
AHBSingle : AHB Single Support
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : value1
The remaining data in a transfer is sent using INCR burst size. This is the default mode.
#1 : value2
The remaining data in a transfer is sent using single burst size.
End of enumeration elements list.
Device Configuration Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DevSpd : Device Speed
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#11 : value4
Full speed (USB 1.1 transceiver clock is 48 MHz)
End of enumeration elements list.
NZStsOUTHShk : Non-Zero-Length Status OUT Handshake
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#1 : value1
Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application.
#0 : value2
Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register.
End of enumeration elements list.
DevAddr : Device Address
bits : 4 - 9 (6 bit)
access : read-write
PerFrInt : Periodic Frame Interval
bits : 11 - 11 (1 bit)
access : read-write
Enumeration:
#00 : value1
80% of the frame interval
#01 : value2
85%
#10 : value3
90%
#11 : value4
95%
End of enumeration elements list.
DescDMA : Enable Scatter/Gather DMA in Device mode.
bits : 23 - 22 (0 bit)
access : read-write
PerSchIntvl : Periodic Scheduling Interval
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#00 : value1
25% of frame.
#01 : value2
50% of frame.
#10 : value3
75% of frame.
End of enumeration elements list.
Device Control Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RmtWkUpSig : Remote Wakeup Signaling
bits : 0 - -1 (0 bit)
access : read-write
SftDiscon : Soft Disconnect
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Normal operation. When this bit is cleared after a soft disconnect, the core drives a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration.
#1 : value2
The core drives a device disconnect event to the USB host.
End of enumeration elements list.
GNPINNakSts : Global Non-periodic IN NAK Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
A handshake is sent out based on the data availability in the transmit FIFO.
#1 : value2
A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO.
End of enumeration elements list.
GOUTNakSts : Global OUT NAK Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.
#1 : value2
No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped.
End of enumeration elements list.
SGNPInNak : Set Global Non-periodic IN NAK
bits : 7 - 6 (0 bit)
access : write-only
CGNPInNak : Clear Global Non-periodic IN NAK
bits : 8 - 7 (0 bit)
access : write-only
SGOUTNak : Set Global OUT NAK
bits : 9 - 8 (0 bit)
access : write-only
CGOUTNak : Clear Global OUT NAK
bits : 10 - 9 (0 bit)
access : write-only
GMC : Global Multi Count
bits : 13 - 13 (1 bit)
access : read-write
Enumeration:
#00 : value1
Invalid.
#01 : value2
1 packet.
#10 : value3
2 packets.
#11 : value4
3 packets.
End of enumeration elements list.
IgnrFrmNum : Ignore frame number for isochronous endpoints in case of Scatter/Gather DMA
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
Scatter/Gather enabled: The core transmits the packets only in the frame number in which they are intended to be transmitted. Scatter/Gather disabled: Periodic transfer interrupt feature is disabled; the application must program transfers for periodic endpoints every frame
#1 : value2
Scatter/Gather enabled: The core ignores the frame number, sending packets immediately as the packets are ready. Scatter/Gather disabled: Periodic transfer interrupt feature is enabled; the application can program transfers for multiple frames for periodic endpoints.
End of enumeration elements list.
NakOnBble : Set NAK automatically on babble
bits : 16 - 15 (0 bit)
access : read-write
EnContOnBNA : Enable continue on BNA
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the DOEPDMA descriptor.
#1 : value2
After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the descriptor that received the BNA interrupt.
End of enumeration elements list.
Device Status Register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SuspSts : Suspend Status
bits : 0 - -1 (0 bit)
access : read-only
EnumSpd : Enumerated Speed
bits : 1 - 1 (1 bit)
access : read-only
Enumeration:
#11 : value4
Full speed (PHY clock is running at 48 MHz)
End of enumeration elements list.
ErrticErr : Erratic Error
bits : 3 - 2 (0 bit)
access : read-only
SOFFN : Frame Number of the Received SOF
bits : 8 - 20 (13 bit)
access : read-only
Device IN Endpoint Common Interrupt Mask Register
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XferComplMsk : Transfer Completed Interrupt Mask
bits : 0 - -1 (0 bit)
access : read-write
EPDisbldMsk : Endpoint Disabled Interrupt Mask
bits : 1 - 0 (0 bit)
access : read-write
AHBErrMsk : AHB Error Mask
bits : 2 - 1 (0 bit)
access : read-write
TimeOUTMsk : Timeout Condition Mask
bits : 3 - 2 (0 bit)
access : read-write
INTknTXFEmpMsk : IN Token Received When TxFIFO Empty Mask
bits : 4 - 3 (0 bit)
access : read-write
INEPNakEffMsk : IN Endpoint NAK Effective Mask
bits : 6 - 5 (0 bit)
access : read-write
TxfifoUndrnMsk : Fifo Underrun Mask
bits : 8 - 7 (0 bit)
access : read-write
BNAInIntrMsk : BNA Interrupt Mask
bits : 9 - 8 (0 bit)
access : read-write
NAKMsk : NAK interrupt Mask
bits : 13 - 12 (0 bit)
access : read-write
Device OUT Endpoint Common Interrupt Mask Register
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XferComplMsk : Transfer Completed Interrupt Mask
bits : 0 - -1 (0 bit)
access : read-write
EPDisbldMsk : Endpoint Disabled Interrupt Mask
bits : 1 - 0 (0 bit)
access : read-write
AHBErrMsk : AHB Error
bits : 2 - 1 (0 bit)
access : read-write
SetUPMsk : SETUP Phase Done Mask
bits : 3 - 2 (0 bit)
access : read-write
OUTTknEPdisMsk : OUT Token Received when Endpoint Disabled Mask
bits : 4 - 3 (0 bit)
access : read-write
Back2BackSETup : Back-to-Back SETUP Packets Received Mask
bits : 6 - 5 (0 bit)
access : read-write
OutPktErrMsk : OUT Packet Error Mask
bits : 8 - 7 (0 bit)
access : read-write
BnaOutIntrMsk : BNA interrupt Mask
bits : 9 - 8 (0 bit)
access : read-write
BbleErrMsk : Babble Interrupt Mask
bits : 12 - 11 (0 bit)
access : read-write
NAKMsk : NAK Interrupt Mask
bits : 13 - 12 (0 bit)
access : read-write
NYETMsk : NYET Interrupt Mask
bits : 14 - 13 (0 bit)
access : read-write
Device All Endpoints Interrupt Register
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
InEpInt : IN Endpoint Interrupt Bits
bits : 0 - 14 (15 bit)
access : read-only
OutEPInt : OUT Endpoint Interrupt Bits
bits : 16 - 30 (15 bit)
access : read-only
Device All Endpoints Interrupt Mask Register
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
InEpMsk : IN EP Interrupt Mask Bits
bits : 0 - 14 (15 bit)
access : read-write
OutEpMsk : OUT EP Interrupt Mask Bits
bits : 16 - 30 (15 bit)
access : read-write
Device VBUS Discharge Time Register
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVBUSDis : Device Vbus Discharge Time
bits : 0 - 14 (15 bit)
access : read-write
Device VBUS Pulsing Time Register
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DVBUSPulse : Device Vbus Pulsing Time
bits : 0 - 10 (11 bit)
access : read-write
Device IN Endpoint FIFO Empty Interrupt Mask Register
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
InEpTxfEmpMsk : IN EP Tx FIFO Empty Interrupt Mask Bits
bits : 0 - 14 (15 bit)
access : read-write
USB Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TOutCal : FS Timeout Calibration
bits : 0 - 1 (2 bit)
access : read-write
PHYSel : USB 1.1 Full-Speed Serial Transceiver Select
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#1 : value2
USB 1.1 full-speed serial transceiver
End of enumeration elements list.
USBTrdTim : USB Turnaround Time
bits : 10 - 12 (3 bit)
access : read-write
TxEndDelay : Tx End Delay
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : value1
Normal mode
#1 : value2
Introduce Tx end delay timers
End of enumeration elements list.
ForceDevMode : Force Device Mode
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : value1
Normal Mode
#1 : value2
Force Device Mode
End of enumeration elements list.
CTP : Corrupt Tx packet
bits : 31 - 30 (0 bit)
access : read-write
Power and Clock Gating Control Register
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
StopPclk : Stop Pclk
bits : 0 - -1 (0 bit)
access : read-write
GateHclk : Gate Hclk
bits : 1 - 0 (0 bit)
access : read-write
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