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SCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

ID

STCON

GPR0

GPR1

IDCHIP

CCUCON

IDMANUF

DTSCON

DTSSTAT

SDMMCDEL

G0ORCEN

G1ORCEN

MIRRSTS

RMACR

RMDATA


ID

SCU Module ID Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ID ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOD_REV MOD_TYPE MOD_NUMBER

MOD_REV : Module Revision
bits : 0 - 6 (7 bit)
access : read-only

MOD_TYPE : Module Type
bits : 8 - 14 (7 bit)
access : read-only

MOD_NUMBER : Module Number
bits : 16 - 30 (15 bit)
access : read-only


STCON

Startup Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCON STCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HWCON SWCON

HWCON : HW Configuration
bits : 0 - 0 (1 bit)
access : read-only

Enumeration:

#00 : Const_00

Normal mode, JTAG

#01 : Const_01

ASC BSL enabled

#10 : Const_10

BMI customized boot enabled

#11 : Const_11

CAN BSL enabled

End of enumeration elements list.

SWCON : SW Configuration
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : Const_0000

Normal mode, boot from Boot ROM

#0001 : Const_0001

ASC BSL enabled

#0010 : Const_0010

BMI customized boot enabled

#0011 : Const_0011

CAN BSL enabled

#0100 : Const_0100

Boot from Code SRAM

#1000 : Const_1000

Boot from alternate Flash Address 0

#1100 : Const_1100

Boot from alternate Flash Address 1

#1110 : Const_1110

Enable fallback Alternate Boot Mode (ABM)

End of enumeration elements list.


GPR0

General Purpose Register 0
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPR0 GPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAT

DAT : User Data
bits : 0 - 30 (31 bit)
access : read-write


GPR1

General Purpose Register 1
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPR1 GPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAT

DAT : User Data
bits : 0 - 30 (31 bit)
access : read-write


IDCHIP

Chip ID Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDCHIP IDCHIP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IDCHIP

IDCHIP : Chip ID
bits : 0 - 30 (31 bit)
access : read-only


CCUCON

CCU Control Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCUCON CCUCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GSC40 GSC41 GSC80

GSC40 : Global Start Control CCU40
bits : 0 - -1 (0 bit)
access : read-write

GSC41 : Global Start Control CCU41
bits : 1 - 0 (0 bit)
access : read-write

GSC80 : Global Start Control CCU80
bits : 8 - 7 (0 bit)
access : read-write


IDMANUF

Manufactory ID Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IDMANUF IDMANUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEPT MANUF

DEPT : Department Identification Number
bits : 0 - 3 (4 bit)
access : read-only

MANUF : Manufacturer Identification Number
bits : 5 - 14 (10 bit)
access : read-only


DTSCON

Die Temperature Sensor Control Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTSCON DTSCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PWD START OFFSET GAIN REFTRIM BGTRIM

PWD : Sensor Power Down
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

The DTS is powered

#1 : Const_1

The DTS is not powered

End of enumeration elements list.

START : Sensor Measurement Start
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : Const_0

No DTS measurement is started

#1 : Const_1

DTS measurement is started

End of enumeration elements list.

OFFSET : Offset Calibration Value
bits : 4 - 9 (6 bit)
access : read-write

GAIN : Gain Calibration Value
bits : 11 - 15 (5 bit)
access : read-write

REFTRIM : Reference Trim Calibration Value
bits : 17 - 18 (2 bit)
access : read-write

BGTRIM : Bandgap Trim Calibration Value
bits : 20 - 22 (3 bit)
access : read-write


DTSSTAT

Die Temperature Sensor Status Register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTSSTAT DTSSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT RDY BUSY

RESULT : Result of the DTS Measurement
bits : 0 - 8 (9 bit)
access : read-only

RDY : Sensor Ready Status
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

The DTS is not ready

#1 : Const_1

The DTS is ready

End of enumeration elements list.

BUSY : Sensor Busy Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

not busy

#1 : Const_1

busy

End of enumeration elements list.


SDMMCDEL

SD-MMC Delay Control Register
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SDMMCDEL SDMMCDEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TAPEN TAPDEL

TAPEN : Enable delay on the CMD/DAT out lines
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disabled

#1 : value2

Enabled

End of enumeration elements list.

TAPDEL : Number of Delay Elements Select
bits : 4 - 6 (3 bit)
access : read-write


G0ORCEN

Out of Range Comparator Enable Register 0
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

G0ORCEN G0ORCEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENORC6 ENORC7

ENORC6 : Enable Out of Range Comparator, Channel 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.

ENORC7 : Enable Out of Range Comparator, Channel 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.


G1ORCEN

Out of Range Comparator Enable Register 1
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

G1ORCEN G1ORCEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENORC6 ENORC7

ENORC6 : Enable Out of Range Comparator, Channel 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.

ENORC7 : Enable Out of Range Comparator, Channel 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

Disabled

#1 : Const_1

Enabled

End of enumeration elements list.


MIRRSTS

Mirror Write Status Register
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MIRRSTS MIRRSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HDCLR HDSET HDCR OSCSICTRL OSCULCTRL RTC_CTR RTC_ATIM0 RTC_ATIM1 RTC_TIM0 RTC_TIM1 RMX RTC_MSKSR RTC_CLRSR

HDCLR : HDCLR Mirror Register Write Status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.

HDSET : HDSET Mirror Register Write Status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.

HDCR : HDCR Mirror Register Write Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.

OSCSICTRL : OSCSICTRL Mirror Register Write Status
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.

OSCULCTRL : OSCULCTRL Mirror Register Write Status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.

RTC_CTR : RTC CTR Mirror Register Write Status
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.

RTC_ATIM0 : RTC ATIM0 Mirror Register Write Status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.

RTC_ATIM1 : RTC ATIM1 Mirror Register Write Status
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.

RTC_TIM0 : RTC TIM0 Mirror Register Write Status
bits : 11 - 10 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.

RTC_TIM1 : RTC TIM1 Mirror Register Write Status
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.

RMX : Retention Memory Access Register Update Status
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.

RTC_MSKSR : RTC MSKSSR Mirror Register Write Status
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.

RTC_CLRSR : RTC CLRSR Mirror Register Write Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : Const_0

Ready

#1 : Const_1

Busy

End of enumeration elements list.


RMACR

Retention Memory Access Control Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RMACR RMACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDWR ADDR

RDWR : Hibernate Retention Memory Register Update Control
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : Const_0

transfer data from Retention Memory in Hibernate domain to RMDATA register

#1 : Const_1

transfer data from RMDATA into Retention Memory in Hibernate domain

End of enumeration elements list.

ADDR : Hibernate Retention Memory Register Address Select
bits : 16 - 18 (3 bit)
access : read-write


RMDATA

Retention Memory Access Data Register
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RMDATA RMDATA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA

DATA : Hibernate Retention Memory Data
bits : 0 - 30 (31 bit)
access : read-write



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