Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
RECEIVE_DESCRIPTOR_LIST_ADDRESS
TRANSMIT_DESCRIPTOR_LIST_ADDRESS
MISSED_FRAME_AND_BUFFER_OVERFLOW_COUNTER
RECEIVE_INTERRUPT_WATCHDOG_TIMER
CURRENT_HOST_TRANSMIT_DESCRIPTOR
CURRENT_HOST_RECEIVE_DESCRIPTOR
CURRENT_HOST_TRANSMIT_BUFFER_ADDRESS
CURRENT_HOST_RECEIVE_BUFFER_ADDRESS
TX_65TO127OCTETS_FRAMES_GOOD_BAD
TX_128TO255OCTETS_FRAMES_GOOD_BAD
TX_256TO511OCTETS_FRAMES_GOOD_BAD
TX_512TO1023OCTETS_FRAMES_GOOD_BAD
TX_1024TOMAXOCTETS_FRAMES_GOOD_BAD
TX_SINGLE_COLLISION_GOOD_FRAMES
TX_MULTIPLE_COLLISION_GOOD_FRAMES
RX_65TO127OCTETS_FRAMES_GOOD_BAD
RX_128TO255OCTETS_FRAMES_GOOD_BAD
RX_256TO511OCTETS_FRAMES_GOOD_BAD
RX_512TO1023OCTETS_FRAMES_GOOD_BAD
RX_1024TOMAXOCTETS_FRAMES_GOOD_BAD
MMC_IPC_RECEIVE_INTERRUPT_MASK
RXIPV4_UDP_CHECKSUM_DISABLED_FRAMES
RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS
SYSTEM_TIME_NANOSECONDS_UPDATE
SYSTEM_TIME_HIGHER_WORD_SECONDS
MAC Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRELEN : Preamble Length for Transmit Frames
bits : 0 - 0 (1 bit)
access : read-write
RE : Receiver Enable
bits : 2 - 1 (0 bit)
access : read-write
TE : Transmitter Enable
bits : 3 - 2 (0 bit)
access : read-write
DC : Deferral Check
bits : 4 - 3 (0 bit)
access : read-write
BL : Back-Off Limit
bits : 5 - 5 (1 bit)
access : read-write
ACS : Automatic Pad or CRC Stripping
bits : 7 - 6 (0 bit)
access : read-write
DR : Disable Retry
bits : 9 - 8 (0 bit)
access : read-write
IPC : Checksum Offload
bits : 10 - 9 (0 bit)
access : read-write
DM : Duplex Mode
bits : 11 - 10 (0 bit)
access : read-write
LM : Loopback Mode
bits : 12 - 11 (0 bit)
access : read-write
DO : Disable Receive Own
bits : 13 - 12 (0 bit)
access : read-write
FES : Speed
bits : 14 - 13 (0 bit)
access : read-write
DCRS : Disable Carrier Sense During Transmission
bits : 16 - 15 (0 bit)
access : read-write
IFG : Inter-Frame Gap
bits : 17 - 18 (2 bit)
access : read-write
JE : Jumbo Frame Enable
bits : 20 - 19 (0 bit)
access : read-write
BE : Frame Burst Enable
bits : 21 - 20 (0 bit)
access : read-only
JD : Jabber Disable
bits : 22 - 21 (0 bit)
access : read-write
WD : Watchdog Disable
bits : 23 - 22 (0 bit)
access : read-write
TC : Transmit Configuration in RMII
bits : 24 - 23 (0 bit)
access : read-only
CST : CRC Stripping of Type Frames
bits : 25 - 24 (0 bit)
access : read-write
TWOKPE : IEEE 802.3as support for 2K packets Enable
bits : 27 - 26 (0 bit)
access : read-write
SARC : Source Address Insertion or Replacement Control
bits : 28 - 29 (2 bit)
access : read-only
MII Address Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MB : MII Busy
bits : 0 - -1 (0 bit)
access : read-write
MW : MII Write
bits : 1 - 0 (0 bit)
access : read-write
CR : CSR Clock Range
bits : 2 - 4 (3 bit)
access : read-write
MR : MII Register
bits : 6 - 9 (4 bit)
access : read-write
PA : Physical Layer Address
bits : 11 - 14 (4 bit)
access : read-write
MMC Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CNTRST : Counters Reset
bits : 0 - -1 (0 bit)
access : read-write
CNTSTOPRO : Counters Stop Rollover
bits : 1 - 0 (0 bit)
access : read-write
RSTONRD : Reset on Read
bits : 2 - 1 (0 bit)
access : read-write
CNTFREEZ : MMC Counter Freeze
bits : 3 - 2 (0 bit)
access : read-write
CNTPRST : Counters Preset
bits : 4 - 3 (0 bit)
access : read-write
CNTPRSTLVL : Full-Half Preset
bits : 5 - 4 (0 bit)
access : read-write
UCDBC : Update MMC Counters for Dropped Broadcast Frames
bits : 8 - 7 (0 bit)
access : read-write
Bus Mode Register
address_offset : 0x1000 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SWR : Software Reset
bits : 0 - -1 (0 bit)
access : read-write
DA : DMA Arbitration Scheme
bits : 1 - 0 (0 bit)
access : read-write
DSL : Descriptor Skip Length
bits : 2 - 5 (4 bit)
access : read-write
ATDS : Alternate Descriptor Size
bits : 7 - 6 (0 bit)
access : read-write
PBL : Programmable Burst Length
bits : 8 - 12 (5 bit)
access : read-write
PR : Priority Ratio
bits : 14 - 14 (1 bit)
access : read-write
FB : Fixed Burst
bits : 16 - 15 (0 bit)
access : read-write
RPBL : Rx DMA PBL
bits : 17 - 21 (5 bit)
access : read-write
USP : Use Seperate PBL
bits : 23 - 22 (0 bit)
access : read-write
PBLX8 : 8xPBL Mode
bits : 24 - 23 (0 bit)
access : read-write
AAL : Address Aligned Beats
bits : 25 - 24 (0 bit)
access : read-write
MB : Mixed Burst
bits : 26 - 25 (0 bit)
access : read-write
TXPR : Transmit Priority
bits : 27 - 26 (0 bit)
access : read-write
PRWG : Channel Priority Weights
bits : 28 - 28 (1 bit)
access : read-only
Transmit Poll Demand Register
address_offset : 0x1004 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TPD : Transmit Poll Demand
bits : 0 - 30 (31 bit)
access : read-write
Receive Poll Demand Register
address_offset : 0x1008 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPD : Receive Poll Demand
bits : 0 - 30 (31 bit)
access : read-write
Receive Descriptor Address Register
address_offset : 0x100C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDESLA_32bit : Start of Receive List
bits : 2 - 30 (29 bit)
access : read-write
Transmit descripter Address Register
address_offset : 0x1010 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDESLA_32bit : Start of Transmit List
bits : 2 - 30 (29 bit)
access : read-write
Status Register
address_offset : 0x1014 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TI : Transmit Interrupt
bits : 0 - -1 (0 bit)
access : read-write
TPS : Transmit Process Stopped
bits : 1 - 0 (0 bit)
access : read-write
TU : Transmit Buffer Unavailable
bits : 2 - 1 (0 bit)
access : read-write
TJT : Transmit Jabber Timeout
bits : 3 - 2 (0 bit)
access : read-write
OVF : Receive Overflow
bits : 4 - 3 (0 bit)
access : read-write
UNF : Transmit Underflow
bits : 5 - 4 (0 bit)
access : read-write
RI : Receive Interrupt
bits : 6 - 5 (0 bit)
access : read-write
RU : Receive Buffer Unavailable
bits : 7 - 6 (0 bit)
access : read-write
RPS : Receive Process Stopped
bits : 8 - 7 (0 bit)
access : read-write
RWT : Receive Watchdog Timeout
bits : 9 - 8 (0 bit)
access : read-write
ETI : Early Transmit Interrupt
bits : 10 - 9 (0 bit)
access : read-write
FBI : Fatal Bus Error Interrupt
bits : 13 - 12 (0 bit)
access : read-write
ERI : Early Receive Interrupt
bits : 14 - 13 (0 bit)
access : read-write
AIS : Abnormal Interrupt Summary
bits : 15 - 14 (0 bit)
access : read-write
NIS : Normal Interrupt Summary
bits : 16 - 15 (0 bit)
access : read-write
RS : Received Process State
bits : 17 - 18 (2 bit)
access : read-only
TS : Transmit Process State
bits : 20 - 21 (2 bit)
access : read-only
EB : Error Bits
bits : 23 - 24 (2 bit)
access : read-only
EMI : ETH MMC Interrupt
bits : 27 - 26 (0 bit)
access : read-only
EPI : ETH PMT Interrupt
bits : 28 - 27 (0 bit)
access : read-only
TTI : Timestamp Trigger Interrupt
bits : 29 - 28 (0 bit)
access : read-only
Operation Mode Register
address_offset : 0x1018 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SR : Start or Stop Receive
bits : 1 - 0 (0 bit)
access : read-write
OSF : Operate on Second Frame
bits : 2 - 1 (0 bit)
access : read-write
RTC : Receive Threshold Control
bits : 3 - 3 (1 bit)
access : read-write
FUF : Forward Undersized Good Frames
bits : 6 - 5 (0 bit)
access : read-write
FEF : Forward Error Frames
bits : 7 - 6 (0 bit)
access : read-write
ST : Start or Stop Transmission Command
bits : 13 - 12 (0 bit)
access : read-write
TTC : Transmit Threshold Control
bits : 14 - 15 (2 bit)
access : read-write
FTF : Flush Transmit FIFO
bits : 20 - 19 (0 bit)
access : read-write
TSF : Transmit Store and Forward
bits : 21 - 20 (0 bit)
access : read-write
DFF : Disable Flushing of Received Frames
bits : 24 - 23 (0 bit)
access : read-write
RSF : Receive Store and Forward
bits : 25 - 24 (0 bit)
access : read-write
DT : Disable Dropping of TCP/IP Checksum Error Frames
bits : 26 - 25 (0 bit)
access : read-write
Interrupt Enable Register
address_offset : 0x101C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIE : Transmit Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
TSE : Transmit Stopped Enable
bits : 1 - 0 (0 bit)
access : read-write
TUE : Transmit Buffer Unvailable Enable
bits : 2 - 1 (0 bit)
access : read-write
TJE : Transmit Jabber Timeout Enable
bits : 3 - 2 (0 bit)
access : read-write
OVE : Overflow Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
UNE : Underflow Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
RIE : Receive Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
RUE : Receive Buffer Unavailable Enable
bits : 7 - 6 (0 bit)
access : read-write
RSE : Receive Stopped Enable
bits : 8 - 7 (0 bit)
access : read-write
RWE : Receive Watchdog Timeout Enable
bits : 9 - 8 (0 bit)
access : read-write
ETE : Early Transmit Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
FBE : Fatal Bus Error Enable
bits : 13 - 12 (0 bit)
access : read-write
ERE : Early Receive Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
AIE : Abnormal Interrupt Summary Enable
bits : 15 - 14 (0 bit)
access : read-write
NIE : Normal Interrupt Summary Enable
bits : 16 - 15 (0 bit)
access : read-write
Missed Frame and Buffer Overflow Counter Register
address_offset : 0x1020 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MISFRMCNT : This field indicates the number of frames missed by the controller because of the RAM Receive Buffer being unavailable. This counter is incremented each time the DMA discards an incoming frame. The counter is cleared when this register is read.
bits : 0 - 14 (15 bit)
access : read-only
MISCNTOVF : Overflow bit for Missed Frame Counter
bits : 16 - 15 (0 bit)
access : read-only
OVFFRMCNT : This field indicates the number of frames missed by the application. The counter is cleared when this register is read.
bits : 17 - 26 (10 bit)
access : read-only
OVFCNTOVF : Overflow bit for FIFO Overflow Counter
bits : 28 - 27 (0 bit)
access : read-only
Receive Interrupt Watchdog Timer Register
address_offset : 0x1024 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIWT : RI Watchdog Timer Count
bits : 0 - 6 (7 bit)
access : read-write
AHB Status Register
address_offset : 0x102C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
AHBMS : AHB Master Status
bits : 0 - -1 (0 bit)
access : read-only
MMC Receive Interrupt Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXGBFRMIS : MMC Receive Good Bad Frame Counter Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only
RXGBOCTIS : MMC Receive Good Bad Octet Counter Interrupt Status
bits : 1 - 0 (0 bit)
access : read-only
RXGOCTIS : MMC Receive Good Octet Counter Interrupt Status.
bits : 2 - 1 (0 bit)
access : read-only
RXBCGFIS : MMC Receive Broadcast Good Frame Counter Interrupt Status.
bits : 3 - 2 (0 bit)
access : read-only
RXMCGFIS : MMC Receive Multicast Good Frame Counter Interrupt Status
bits : 4 - 3 (0 bit)
access : read-only
RXCRCERFIS : MMC Receive CRC Error Frame Counter Interrupt Status
bits : 5 - 4 (0 bit)
access : read-only
RXALGNERFIS : MMC Receive Alignment Error Frame Counter Interrupt Status
bits : 6 - 5 (0 bit)
access : read-only
RXRUNTFIS : MMC Receive Runt Frame Counter Interrupt Status
bits : 7 - 6 (0 bit)
access : read-only
RXJABERFIS : MMC Receive Jabber Error Frame Counter Interrupt Status
bits : 8 - 7 (0 bit)
access : read-only
RXUSIZEGFIS : MMC Receive Undersize Good Frame Counter Interrupt Status
bits : 9 - 8 (0 bit)
access : read-only
RXOSIZEGFIS : MMC Receive Oversize Good Frame Counter Interrupt Status
bits : 10 - 9 (0 bit)
access : read-only
RX64OCTGBFIS : MMC Receive 64 Octet Good Bad Frame Counter Interrupt Status
bits : 11 - 10 (0 bit)
access : read-only
RX65T127OCTGBFIS : MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Status
bits : 12 - 11 (0 bit)
access : read-only
RX128T255OCTGBFIS : MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Status
bits : 13 - 12 (0 bit)
access : read-only
RX256T511OCTGBFIS : MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Status
bits : 14 - 13 (0 bit)
access : read-only
RX512T1023OCTGBFIS : MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Status
bits : 15 - 14 (0 bit)
access : read-only
RX1024TMAXOCTGBFIS : MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status
bits : 16 - 15 (0 bit)
access : read-only
RXUCGFIS : MMC Receive Unicast Good Frame Counter Interrupt Status
bits : 17 - 16 (0 bit)
access : read-only
RXLENERFIS : MMC Receive Length Error Frame Counter Interrupt Status
bits : 18 - 17 (0 bit)
access : read-only
RXORANGEFIS : MMC Receive Out Of Range Error Frame Counter Interrupt Status
bits : 19 - 18 (0 bit)
access : read-only
RXPAUSFIS : MMC Receive Pause Frame Counter Interrupt Status
bits : 20 - 19 (0 bit)
access : read-only
RXFOVFIS : MMC Receive FIFO Overflow Frame Counter Interrupt Status
bits : 21 - 20 (0 bit)
access : read-only
RXVLANGBFIS : MMC Receive VLAN Good Bad Frame Counter Interrupt Status
bits : 22 - 21 (0 bit)
access : read-only
RXWDOGFIS : MMC Receive Watchdog Error Frame Counter Interrupt Status
bits : 23 - 22 (0 bit)
access : read-only
RXRCVERRFIS : MMC Receive Error Frame Counter Interrupt Status
bits : 24 - 23 (0 bit)
access : read-only
RXCTRLFIS : MMC Receive Control Frame Counter Interrupt Status
bits : 25 - 24 (0 bit)
access : read-only
Current Host Transmit Descriptor Register
address_offset : 0x1048 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURTDESAPTR : Host Transmit Descriptor Address Pointer
bits : 0 - 30 (31 bit)
access : read-only
Current Host Receive Descriptor Register
address_offset : 0x104C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURRDESAPTR : Host Receive Descriptor Address Pointer
bits : 0 - 30 (31 bit)
access : read-only
Current Host Transmit Buffer Address Register
address_offset : 0x1050 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURTBUFAPTR : Host Transmit Buffer Address Pointer
bits : 0 - 30 (31 bit)
access : read-only
Current Host Receive Buffer Address Register
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURRBUFAPTR : Host Receive Buffer Address Pointer
bits : 0 - 30 (31 bit)
access : read-only
HW Feature Register
address_offset : 0x1058 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MIISEL : 10 or 100 Mbps support
bits : 0 - -1 (0 bit)
access : read-only
GMIISEL : 1000 Mbps support
bits : 1 - 0 (0 bit)
access : read-only
HDSEL : Half-Duplex support
bits : 2 - 1 (0 bit)
access : read-only
EXTHASHEN : Expanded DA Hash Filter
bits : 3 - 2 (0 bit)
access : read-only
HASHSEL : HASH Filter
bits : 4 - 3 (0 bit)
access : read-only
ADDMACADRSEL : Multiple MAC Address Registers
bits : 5 - 4 (0 bit)
access : read-only
PCSSEL : PCS registers (TBI, SGMII, or RTBI PHY interface)
bits : 6 - 5 (0 bit)
access : read-only
L3L4FLTREN : Layer 3 and Layer 4 Filter Feature
bits : 7 - 6 (0 bit)
access : read-only
SMASEL : SMA (MDIO) Interface
bits : 8 - 7 (0 bit)
access : read-only
RWKSEL : PMT Remote Wakeup
bits : 9 - 8 (0 bit)
access : read-only
MGKSEL : PMT Magic Packet
bits : 10 - 9 (0 bit)
access : read-only
MMCSEL : RMON Module
bits : 11 - 10 (0 bit)
access : read-only
TSVER1SEL : Only IEEE 1588-2002 Timestamp
bits : 12 - 11 (0 bit)
access : read-only
TSVER2SEL : IEEE 1588-2008 Advanced Timestamp
bits : 13 - 12 (0 bit)
access : read-only
EEESEL : Energy Efficient Ethernet
bits : 14 - 13 (0 bit)
access : read-only
AVSEL : AV Feature
bits : 15 - 14 (0 bit)
access : read-only
TXCOESEL : Checksum Offload in Tx
bits : 16 - 15 (0 bit)
access : read-only
RXTYP1COE : IP Checksum Offload (Type 1) in Rx
bits : 17 - 16 (0 bit)
access : read-only
RXTYP2COE : IP Checksum Offload (Type 2) in Rx
bits : 18 - 17 (0 bit)
access : read-only
RXFIFOSIZE : Rx FIFO > 2,048 Bytes
bits : 19 - 18 (0 bit)
access : read-write
RXCHCNT : Number of additional Rx channels
bits : 20 - 20 (1 bit)
access : read-only
TXCHCNT : Number of additional Tx channels
bits : 22 - 22 (1 bit)
access : read-only
ENHDESSEL : Alternate (Enhanced Descriptor)
bits : 24 - 23 (0 bit)
access : read-only
INTTSEN : Timestamping with Internal System Time
bits : 25 - 24 (0 bit)
access : read-only
FLEXIPPSEN : Flexible Pulse-Per-Second Output
bits : 26 - 25 (0 bit)
access : read-only
SAVLANINS : Source Address or VLAN Insertion
bits : 27 - 26 (0 bit)
access : read-only
ACTPHYIF : Active or Selected PHY interface
bits : 28 - 29 (2 bit)
access : read-only
MMC Transmit Interrupt Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXGBOCTIS : MMC Transmit Good Bad Octet Counter Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only
TXGBFRMIS : MMC Transmit Good Bad Frame Counter Interrupt Status
bits : 1 - 0 (0 bit)
access : read-only
TXBCGFIS : MMC Transmit Broadcast Good Frame Counter Interrupt Status
bits : 2 - 1 (0 bit)
access : read-only
TXMCGFIS : MMC Transmit Multicast Good Frame Counter Interrupt Status
bits : 3 - 2 (0 bit)
access : read-only
TX64OCTGBFIS : MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Status.
bits : 4 - 3 (0 bit)
access : read-only
TX65T127OCTGBFIS : MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Status
bits : 5 - 4 (0 bit)
access : read-only
TX128T255OCTGBFIS : MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Status
bits : 6 - 5 (0 bit)
access : read-only
TX256T511OCTGBFIS : MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Status
bits : 7 - 6 (0 bit)
access : read-only
TX512T1023OCTGBFIS : MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Status
bits : 8 - 7 (0 bit)
access : read-only
TX1024TMAXOCTGBFIS : MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Status
bits : 9 - 8 (0 bit)
access : read-only
TXUCGBFIS : MMC Transmit Unicast Good Bad Frame Counter Interrupt Status
bits : 10 - 9 (0 bit)
access : read-only
TXMCGBFIS : MMC Transmit Multicast Good Bad Frame Counter Interrupt Status
bits : 11 - 10 (0 bit)
access : read-only
TXBCGBFIS : MMC Transmit Broadcast Good Bad Frame Counter Interrupt Status
bits : 12 - 11 (0 bit)
access : read-only
TXUFLOWERFIS : MMC Transmit Underflow Error Frame Counter Interrupt Status
bits : 13 - 12 (0 bit)
access : read-only
TXSCOLGFIS : MMC Transmit Single Collision Good Frame Counter Interrupt Status
bits : 14 - 13 (0 bit)
access : read-only
TXMCOLGFIS : MMC Transmit Multiple Collision Good Frame Counter Interrupt Status
bits : 15 - 14 (0 bit)
access : read-only
TXDEFFIS : MMC Transmit Deferred Frame Counter Interrupt Status
bits : 16 - 15 (0 bit)
access : read-only
TXLATCOLFIS : MMC Transmit Late Collision Frame Counter Interrupt Status
bits : 17 - 16 (0 bit)
access : read-only
TXEXCOLFIS : MMC Transmit Excessive Collision Frame Counter Interrupt Status
bits : 18 - 17 (0 bit)
access : read-only
TXCARERFIS : MMC Transmit Carrier Error Frame Counter Interrupt Status
bits : 19 - 18 (0 bit)
access : read-only
TXGOCTIS : MMC Transmit Good Octet Counter Interrupt Status
bits : 20 - 19 (0 bit)
access : read-only
TXGFRMIS : MMC Transmit Good Frame Counter Interrupt Status
bits : 21 - 20 (0 bit)
access : read-only
TXEXDEFFIS : MMC Transmit Excessive Deferral Frame Counter Interrupt Status
bits : 22 - 21 (0 bit)
access : read-only
TXPAUSFIS : MMC Transmit Pause Frame Counter Interrupt Status
bits : 23 - 22 (0 bit)
access : read-only
TXVLANGFIS : MMC Transmit VLAN Good Frame Counter Interrupt Status
bits : 24 - 23 (0 bit)
access : read-only
TXOSIZEGFIS : MMC Transmit Oversize Good Frame Counter Interrupt Status
bits : 25 - 24 (0 bit)
access : read-only
MMC Reveive Interrupt Mask Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXGBFRMIM : MMC Receive Good Bad Frame Counter Interrupt Mask
bits : 0 - -1 (0 bit)
access : read-write
RXGBOCTIM : MMC Receive Good Bad Octet Counter Interrupt Mask
bits : 1 - 0 (0 bit)
access : read-write
RXGOCTIM : MMC Receive Good Octet Counter Interrupt Mask
bits : 2 - 1 (0 bit)
access : read-write
RXBCGFIM : MMC Receive Broadcast Good Frame Counter Interrupt Mask
bits : 3 - 2 (0 bit)
access : read-write
RXMCGFIM : MMC Receive Multicast Good Frame Counter Interrupt Mask
bits : 4 - 3 (0 bit)
access : read-write
RXCRCERFIM : MMC Receive CRC Error Frame Counter Interrupt Mask
bits : 5 - 4 (0 bit)
access : read-write
RXALGNERFIM : MMC Receive Alignment Error Frame Counter Interrupt Mask
bits : 6 - 5 (0 bit)
access : read-write
RXRUNTFIM : MMC Receive Runt Frame Counter Interrupt Mask
bits : 7 - 6 (0 bit)
access : read-write
RXJABERFIM : MMC Receive Jabber Error Frame Counter Interrupt Mask
bits : 8 - 7 (0 bit)
access : read-write
RXUSIZEGFIM : MMC Receive Undersize Good Frame Counter Interrupt Mask
bits : 9 - 8 (0 bit)
access : read-write
RXOSIZEGFIM : MMC Receive Oversize Good Frame Counter Interrupt Mask
bits : 10 - 9 (0 bit)
access : read-write
RX64OCTGBFIM : MMC Receive 64 Octet Good Bad Frame Counter Interrupt Mask
bits : 11 - 10 (0 bit)
access : read-write
RX65T127OCTGBFIM : MMC Receive 65 to 127 Octet Good Bad Frame Counter Interrupt Mask
bits : 12 - 11 (0 bit)
access : read-write
RX128T255OCTGBFIM : MMC Receive 128 to 255 Octet Good Bad Frame Counter Interrupt Mask
bits : 13 - 12 (0 bit)
access : read-write
RX256T511OCTGBFIM : MMC Receive 256 to 511 Octet Good Bad Frame Counter Interrupt Mask
bits : 14 - 13 (0 bit)
access : read-write
RX512T1023OCTGBFIM : MMC Receive 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask
bits : 15 - 14 (0 bit)
access : read-write
RX1024TMAXOCTGBFIM : MMC Receive 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask
bits : 16 - 15 (0 bit)
access : read-write
RXUCGFIM : MMC Receive Unicast Good Frame Counter Interrupt Mask
bits : 17 - 16 (0 bit)
access : read-write
RXLENERFIM : MMC Receive Length Error Frame Counter Interrupt Mask
bits : 18 - 17 (0 bit)
access : read-write
RXORANGEFIM : MMC Receive Out Of Range Error Frame Counter Interrupt Mask
bits : 19 - 18 (0 bit)
access : read-write
RXPAUSFIM : MMC Receive Pause Frame Counter Interrupt Mask
bits : 20 - 19 (0 bit)
access : read-write
RXFOVFIM : MMC Receive FIFO Overflow Frame Counter Interrupt Mask
bits : 21 - 20 (0 bit)
access : read-write
RXVLANGBFIM : MMC Receive VLAN Good Bad Frame Counter Interrupt Mask
bits : 22 - 21 (0 bit)
access : read-write
RXWDOGFIM : MMC Receive Watchdog Error Frame Counter Interrupt Mask
bits : 23 - 22 (0 bit)
access : read-write
RXRCVERRFIM : MMC Receive Error Frame Counter Interrupt Mask
bits : 24 - 23 (0 bit)
access : read-write
RXCTRLFIM : MMC Receive Control Frame Counter Interrupt Mask
bits : 25 - 24 (0 bit)
access : read-write
MMC Transmit Interrupt Mask Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXGBOCTIM : MMC Transmit Good Bad Octet Counter Interrupt Mask
bits : 0 - -1 (0 bit)
access : read-write
TXGBFRMIM : MMC Transmit Good Bad Frame Counter Interrupt Mask
bits : 1 - 0 (0 bit)
access : read-write
TXBCGFIM : MMC Transmit Broadcast Good Frame Counter Interrupt Mask
bits : 2 - 1 (0 bit)
access : read-write
TXMCGFIM : MMC Transmit Multicast Good Frame Counter Interrupt Mask
bits : 3 - 2 (0 bit)
access : read-write
TX64OCTGBFIM : MMC Transmit 64 Octet Good Bad Frame Counter Interrupt Mask
bits : 4 - 3 (0 bit)
access : read-write
TX65T127OCTGBFIM : MMC Transmit 65 to 127 Octet Good Bad Frame Counter Interrupt Mask
bits : 5 - 4 (0 bit)
access : read-write
TX128T255OCTGBFIM : MMC Transmit 128 to 255 Octet Good Bad Frame Counter Interrupt Mask
bits : 6 - 5 (0 bit)
access : read-write
TX256T511OCTGBFIM : MMC Transmit 256 to 511 Octet Good Bad Frame Counter Interrupt Mask
bits : 7 - 6 (0 bit)
access : read-write
TX512T1023OCTGBFIM : MMC Transmit 512 to 1023 Octet Good Bad Frame Counter Interrupt Mask
bits : 8 - 7 (0 bit)
access : read-write
TX1024TMAXOCTGBFIM : MMC Transmit 1024 to Maximum Octet Good Bad Frame Counter Interrupt Mask
bits : 9 - 8 (0 bit)
access : read-write
TXUCGBFIM : MMC Transmit Unicast Good Bad Frame Counter Interrupt Mask
bits : 10 - 9 (0 bit)
access : read-write
TXMCGBFIM : MMC Transmit Multicast Good Bad Frame Counter Interrupt Mask
bits : 11 - 10 (0 bit)
access : read-write
TXBCGBFIM : MMC Transmit Broadcast Good Bad Frame Counter Interrupt Mask
bits : 12 - 11 (0 bit)
access : read-write
TXUFLOWERFIM : MMC Transmit Underflow Error Frame Counter Interrupt Mask
bits : 13 - 12 (0 bit)
access : read-write
TXSCOLGFIM : MMC Transmit Single Collision Good Frame Counter Interrupt Mask
bits : 14 - 13 (0 bit)
access : read-write
TXMCOLGFIM : MMC Transmit Multiple Collision Good Frame Counter Interrupt Mask
bits : 15 - 14 (0 bit)
access : read-write
TXDEFFIM : MMC Transmit Deferred Frame Counter Interrupt Mask
bits : 16 - 15 (0 bit)
access : read-write
TXLATCOLFIM : MMC Transmit Late Collision Frame Counter Interrupt Mask
bits : 17 - 16 (0 bit)
access : read-write
TXEXCOLFIM : MMC Transmit Excessive Collision Frame Counter Interrupt Mask
bits : 18 - 17 (0 bit)
access : read-write
TXCARERFIM : MMC Transmit Carrier Error Frame Counter Interrupt Mask
bits : 19 - 18 (0 bit)
access : read-write
TXGOCTIM : MMC Transmit Good Octet Counter Interrupt Mask
bits : 20 - 19 (0 bit)
access : read-write
TXGFRMIM : MMC Transmit Good Frame Counter Interrupt Mask
bits : 21 - 20 (0 bit)
access : read-write
TXEXDEFFIM : MMC Transmit Excessive Deferral Frame Counter Interrupt Mask
bits : 22 - 21 (0 bit)
access : read-write
TXPAUSFIM : MMC Transmit Pause Frame Counter Interrupt Mask
bits : 23 - 22 (0 bit)
access : read-write
TXVLANGFIM : MMC Transmit VLAN Good Frame Counter Interrupt Mask
bits : 24 - 23 (0 bit)
access : read-write
TXOSIZEGFIM : MMC Transmit Oversize Good Frame Counter Interrupt Mask
bits : 25 - 24 (0 bit)
access : read-write
Transmit Octet Count for Good and Bad Frames Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXOCTGB : This field indicates the number of bytes transmitted in good and bad frames exclusive of preamble and retried bytes.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Goodand Bad Frames Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFRMGB : This field indicates the number of good and bad frames transmitted, exclusive of retried frames
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Good Broadcast Frames
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBCASTG : This field indicates the number of transmitted good broadcast frames.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Good Multicast Frames
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXMCASTG : This field indicates the number of transmitted good multicast frames.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Octet Count for Good and Bad 64 Byte Frames
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX64OCTGB : This field indicates the number of transmitted good and bad frames with length of 64 bytes, exclusive of preamble and retried frames.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Octet Count for Good and Bad 65 to 127 Bytes Frames
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX65_127OCTGB : This field indicates the number of transmitted good and bad frames with length between 65 and 127 (inclusive) bytes, exclusive of preamble and retried frames.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Octet Count for Good and Bad 128 to 255 Bytes Frames
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX128_255OCTGB : This field indicates the number of transmitted good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble and retried frames.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Octet Count for Good and Bad 256 to 511 Bytes Frames
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX256_511OCTGB : This field indicates the number of transmitted good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble and retried frames.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Octet Count for Good and Bad 512 to 1023 Bytes Frames
address_offset : 0x134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX512_1023OCTGB : This field indicates the number of transmitted good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble and retried frames.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Octet Count for Good and Bad 1024 to Maxsize Bytes Frames
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TX1024_MAXOCTGB : This field indicates the number of good and bad frames transmitted with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Good and Bad Unicast Frames
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXUCASTGB : This field indicates the number of transmitted good and bad unicast frames.
bits : 0 - 30 (31 bit)
access : read-only
MII Data Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MD : MII Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit Frame Count for Good and Bad Multicast Frames
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXMCASTGB : This field indicates the number of transmitted good and bad multicast frames.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Good and Bad Broadcast Frames
address_offset : 0x144 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXBCASTGB : This field indicates the number of transmitted good and bad broadcast frames.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Underflow Error Frames
address_offset : 0x148 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXUNDRFLW : This field indicates the number of frames aborted because of frame underflow error.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Frames Transmitted after Single Collision
address_offset : 0x14C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXSNGLCOLG : This field indicates the number of successfully transmitted frames after a single collision in the half-duplex mode.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Frames Transmitted after Multiple Collision
address_offset : 0x150 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXMULTCOLG : This field indicates the number of successfully transmitted frames after multiple collisions in the half-duplex mode.
bits : 0 - 30 (31 bit)
access : read-only
Tx Deferred Frames Register
address_offset : 0x154 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXDEFRD : This field indicates the number of successfully transmitted frames after a deferral in the half-duplex mode.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Late Collision Error Frames
address_offset : 0x158 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXLATECOL : This field indicates the number of frames aborted because of late collision error.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Excessive Collision Error Frames
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEXSCOL : This field indicates the number of frames aborted because of excessive (16) collision error.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Carrier Sense Error Frames
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXCARR : This field indicates the number of frames aborted because of carrier sense error (no carrier or loss of carrier).
bits : 0 - 30 (31 bit)
access : read-only
Tx Octet Count Good Register
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXOCTG : This field indicates the number of bytes transmitted, exclusive of preamble, in good frames.
bits : 0 - 30 (31 bit)
access : read-only
Tx Frame Count Good Register
address_offset : 0x168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXFRMG : This field indicates the number of transmitted good frames, exclusive of preamble.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Excessive Deferral Error Frames
address_offset : 0x16C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXEXSDEF : This field indicates the number of frames aborted because of excessive deferral error, that is, frames deferred for more than two max-sized frame times.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Good PAUSE Frames
address_offset : 0x170 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXPAUSE : This field indicates the number of transmitted good PAUSE frames.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Good VLAN Frames
address_offset : 0x174 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXVLANG : This register maintains the number of transmitted good VLAN frames, exclusive of retried frames.
bits : 0 - 30 (31 bit)
access : read-only
Transmit Frame Count for Good Oversize Frames
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TXOSIZG : This field indicates the number of frames transmitted without errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged frames; 2000 bytes if enabled by setting MAC Configuration.2KPE).
bits : 0 - 30 (31 bit)
access : read-only
Flow Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FCA_BPA : Flow Control Busy or Backpressure Activate
bits : 0 - -1 (0 bit)
access : read-write
TFE : Transmit Flow Control Enable
bits : 1 - 0 (0 bit)
access : read-write
RFE : Receive Flow Control Enable
bits : 2 - 1 (0 bit)
access : read-write
UP : Unicast Pause Frame Detect
bits : 3 - 2 (0 bit)
access : read-write
PLT : Pause Low Threshold
bits : 4 - 4 (1 bit)
access : read-write
DZPQ : Disable Zero-Quanta Pause
bits : 7 - 6 (0 bit)
access : read-write
PT : Pause Time
bits : 16 - 30 (15 bit)
access : read-write
Receive Frame Count for Good and Bad Frames
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFRMGB : This field indicates the number of received good and bad frames.
bits : 0 - 30 (31 bit)
access : read-only
Receive Octet Count for Good and Bad Frames
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXOCTGB : This field indicates the number of bytes received, exclusive of preamble, in good and bad frames.
bits : 0 - 30 (31 bit)
access : read-only
Rx Octet Count Good Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXOCTG : This field indicates the number of bytes received, exclusive of preamble, only in good frames.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Good Broadcast Frames
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXBCASTG : This field indicates the number of received good broadcast frames.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Good Multicast Frames
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXMCASTG : This field indicates the number of received good multicast frames.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for CRC Error Frames
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCRCERR : This field indicates the number of frames received with CRC error.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Alignment Error Frames
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXALGNERR : This field indicates the number of frames received with alignment (dribble) error.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Runt Error Frames
address_offset : 0x19C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRUNTERR : This field indicates the number of frames received with runt error(<64 bytes and CRC error).
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Jabber Error Frames
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXJABERR : This field indicates the number of giant frames received with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC error. If Jumbo Frame mode is enabled, then frames of length greater than 9,018 bytes (9,022 for VLAN tagged) are considered as giant frames.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Undersize Frames
address_offset : 0x1A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXUNDERSZG : This field indicates the number of frames received with length less than 64 bytes and without errors.
bits : 0 - 30 (31 bit)
access : read-only
Rx Oversize Frames Good Register
address_offset : 0x1A8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXOVERSZG : This field indicates the number of frames received without errors, with length greater than the maxsize (1,518 or 1,522 for VLAN tagged frames; 2,000 bytes if enabled by setting MAC Configuration.2KPE).
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Good and Bad 64 Byte Frames
address_offset : 0x1AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX64OCTGB : This field indicates the number of received good and bad frames with length 64 bytes, exclusive of preamble.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Good and Bad 65 to 127 Bytes Frames
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX65_127OCTGB : This field indicates the number of received good and bad frames received with length between 65 and 127 (inclusive) bytes, exclusive of preamble.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Good and Bad 128 to 255 Bytes Frames
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX128_255OCTGB : This field indicates the number of received good and bad frames with length between 128 and 255 (inclusive) bytes, exclusive of preamble.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Good and Bad 256 to 511 Bytes Frames
address_offset : 0x1B8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX256_511OCTGB : This field indicates the number of received good and bad frames with length between 256 and 511 (inclusive) bytes, exclusive of preamble.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Good and Bad 512 to 1,023 Bytes Frames
address_offset : 0x1BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX512_1023OCTGB : This field indicates the number of received good and bad frames with length between 512 and 1,023 (inclusive) bytes, exclusive of preamble.
bits : 0 - 30 (31 bit)
access : read-only
VLAN Tag Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VL : VLAN Tag Identifier for Receive Frames
bits : 0 - 14 (15 bit)
access : read-write
ETV : Enable 12-Bit VLAN Tag Comparison
bits : 16 - 15 (0 bit)
access : read-write
VTIM : VLAN Tag Inverse Match Enable
bits : 17 - 16 (0 bit)
access : read-write
ESVL : Enable S-VLAN
bits : 18 - 17 (0 bit)
access : read-write
VTHM : VLAN Tag Hash Table Match Enable
bits : 19 - 18 (0 bit)
access : read-only
Receive Frame Count for Good and Bad 1,024 to Maxsize Bytes Frames
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RX1024_MAXOCTGB : This field indicates the number of received good and bad frames with length between 1,024 and maxsize (inclusive) bytes, exclusive of preamble and retried frames.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Good Unicast Frames
address_offset : 0x1C4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXUCASTG : This field indicates the number of received good unicast frames.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Length Error Frames
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXLENERR : This field indicates the number of frames received with length error (Length type field not equal to frame size) for all frames with valid length field.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Out of Range Frames
address_offset : 0x1CC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXOUTOFRNG : This field indicates the number of received frames with length field not equal to the valid frame size (greater than 1,500 but less than 1,536).
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for PAUSE Frames
address_offset : 0x1D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXPAUSEFRM : This field indicates the number of received good and valid PAUSE frames.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for FIFO Overflow Frames
address_offset : 0x1D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXFIFOOVFL : This field indicates the number of received frames missed because of FIFO overflow.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Good and Bad VLAN Frames
address_offset : 0x1D8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXVLANFRGB : This field indicates the number of received good and bad VLAN frames.
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Watchdog Error Frames
address_offset : 0x1DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXWDGERR : This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load).
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Receive Error Frames
address_offset : 0x1E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXRCVERR : This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load).
bits : 0 - 30 (31 bit)
access : read-only
Receive Frame Count for Good Control Frames Frames
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXCTRLG : This field indicates the number of frames received with error because of the watchdog timeout error (frames with more than 2,048 bytes data load).
bits : 0 - 30 (31 bit)
access : read-only
Version Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SNPSVER : Synopsys-defined Version (3.7)
bits : 0 - 6 (7 bit)
access : read-only
USERVER : User-defined Version (Configured with the coreConsultant)
bits : 8 - 14 (7 bit)
access : read-only
MMC Receive Checksum Offload Interrupt Mask Register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV4GFIM : MMC Receive IPV4 Good Frame Counter Interrupt Mask
bits : 0 - -1 (0 bit)
access : read-write
RXIPV4HERFIM : MMC Receive IPV4 Header Error Frame Counter Interrupt Mask
bits : 1 - 0 (0 bit)
access : read-write
RXIPV4NOPAYFIM : MMC Receive IPV4 No Payload Frame Counter Interrupt Mask
bits : 2 - 1 (0 bit)
access : read-write
RXIPV4FRAGFIM : MMC Receive IPV4 Fragmented Frame Counter Interrupt Mask
bits : 3 - 2 (0 bit)
access : read-write
RXIPV4UDSBLFIM : MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Mask
bits : 4 - 3 (0 bit)
access : read-write
RXIPV6GFIM : MMC Receive IPV6 Good Frame Counter Interrupt Mask
bits : 5 - 4 (0 bit)
access : read-write
RXIPV6HERFIM : MMC Receive IPV6 Header Error Frame Counter Interrupt Mask
bits : 6 - 5 (0 bit)
access : read-write
RXIPV6NOPAYFIM : MMC Receive IPV6 No Payload Frame Counter Interrupt Mask
bits : 7 - 6 (0 bit)
access : read-write
RXUDPGFIM : MMC Receive UDP Good Frame Counter Interrupt Mask
bits : 8 - 7 (0 bit)
access : read-write
RXUDPERFIM : MMC Receive UDP Error Frame Counter Interrupt Mask
bits : 9 - 8 (0 bit)
access : read-write
RXTCPGFIM : MMC Receive TCP Good Frame Counter Interrupt Mask
bits : 10 - 9 (0 bit)
access : read-write
RXTCPERFIM : MMC Receive TCP Error Frame Counter Interrupt Mask
bits : 11 - 10 (0 bit)
access : read-write
RXICMPGFIM : MMC Receive ICMP Good Frame Counter Interrupt Mask
bits : 12 - 11 (0 bit)
access : read-write
RXICMPERFIM : MMC Receive ICMP Error Frame Counter Interrupt Mask
bits : 13 - 12 (0 bit)
access : read-write
RXIPV4GOIM : MMC Receive IPV4 Good Octet Counter Interrupt Mask
bits : 16 - 15 (0 bit)
access : read-write
RXIPV4HEROIM : MMC Receive IPV4 Header Error Octet Counter Interrupt Mask
bits : 17 - 16 (0 bit)
access : read-write
RXIPV4NOPAYOIM : MMC Receive IPV4 No Payload Octet Counter Interrupt Mask
bits : 18 - 17 (0 bit)
access : read-write
RXIPV4FRAGOIM : MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask
bits : 19 - 18 (0 bit)
access : read-write
RXIPV4UDSBLOIM : MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask
bits : 20 - 19 (0 bit)
access : read-write
RXIPV6GOIM : MMC Receive IPV6 Good Octet Counter Interrupt Mask
bits : 21 - 20 (0 bit)
access : read-write
RXIPV6HEROIM : MMC Receive IPV6 Header Error Octet Counter Interrupt Mask
bits : 22 - 21 (0 bit)
access : read-write
RXIPV6NOPAYOIM : MMC Receive IPV6 No Payload Octet Counter Interrupt Mask
bits : 23 - 22 (0 bit)
access : read-write
RXUDPGOIM : MMC Receive UDP Good Octet Counter Interrupt Mask
bits : 24 - 23 (0 bit)
access : read-write
RXUDPEROIM : MMC Receive UDP Error Octet Counter Interrupt Mask
bits : 25 - 24 (0 bit)
access : read-write
RXTCPGOIM : MMC Receive TCP Good Octet Counter Interrupt Mask
bits : 26 - 25 (0 bit)
access : read-write
RXTCPEROIM : MMC Receive TCP Error Octet Counter Interrupt Mask
bits : 27 - 26 (0 bit)
access : read-write
RXICMPGOIM : MMC Receive ICMP Good Octet Counter Interrupt Mask
bits : 28 - 27 (0 bit)
access : read-write
RXICMPEROIM : MMC Receive ICMP Error Octet Counter Interrupt Mask
bits : 29 - 28 (0 bit)
access : read-write
MMC Receive Checksum Offload Interrupt Register
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV4GFIS : MMC Receive IPV4 Good Frame Counter Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only
RXIPV4HERFIS : MMC Receive IPV4 Header Error Frame Counter Interrupt Status
bits : 1 - 0 (0 bit)
access : read-only
RXIPV4NOPAYFIS : MMC Receive IPV4 No Payload Frame Counter Interrupt Status
bits : 2 - 1 (0 bit)
access : read-only
RXIPV4FRAGFIS : MMC Receive IPV4 Fragmented Frame Counter Interrupt Status
bits : 3 - 2 (0 bit)
access : read-only
RXIPV4UDSBLFIS : MMC Receive IPV4 UDP Checksum Disabled Frame Counter Interrupt Status
bits : 4 - 3 (0 bit)
access : read-only
RXIPV6GFIS : MMC Receive IPV6 Good Frame Counter Interrupt Status
bits : 5 - 4 (0 bit)
access : read-only
RXIPV6HERFIS : MMC Receive IPV6 Header Error Frame Counter Interrupt Status
bits : 6 - 5 (0 bit)
access : read-only
RXIPV6NOPAYFIS : MMC Receive IPV6 No Payload Frame Counter Interrupt Status
bits : 7 - 6 (0 bit)
access : read-only
RXUDPGFIS : MMC Receive UDP Good Frame Counter Interrupt Status
bits : 8 - 7 (0 bit)
access : read-only
RXUDPERFIS : MMC Receive UDP Error Frame Counter Interrupt Status
bits : 9 - 8 (0 bit)
access : read-only
RXTCPGFIS : MMC Receive TCP Good Frame Counter Interrupt Status
bits : 10 - 9 (0 bit)
access : read-only
RXTCPERFIS : MMC Receive TCP Error Frame Counter Interrupt Status
bits : 11 - 10 (0 bit)
access : read-only
RXICMPGFIS : MMC Receive ICMP Good Frame Counter Interrupt Status
bits : 12 - 11 (0 bit)
access : read-only
RXICMPERFIS : MMC Receive ICMP Error Frame Counter Interrupt Status
bits : 13 - 12 (0 bit)
access : read-only
RXIPV4GOIS : MMC Receive IPV4 Good Octet Counter Interrupt Status
bits : 16 - 15 (0 bit)
access : read-only
RXIPV4HEROIS : MMC Receive IPV4 Header Error Octet Counter Interrupt Status
bits : 17 - 16 (0 bit)
access : read-only
RXIPV4NOPAYOIS : MMC Receive IPV4 No Payload Octet Counter Interrupt Status
bits : 18 - 17 (0 bit)
access : read-only
RXIPV4FRAGOIS : MMC Receive IPV4 Fragmented Octet Counter Interrupt Status
bits : 19 - 18 (0 bit)
access : read-only
RXIPV4UDSBLOIS : MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status
bits : 20 - 19 (0 bit)
access : read-only
RXIPV6GOIS : MMC Receive IPV6 Good Octet Counter Interrupt Status
bits : 21 - 20 (0 bit)
access : read-only
RXIPV6HEROIS : MMC Receive IPV6 Header Error Octet Counter Interrupt Status
bits : 22 - 21 (0 bit)
access : read-only
RXIPV6NOPAYOIS : MMC Receive IPV6 No Payload Octet Counter Interrupt Status
bits : 23 - 22 (0 bit)
access : read-only
RXUDPGOIS : MMC Receive UDP Good Octet Counter Interrupt Status
bits : 24 - 23 (0 bit)
access : read-only
RXUDPEROIS : MMC Receive UDP Error Octet Counter Interrupt Status
bits : 25 - 24 (0 bit)
access : read-only
RXTCPGOIS : MMC Receive TCP Good Octet Counter Interrupt Status
bits : 26 - 25 (0 bit)
access : read-only
RXTCPEROIS : MMC Receive TCP Error Octet Counter Interrupt Status
bits : 27 - 26 (0 bit)
access : read-only
RXICMPGOIS : MMC Receive ICMP Good Octet Counter Interrupt Status
bits : 28 - 27 (0 bit)
access : read-only
RXICMPEROIS : MMC Receive ICMP Error Octet Counter Interrupt Status
bits : 29 - 28 (0 bit)
access : read-only
RxIPv4 Good Frames Register
address_offset : 0x210 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV4GDFRM : This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload.
bits : 0 - 30 (31 bit)
access : read-only
Receive IPV4 Header Error Frame Counter Register
address_offset : 0x214 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV4HDRERRFRM : This field indicates the number of IPv4 datagrams received with header errors (checksum, length, or version mismatch).
bits : 0 - 30 (31 bit)
access : read-only
Receive IPV4 No Payload Frame Counter Register
address_offset : 0x218 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV4NOPAYFRM : This field indicates the number of IPv4 datagram frames received that did not have a TCP, UDP, or ICMP payload processed by the Checksum engine.
bits : 0 - 30 (31 bit)
access : read-only
Receive IPV4 Fragmented Frame Counter Register
address_offset : 0x21C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV4FRAGFRM : This field indicates the number of good IPv4 datagrams received with fragmentation.
bits : 0 - 30 (31 bit)
access : read-only
Receive IPV4 UDP Checksum Disabled Frame Counter Register
address_offset : 0x220 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV4UDSBLFRM : This field indicates the number of received good IPv4 datagrams which have the UDP payload with checksum disabled.
bits : 0 - 30 (31 bit)
access : read-only
RxIPv6 Good Frames Register
address_offset : 0x224 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV6GDFRM : This field indicates the number of good IPv6 datagrams received with TCP, UDP, or ICMP payloads.
bits : 0 - 30 (31 bit)
access : read-only
Receive IPV6 Header Error Frame Counter Register
address_offset : 0x228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV6HDRERRFRM : This field indicates the number of IPv6 datagrams received with header errors (length or version mismatch).
bits : 0 - 30 (31 bit)
access : read-only
Receive IPV6 No Payload Frame Counter Register
address_offset : 0x22C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV6NOPAYFRM : This field indicates the number of IPv6 datagram frames received that did not have a TCP, UDP, or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers.
bits : 0 - 30 (31 bit)
access : read-only
RxUDP Good Frames Register
address_offset : 0x230 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXUDPGDFRM : This field indicates the number of good IP datagrams with a good UDP payload. This counter is not updated when the counter is incremented.
bits : 0 - 30 (31 bit)
access : read-only
RxUDP Error Frames Register
address_offset : 0x234 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXUDPERRFRM : This field indicates the number of good IP datagrams whose UDP payload has a checksum error.
bits : 0 - 30 (31 bit)
access : read-only
RxTCP Good Frames Register
address_offset : 0x238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXTCPGDFRM : This field indicates the number of good IP datagrams with a good TCP payload.
bits : 0 - 30 (31 bit)
access : read-only
RxTCP Error Frames Register
address_offset : 0x23C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXTCPERRFRM : This field indicates the number of good IP datagrams whose TCP payload has a checksum error.
bits : 0 - 30 (31 bit)
access : read-only
Debug Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RPESTS : MAC MII Receive Protocol Engine Status
bits : 0 - -1 (0 bit)
access : read-only
RFCFCSTS : MAC Receive Frame Controller FIFO Status
bits : 1 - 1 (1 bit)
access : read-only
RWCSTS : MTL Rx FIFO Write Controller Active Status
bits : 4 - 3 (0 bit)
access : read-only
RRCSTS : MTL Rx FIFO Read Controller State
bits : 5 - 5 (1 bit)
access : read-only
RXFSTS : MTL Rx FIFO Fill-level Status
bits : 8 - 8 (1 bit)
access : read-only
TPESTS : MAC MII Transmit Protocol Engine Status
bits : 16 - 15 (0 bit)
access : read-only
TFCSTS : MAC Transmit Frame Controller Status
bits : 17 - 17 (1 bit)
access : read-only
TXPAUSED : MAC transmitter in PAUSE
bits : 19 - 18 (0 bit)
access : read-only
TRCSTS : MTL Tx FIFO Read Controller Status
bits : 20 - 20 (1 bit)
access : read-only
TWCSTS : MTL Tx FIFO Write Controller Active Status
bits : 22 - 21 (0 bit)
access : read-only
TXFSTS : MTL Tx FIFO Not Empty Status
bits : 24 - 23 (0 bit)
access : read-only
TXSTSFSTS : MTL TxStatus FIFO Full Status
bits : 25 - 24 (0 bit)
access : read-only
RxICMP Good Frames Register
address_offset : 0x240 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXICMPGDFRM : This field indicates the number of good IP datagrams with a good ICMP payload.
bits : 0 - 30 (31 bit)
access : read-only
RxICMP Error Frames Register
address_offset : 0x244 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXICMPERRFRM : This field indicates the number of good IP datagrams whose ICMP payload has a checksum error.
bits : 0 - 30 (31 bit)
access : read-only
RxIPv4 Good Octets Register
address_offset : 0x250 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV4GDOCT : This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP, UDP, or ICMP data. The Ethernet header, FCS, pad, or IP pad
bits : 0 - 30 (31 bit)
access : read-only
Receive IPV4 Header Error Octet Counter Register
address_offset : 0x254 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV4HDRERROCT : This field indicates the number of bytes received in the IPv4 datagrams with header errors (checksum, length, or version mismatch). The value in the Length field of IPv4 header is used to update this counter.
bits : 0 - 30 (31 bit)
access : read-only
Receive IPV4 No Payload Octet Counter Register
address_offset : 0x258 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV4NOPAYOCT : This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv4 headers Length field is used to update this counter.
bits : 0 - 30 (31 bit)
access : read-only
Receive IPV4 Fragmented Octet Counter Register
address_offset : 0x25C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV4FRAGOCT : This field indicates the number of bytes received in fragmented IPv4 datagrams. The value in the IPv4 headers Length field is used to update this counter.
bits : 0 - 30 (31 bit)
access : read-only
Receive IPV4 Fragmented Octet Counter Register
address_offset : 0x260 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV4UDSBLOCT : This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.
bits : 0 - 30 (31 bit)
access : read-only
RxIPv6 Good Octets Register
address_offset : 0x264 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV6GDOCT : Thsi field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP, UDP or ICMPv6 data.
bits : 0 - 30 (31 bit)
access : read-only
Receive IPV6 Header Error Octet Counter Register
address_offset : 0x268 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV6HDRERROCT : This field indicates the number of bytes received in IPv6 datagrams with header errors (length or version mismatch). The value in the IPv6 headers Length field is used to update this counter.
bits : 0 - 30 (31 bit)
access : read-only
Receive IPV6 No Payload Octet Counter Register
address_offset : 0x26C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXIPV6NOPAYOCT : This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP, UDP, or ICMP payload. The value in the IPv6 headers Length field is used to update this counter.
bits : 0 - 30 (31 bit)
access : read-only
Receive UDP Good Octets Register
address_offset : 0x270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXUDPGDOCT : This field indicates the number of bytes received in a good UDP segment. This counter does not count IP header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.
bits : 0 - 30 (31 bit)
access : read-only
Receive UDP Error Octets Register
address_offset : 0x274 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXUDPERROCT : This field indicates the number of bytes received in a UDP segment with checksum errors. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.
bits : 0 - 30 (31 bit)
access : read-only
Receive TCP Good Octets Register
address_offset : 0x278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXTCPGDOCT : This field indicates the number of bytes received in a good TCP segment. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.
bits : 0 - 30 (31 bit)
access : read-only
Receive TCP Error Octets Register
address_offset : 0x27C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXTCPERROCT : Thsi field indicates the number of bytes received in a TCP segment with checksum errors. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.
bits : 0 - 30 (31 bit)
access : read-only
Remote Wake Up Frame Filter Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WKUPFRMFTR : Remote Wake-Up Frame Filter
bits : 0 - 30 (31 bit)
access : read-write
Receive ICMP Good Octets Register
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXICMPGDOCT : This field indicates the number of bytes received in a good ICMP segment. This counter does not count the IP Header bytes. The Ethernet header, FCS, pad, or IP pad bytes are not included in this counter.
bits : 0 - 30 (31 bit)
access : read-only
Receive ICMP Error Octets Register
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXICMPERROCT : Number of bytes received in an ICMP segment with checksum errors
bits : 0 - 30 (31 bit)
access : read-only
PMT Control and Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PWRDWN : Power Down
bits : 0 - -1 (0 bit)
access : read-write
MGKPKTEN : Magic Packet Enable
bits : 1 - 0 (0 bit)
access : read-write
RWKPKTEN : Wake-Up Frame Enable
bits : 2 - 1 (0 bit)
access : read-write
MGKPRCVD : Magic Packet Received
bits : 5 - 4 (0 bit)
access : read-only
RWKPRCVD : Wake-Up Frame Received
bits : 6 - 5 (0 bit)
access : read-only
GLBLUCAST : Global Unicast
bits : 9 - 8 (0 bit)
access : read-write
RWKFILTRST : Wake-Up Frame Filter Register Pointer Reset
bits : 31 - 30 (0 bit)
access : read-write
Interrupt Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMTIS : PMT Interrupt Status
bits : 3 - 2 (0 bit)
access : read-only
MMCIS : MMC Interrupt Status
bits : 4 - 3 (0 bit)
access : read-only
MMCRXIS : MMC Receive Interrupt Status
bits : 5 - 4 (0 bit)
access : read-only
MMCTXIS : MMC Transmit Interrupt Status
bits : 6 - 5 (0 bit)
access : read-only
MMCRXIPIS : MMC Receive Checksum Offload Interrupt Status
bits : 7 - 6 (0 bit)
access : read-only
TSIS : Timestamp Interrupt Status
bits : 9 - 8 (0 bit)
access : read-only
Interrupt Mask Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PMTIM : PMT Interrupt Mask
bits : 3 - 2 (0 bit)
access : read-write
TSIM : Timestamp Interrupt Mask
bits : 9 - 8 (0 bit)
access : read-write
MAC Frame Filter
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PR : Promiscuous Mode
bits : 0 - -1 (0 bit)
access : read-write
HUC : Hash Unicast
bits : 1 - 0 (0 bit)
access : read-write
HMC : Hash Multicast
bits : 2 - 1 (0 bit)
access : read-write
DAIF : DA Inverse Filtering
bits : 3 - 2 (0 bit)
access : read-write
PM : Pass All Multicast
bits : 4 - 3 (0 bit)
access : read-write
DBF : Disable Broadcast Frames
bits : 5 - 4 (0 bit)
access : read-write
PCF : Pass Control Frames
bits : 6 - 6 (1 bit)
access : read-write
SAIF : SA Inverse Filtering
bits : 8 - 7 (0 bit)
access : read-write
SAF : Source Address Filter Enable
bits : 9 - 8 (0 bit)
access : read-write
HPF : Hash or Perfect Filter
bits : 10 - 9 (0 bit)
access : read-write
VTFE : VLAN Tag Filter Enable
bits : 16 - 15 (0 bit)
access : read-write
IPFE : Layer 3 and Layer 4 Filter Enable
bits : 20 - 19 (0 bit)
access : read-only
DNTU : Drop non-TCP/UDP over IP Frames
bits : 21 - 20 (0 bit)
access : read-only
RA : Receive All
bits : 31 - 30 (0 bit)
access : read-write
MAC Address0 High Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRHI : MAC Address0 [47:32]
bits : 0 - 14 (15 bit)
access : read-write
AE : Address Enable
bits : 31 - 30 (0 bit)
access : read-only
MAC Address0 Low Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRLO : MAC Address0 [31:0]
bits : 0 - 30 (31 bit)
access : read-write
MAC Address1 High Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRHI : MAC Address1 [47:32]
bits : 0 - 14 (15 bit)
access : read-write
MBC : Mask Byte Control
bits : 24 - 28 (5 bit)
access : read-write
SA : Source Address
bits : 30 - 29 (0 bit)
access : read-write
AE : Address Enable
bits : 31 - 30 (0 bit)
access : read-write
MAC Address1 Low Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRLO : MAC Address1 [31:0]
bits : 0 - 30 (31 bit)
access : read-write
MAC Address2 High Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRHI : MAC Address2 [47:32]
bits : 0 - 14 (15 bit)
access : read-write
MBC : Mask Byte Control
bits : 24 - 28 (5 bit)
access : read-write
SA : Source Address
bits : 30 - 29 (0 bit)
access : read-write
AE : Address Enable
bits : 31 - 30 (0 bit)
access : read-write
MAC Address2 Low Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRLO : MAC Address2 [31:0]
bits : 0 - 30 (31 bit)
access : read-write
MAC Address3 High Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRHI : MAC Address3 [47:32]
bits : 0 - 14 (15 bit)
access : read-write
MBC : Mask Byte Control
bits : 24 - 28 (5 bit)
access : read-write
SA : Source Address
bits : 30 - 29 (0 bit)
access : read-write
AE : Address Enable
bits : 31 - 30 (0 bit)
access : read-write
MAC Address3 Low Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRLO : MAC Address3 [31:0]
bits : 0 - 30 (31 bit)
access : read-write
Timestamp Control Register
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSENA : Timestamp Enable
bits : 0 - -1 (0 bit)
access : read-write
TSCFUPDT : Timestamp Fine or Coarse Update
bits : 1 - 0 (0 bit)
access : read-write
TSINIT : Timestamp Initialize
bits : 2 - 1 (0 bit)
access : read-write
TSUPDT : Timestamp Update
bits : 3 - 2 (0 bit)
access : read-write
TSTRIG : Timestamp Interrupt Trigger Enable
bits : 4 - 3 (0 bit)
access : read-write
TSADDREG : Addend Reg Update
bits : 5 - 4 (0 bit)
access : read-write
TSENALL : Enable Timestamp for All Frames
bits : 8 - 7 (0 bit)
access : read-write
TSCTRLSSR : Timestamp Digital or Binary Rollover Control
bits : 9 - 8 (0 bit)
access : read-write
TSVER2ENA : Enable PTP packet Processing for Version 2 Format
bits : 10 - 9 (0 bit)
access : read-write
TSIPENA : Enable Processing of PTP over Ethernet Frames
bits : 11 - 10 (0 bit)
access : read-write
TSIPV6ENA : Enable Processing of PTP Frames Sent Over IPv6-UDP
bits : 12 - 11 (0 bit)
access : read-write
TSIPV4ENA : Enable Processing of PTP Frames Sent over IPv4-UDP
bits : 13 - 12 (0 bit)
access : read-write
TSEVNTENA : Enable Timestamp Snapshot for Event Messages
bits : 14 - 13 (0 bit)
access : read-write
TSMSTRENA : Enable Snapshot for Messages Relevant to Master
bits : 15 - 14 (0 bit)
access : read-write
SNAPTYPSEL : Select PTP packets for Taking Snapshots
bits : 16 - 16 (1 bit)
access : read-write
TSENMACADDR : Enable MAC address for PTP Frame Filtering
bits : 18 - 17 (0 bit)
access : read-write
Sub-Second Increment Register
address_offset : 0x704 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSINC : Sub-second Increment Value
bits : 0 - 6 (7 bit)
access : read-write
System Time - Seconds Register
address_offset : 0x708 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : Timestamp Second
bits : 0 - 30 (31 bit)
access : read-only
System Time Nanoseconds Register
address_offset : 0x70C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSSS : Timestamp Sub Seconds
bits : 0 - 29 (30 bit)
access : read-only
System Time - Seconds Update Register
address_offset : 0x710 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSS : Timestamp Second
bits : 0 - 30 (31 bit)
access : read-write
System Time Nanoseconds Update Register
address_offset : 0x714 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSSS : Timestamp Sub Second
bits : 0 - 29 (30 bit)
access : read-write
ADDSUB : Add or subtract time
bits : 31 - 30 (0 bit)
access : read-write
Timestamp Addend Register
address_offset : 0x718 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSAR : Timestamp Addend Register
bits : 0 - 30 (31 bit)
access : read-write
Target Time Seconds Register
address_offset : 0x71C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSTR : Target Time Seconds Register
bits : 0 - 30 (31 bit)
access : read-write
Target Time Nanoseconds Register
address_offset : 0x720 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TTSLO : Target Timestamp Low Register
bits : 0 - 29 (30 bit)
access : read-write
TRGTBUSY : Target Time Register Busy
bits : 31 - 30 (0 bit)
access : read-only
System Time - Higher Word Seconds Register
address_offset : 0x724 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSHWR : Timestamp Higher Word Register
bits : 0 - 14 (15 bit)
access : read-write
Timestamp Status Register
address_offset : 0x728 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSSOVF : Timestamp Seconds Overflow
bits : 0 - -1 (0 bit)
access : read-only
TSTARGT : Timestamp Target Time Reached
bits : 1 - 0 (0 bit)
access : read-only
TSTRGTERR : Timestamp Target Time Error
bits : 3 - 2 (0 bit)
access : read-only
TSTARGT1 : Timestamp Target Time Reached for Target Time PPS1
bits : 4 - 3 (0 bit)
access : read-only
TSTRGTERR1 : Timestamp Target Time Error
bits : 5 - 4 (0 bit)
access : read-only
TSTARGT2 : Timestamp Target Time Reached for Target Time PPS2
bits : 6 - 5 (0 bit)
access : read-only
TSTRGTERR2 : Timestamp Target Time Error
bits : 7 - 6 (0 bit)
access : read-only
TSTARGT3 : Timestamp Target Time Reached for Target Time PPS3
bits : 8 - 7 (0 bit)
access : read-only
TSTRGTERR3 : Timestamp Target Time Error
bits : 9 - 8 (0 bit)
access : read-only
Hash Table High Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTH : Hash Table High
bits : 0 - 30 (31 bit)
access : read-write
Hash Table Low Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HTL : Hash Table Low
bits : 0 - 30 (31 bit)
access : read-write
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