\n

USB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

HCCHAR

HCTSIZ_BUFFERMODE

HCTSIZ_SCATGATHER

HCDMA_BUFFERMODE

HCDMA_SCATGATHER

HCDMAB

HCINT

HCINTMSK


HCCHAR

Host Channel Characteristics Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCCHAR HCCHAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MPS EPNum EPDir EPType MC_EC DevAddr OddFrm ChDis ChEna

MPS : Maximum Packet Size
bits : 0 - 9 (10 bit)
access : read-write

EPNum : Endpoint Number
bits : 11 - 13 (3 bit)
access : read-write

EPDir : Endpoint Direction
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : value1

OUT

#1 : value2

IN

End of enumeration elements list.

EPType : Endpoint Type
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#00 : value1

Control

#01 : value2

Isochronous

#10 : value3

Bulk

#11 : value4

Interrupt

End of enumeration elements list.

MC_EC : Multi Count / Error Count
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#01 : value2

1 transaction

#10 : value3

2 transactions to be issued for this endpoint per frame

#11 : value4

3 transactions to be issued for this endpoint per frame

End of enumeration elements list.

DevAddr : Device Address
bits : 22 - 27 (6 bit)
access : read-write

OddFrm : Odd Frame
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

#0 : value1

Even frame

#1 : value2

Odd frame

End of enumeration elements list.

ChDis : Channel Disable
bits : 30 - 29 (0 bit)
access : read-write

ChEna : Channel Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

Scatter/Gather mode enabled: Indicates that the descriptor structure is not yet ready. Scatter/Gather mode disabled: Channel disabled

#1 : value2

Scatter/Gather mode enabled: Indicates that the descriptor structure and data buffer with data is setup and this channel can access the descriptor. Scatter/Gather mode disabled: Channel enabled

End of enumeration elements list.


HCTSIZ_BUFFERMODE

Host Channel Transfer Size Register [BUFFERMODE]
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCTSIZ_BUFFERMODE HCTSIZ_BUFFERMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XferSize PktCnt Pid

XferSize : Transfer Size
bits : 0 - 17 (18 bit)
access : read-write

PktCnt : Packet Count
bits : 19 - 27 (9 bit)
access : read-write

Pid : PID
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#00 : value1

DATA0

#01 : value2

DATA2

#10 : value3

DATA1

#11 : value4

MDATA (non-control)/SETUP (control)

End of enumeration elements list.


HCTSIZ_SCATGATHER

Host Channel Transfer Size Register [SCATGATHER]
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : HCTSIZ_BUFFERMODE
reset_Mask : 0x0

HCTSIZ_SCATGATHER HCTSIZ_SCATGATHER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SCHED_INFO NTD Pid

SCHED_INFO : Schedule information
bits : 0 - 6 (7 bit)
access : read-write

NTD : Number of Transfer Descriptors: 0=1 descriptor, 63=64 descriptors, 1=2 descriptors, 3=4 descriptors, 7=8 descriptors, 15=16 descriptors, 31=32 descriptors, 63=64 descriptors,
bits : 8 - 14 (7 bit)
access : read-write

Pid : PID
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#00 : value1

DATA0

#01 : value2

DATA2

#10 : value3

DATA1

#11 : value4

MDATA (non-control)

End of enumeration elements list.


HCDMA_BUFFERMODE

Host Channel DMA Address Register [BUFFERMODE]
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCDMA_BUFFERMODE HCDMA_BUFFERMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMAAddr

DMAAddr : DMA Address
bits : 0 - 30 (31 bit)
access : read-write


HCDMA_SCATGATHER

Host Channel DMA Address Register [SCATGATHER]
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : HCDMA_BUFFERMODE
reset_Mask : 0x0

HCDMA_SCATGATHER HCDMA_SCATGATHER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CTD DMAAddr

CTD : Current Transfer Desc:
bits : 3 - 7 (5 bit)
access : read-write

Enumeration:

0 : value1

1 descriptor

63 : value2

64 descriptors

End of enumeration elements list.

DMAAddr : DMA Address
bits : 9 - 30 (22 bit)
access : read-write


HCDMAB

Host Channel DMA Buffer Address Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCDMAB HCDMAB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Buffer_Address

Buffer_Address : Buffer Address
bits : 0 - 30 (31 bit)
access : read-only


HCINT

Host Channel Interrupt Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINT HCINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XferCompl ChHltd AHBErr STALL NAK ACK NYET XactErr BblErr FrmOvrun DataTglErr BNAIntr XCS_XACT_ERR DESC_LST_ROLLIntr

XferCompl : Transfer Completed
bits : 0 - -1 (0 bit)
access : read-write

ChHltd : Channel Halted
bits : 1 - 0 (0 bit)
access : read-write

AHBErr : AHB Error
bits : 2 - 1 (0 bit)
access : read-write

STALL : STALL Response Received Interrupt
bits : 3 - 2 (0 bit)
access : read-write

NAK : NAK Response Received Interrupt
bits : 4 - 3 (0 bit)
access : read-write

ACK : ACK Response Received/Transmitted Interrupt
bits : 5 - 4 (0 bit)
access : read-write

NYET : NYET Response Received Interrupt
bits : 6 - 5 (0 bit)
access : read-write

XactErr : Transaction Error
bits : 7 - 6 (0 bit)
access : read-write

BblErr : Babble Error
bits : 8 - 7 (0 bit)
access : read-write

FrmOvrun : Frame Overrun
bits : 9 - 8 (0 bit)
access : read-write

DataTglErr : Data Toggle Error
bits : 10 - 9 (0 bit)
access : read-write

BNAIntr : BNA (Buffer Not Available) Interrupt
bits : 11 - 10 (0 bit)
access : read-write

XCS_XACT_ERR : Excessive Transaction Error
bits : 12 - 11 (0 bit)
access : read-write

DESC_LST_ROLLIntr : Descriptor rollover interrupt
bits : 13 - 12 (0 bit)
access : read-write


HCINTMSK

Host Channel Interrupt Mask Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCINTMSK HCINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XferComplMsk ChHltdMsk AHBErrMsk StallMsk NakMsk AckMsk NyetMsk XactErrMsk BblErrMsk FrmOvrunMsk DataTglErrMsk BNAIntrMsk DESC_LST_ROLLIntrMsk

XferComplMsk : Transfer Completed Mask
bits : 0 - -1 (0 bit)
access : read-write

ChHltdMsk : Channel Halted Mask
bits : 1 - 0 (0 bit)
access : read-write

AHBErrMsk : AHB Error Mask
bits : 2 - 1 (0 bit)
access : read-write

StallMsk : STALL Response Received Interrupt Mask
bits : 3 - 2 (0 bit)
access : read-write

NakMsk : NAK Response Received Interrupt Mask
bits : 4 - 3 (0 bit)
access : read-write

AckMsk : ACK Response Received/Transmitted Interrupt Mask
bits : 5 - 4 (0 bit)
access : read-write

NyetMsk : NYET Response Received Interrupt Mask
bits : 6 - 5 (0 bit)
access : read-write

XactErrMsk : Transaction Error Mask
bits : 7 - 6 (0 bit)
access : read-write

BblErrMsk : Babble Error Mask
bits : 8 - 7 (0 bit)
access : read-write

FrmOvrunMsk : Frame Overrun Mask
bits : 9 - 8 (0 bit)
access : read-write

DataTglErrMsk : Data Toggle Error Mask
bits : 10 - 9 (0 bit)
access : read-write

BNAIntrMsk : BNA (Buffer Not Available) Interrupt mask register
bits : 11 - 10 (0 bit)
access : read-write

DESC_LST_ROLLIntrMsk : Descriptor rollover interrupt Mask register
bits : 13 - 12 (0 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.