Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x200 byte (0x0)
mem_usage : registers
protection : not protected
Fractional Divider Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STEP : Step Value
bits : 0 - 8 (9 bit)
access : read-write
DM : Divider Mode
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : value1
The divider is switched off, fFD = 0.
#01 : value2
Normal divider mode selected.
#10 : value3
Fractional divider mode selected.
#11 : value4
The divider is switched off, fFD = 0.
End of enumeration elements list.
RESULT : Result Value
bits : 16 - 24 (9 bit)
access : read-only
Transmit Buffer
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Bypass Data Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BDATA : Bypass Data
bits : 0 - 14 (15 bit)
access : read-write
Bypass Control Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BWLE : Bypass Word Length
bits : 0 - 2 (3 bit)
access : read-write
BDSSM : Bypass Data Single Shot Mode
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
The bypass data is still considered as valid after it has been loaded into TBUF. The loading of the data into TBUF does not clear BDV.
#1 : value2
The bypass data is considered as invalid after it has been loaded into TBUF. The loading of the data into TBUF clears BDV.
End of enumeration elements list.
BDEN : Bypass Data Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
The transfer of bypass data is disabled.
#01 : value2
The transfer of bypass data to TBUF is possible. Bypass data will be transferred to TBUF according to its priority if BDV = 1.
#10 : value3
Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 0.
#11 : value4
Gated bypass data transfer is enabled. Bypass data will be transferred to TBUF according to its priority if BDV = 1 and while DX2S = 1.
End of enumeration elements list.
BDVTR : Bypass Data Valid Trigger
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
Bit BDV is not influenced by DX2T.
#1 : value2
Bit BDV is set if DX2T is active.
End of enumeration elements list.
BPRIO : Bypass Priority
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
The transmit FIFO data has a higher priority than the bypass data.
#1 : value2
The bypass data has a higher priority than the transmit FIFO data.
End of enumeration elements list.
BDV : Bypass Data Valid
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : value1
The bypass data is not valid.
#1 : value2
The bypass data is valid.
End of enumeration elements list.
BSELO : Bypass Select Outputs
bits : 16 - 19 (4 bit)
access : read-write
BHPC : Bypass Hardware Port Control
bits : 21 - 22 (2 bit)
access : read-write
Transmitter Buffer Control Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPTR : Data Pointer
bits : 0 - 4 (5 bit)
access : write-only
LIMIT : Limit For Interrupt Generation
bits : 8 - 12 (5 bit)
access : read-write
STBTM : Standard Transmit Buffer Trigger Mode
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trigger mode 0: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.LIMIT.
#1 : value2
Trigger mode 1: While TRBSR.STBT=1, a standard buffer event will be generated whenever there is a data transfer to TBUF or data write to INx (depending on TBCTR.LOF setting). STBT is cleared when TRBSR.TBFLVL=TBCTR.SIZE.
End of enumeration elements list.
STBTEN : Standard Transmit Buffer Trigger Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
The standard transmit buffer event trigger through bit TRBSR.STBT is disabled.
#1 : value2
The standard transmit buffer event trigger through bit TRBSR.STBT is enabled.
End of enumeration elements list.
STBINP : Standard Transmit Buffer Interrupt Node Pointer
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#000 : value1
Output SR0 becomes activated.
#001 : value2
Output SR1 becomes activated.
#010 : value3
Output SR2 becomes activated.
#011 : value4
Output SR3 becomes activated.
#100 : value5
Output SR4 becomes activated.
#101 : value6
Output SR5 becomes activated.
End of enumeration elements list.
ATBINP : Alternative Transmit Buffer Interrupt Node Pointer
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#000 : value1
Output SR0 becomes activated.
#001 : value2
Output SR1 becomes activated.
#010 : value3
Output SR2 becomes activated.
#011 : value4
Output SR3 becomes activated.
#100 : value5
Output SR4 becomes activated.
#101 : value6
Output SR5 becomes activated.
End of enumeration elements list.
SIZE : Buffer Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#000 : value1
The FIFO mechanism is disabled. The buffer does not accept any request for data.
#001 : value2
The FIFO buffer contains 2 entries.
#010 : value3
The FIFO buffer contains 4 entries.
#011 : value4
The FIFO buffer contains 8 entries.
#100 : value5
The FIFO buffer contains 16 entries.
#101 : value6
The FIFO buffer contains 32 entries.
#110 : value7
The FIFO buffer contains 64 entries.
End of enumeration elements list.
LOF : Buffer Event on Limit Overflow
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : value1
A standard transmit buffer event occurs when the filling level equals the limit value and gets lower due to transmission of a data word.
#1 : value2
A standard transmit buffer interrupt event occurs when the filling level equals the limit value and gets bigger due to a write access to a data input location INx.
End of enumeration elements list.
STBIEN : Standard Transmit Buffer Interrupt Enable
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : value1
The standard transmit buffer interrupt generation is disabled.
#1 : value2
The standard transmit buffer interrupt generation is enabled.
End of enumeration elements list.
TBERIEN : Transmit Buffer Error Interrupt Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : value1
The transmit buffer error interrupt generation is disabled.
#1 : value2
The transmit buffer error interrupt generation is enabled.
End of enumeration elements list.
Receiver Buffer Control Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DPTR : Data Pointer
bits : 0 - 4 (5 bit)
access : write-only
LIMIT : Limit For Interrupt Generation
bits : 8 - 12 (5 bit)
access : read-write
SRBTM : Standard Receive Buffer Trigger Mode
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trigger mode 0: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=RBCTR.LIMIT.
#1 : value2
Trigger mode 1: While TRBSR.SRBT=1, a standard receive buffer event will be generated whenever there is a new data received or data read out (depending on RBCTR.LOF setting). SRBT is cleared when TRBSR.RBFLVL=0.
End of enumeration elements list.
SRBTEN : Standard Receive Buffer Trigger Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
The standard receive buffer event trigger through bit TRBSR.SRBT is disabled.
#1 : value2
The standard receive buffer event trigger through bit TRBSR.SRBT is enabled.
End of enumeration elements list.
SRBINP : Standard Receive Buffer Interrupt Node Pointer
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#000 : value1
Output SR0 becomes activated.
#001 : value2
Output SR1 becomes activated.
#010 : value3
Output SR2 becomes activated.
#011 : value4
Output SR3 becomes activated.
#100 : value5
Output SR4 becomes activated.
#101 : value6
Output SR5 becomes activated.
End of enumeration elements list.
ARBINP : Alternative Receive Buffer Interrupt Node Pointer
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#000 : value1
Output SR0 becomes activated.
#001 : value2
Output SR1 becomes activated.
#010 : value3
Output SR2 becomes activated.
#011 : value4
Output SR3 becomes activated.
#100 : value5
Output SR4 becomes activated.
#101 : value6
Output SR5 becomes activated.
End of enumeration elements list.
RCIM : Receiver Control Information Mode
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#00 : value1
RCI[4] = PERR, RCI[3:0] = WLEN
#01 : value2
RCI[4] = SOF, RCI[3:0] = WLEN
#10 : value3
RCI[4] = 0, RCI[3:0] = WLEN
#11 : value4
RCI[4] = PERR, RCI[3] = PAR, RCI[2:1] = 00B, RCI[0] = SOF
End of enumeration elements list.
SIZE : Buffer Size
bits : 24 - 25 (2 bit)
access : read-write
Enumeration:
#000 : value1
The FIFO mechanism is disabled. The buffer does not accept any request for data.
#001 : value2
The FIFO buffer contains 2 entries.
#010 : value3
The FIFO buffer contains 4 entries.
#011 : value4
The FIFO buffer contains 8 entries.
#100 : value5
The FIFO buffer contains 16 entries.
#101 : value6
The FIFO buffer contains 32 entries.
#110 : value7
The FIFO buffer contains 64 entries.
End of enumeration elements list.
RNM : Receiver Notification Mode
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : value1
Filling level mode: A standard receive buffer event occurs when the filling level equals the limit value and changes, either due to a read access from OUTR (LOF = 0) or due to a new received data word (LOF = 1).
#1 : value2
RCI mode: A standard receive buffer event occurs when register OUTR is updated with a new value if the corresponding value in OUTR.RCI[4] = 0. If OUTR.RCI[4] = 1, an alternative receive buffer event occurs instead of the standard receive buffer event.
End of enumeration elements list.
LOF : Buffer Event on Limit Overflow
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : value1
A standard receive buffer event occurs when the filling level equals the limit value and gets lower due to a read access from OUTR.
#1 : value2
A standard receive buffer event occurs when the filling level equals the limit value and gets bigger due to the reception of a new data word.
End of enumeration elements list.
ARBIEN : Alternative Receive Buffer Interrupt Enable
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : value1
The alternative receive buffer interrupt generation is disabled.
#1 : value2
The alternative receive buffer interrupt generation is enabled.
End of enumeration elements list.
SRBIEN : Standard Receive Buffer Interrupt Enable
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : value1
The standard receive buffer interrupt generation is disabled.
#1 : value2
The standard receive buffer interrupt generation is enabled.
End of enumeration elements list.
RBERIEN : Receive Buffer Error Interrupt Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : value1
The receive buffer error interrupt generation is disabled.
#1 : value2
The receive buffer error interrupt generation is enabled.
End of enumeration elements list.
Transmit Buffer
address_offset : 0x10D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit/Receive Buffer Pointer Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDIPTR : Transmitter Data Input Pointer
bits : 0 - 4 (5 bit)
access : read-only
TDOPTR : Transmitter Data Output Pointer
bits : 8 - 12 (5 bit)
access : read-only
RDIPTR : Receiver Data Input Pointer
bits : 16 - 20 (5 bit)
access : read-only
RDOPTR : Receiver Data Output Pointer
bits : 24 - 28 (5 bit)
access : read-only
Transmit FIFO Buffer
address_offset : 0x1134 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit/Receive Buffer Status Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SRBI : Standard Receive Buffer Event
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
A standard receive buffer event has not been detected.
#1 : value2
A standard receive buffer event has been detected.
End of enumeration elements list.
RBERI : Receive Buffer Error Event
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
A receive buffer error event has not been detected.
#1 : value2
A receive buffer error event has been detected.
End of enumeration elements list.
ARBI : Alternative Receive Buffer Event
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
An alternative receive buffer event has not been detected.
#1 : value2
An alternative receive buffer event has been detected.
End of enumeration elements list.
REMPTY : Receive Buffer Empty
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
The receive buffer is not empty.
#1 : value2
The receive buffer is empty.
End of enumeration elements list.
RFULL : Receive Buffer Full
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
The receive buffer is not full.
#1 : value2
The receive buffer is full.
End of enumeration elements list.
RBUS : Receive Buffer Busy
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : value1
The receive buffer information has been completely updated.
#1 : value2
The OUTR update from the FIFO memory is ongoing. A read from OUTR will be delayed. FIFO pointers from the previous read are not yet updated.
End of enumeration elements list.
SRBT : Standard Receive Buffer Event Trigger
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : value1
A standard receive buffer event is not triggered using this bit.
#1 : value2
A standard receive buffer event is triggered using this bit.
End of enumeration elements list.
STBI : Standard Transmit Buffer Event
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
A standard transmit buffer event has not been detected.
#1 : value2
A standard transmit buffer event has been detected.
End of enumeration elements list.
TBERI : Transmit Buffer Error Event
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : value1
A transmit buffer error event has not been detected.
#1 : value2
A transmit buffer error event has been detected.
End of enumeration elements list.
TEMPTY : Transmit Buffer Empty
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
#0 : value1
The transmit buffer is not empty.
#1 : value2
The transmit buffer is empty.
End of enumeration elements list.
TFULL : Transmit Buffer Full
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : value1
The transmit buffer is not full.
#1 : value2
The transmit buffer is full.
End of enumeration elements list.
TBUS : Transmit Buffer Busy
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : value1
The transmit buffer information has been completely updated.
#1 : value2
The FIFO memory update after write to INx is ongoing. A write to INx will be delayed. FIFO pointers from the previous INx write are not yet updated.
End of enumeration elements list.
STBT : Standard Transmit Buffer Event Trigger
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : value1
A standard transmit buffer event is not triggered using this bit.
#1 : value2
A standard transmit buffer event is triggered using this bit.
End of enumeration elements list.
RBFLVL : Receive Buffer Filling Level
bits : 16 - 21 (6 bit)
access : read-only
TBFLVL : Transmit Buffer Filling Level
bits : 24 - 29 (6 bit)
access : read-only
Transmit/Receive Buffer Status Clear Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSRBI : Clear Standard Receive Buffer Event
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Clear TRBSR.SRBI.
End of enumeration elements list.
CRBERI : Clear Receive Buffer Error Event
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Clear TRBSR.RBERI.
End of enumeration elements list.
CARBI : Clear Alternative Receive Buffer Event
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Clear TRBSR.ARBI.
End of enumeration elements list.
CSTBI : Clear Standard Transmit Buffer Event
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Clear TRBSR.STBI.
End of enumeration elements list.
CTBERI : Clear Transmit Buffer Error Event
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Clear TRBSR.TBERI.
End of enumeration elements list.
CBDV : Clear Bypass Data Valid
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
Clear BYPCR.BDV.
End of enumeration elements list.
FLUSHRB : Flush Receive Buffer
bits : 14 - 13 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
The receive FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic.
End of enumeration elements list.
FLUSHTB : Flush Transmit Buffer
bits : 15 - 14 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect.
#1 : value2
The transmit FIFO buffer is cleared (filling level is cleared and output pointer is set to input pointer value). Should only be used while the FIFO buffer is not taking part in data traffic.
End of enumeration elements list.
Transmit Buffer
address_offset : 0x11B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Receiver Buffer Output Register
address_offset : 0x11C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSR : Received Data
bits : 0 - 14 (15 bit)
access : read-only
RCI : Receiver Control Information
bits : 16 - 19 (4 bit)
access : read-only
Receiver Buffer Output Register L for Debugger
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSR : Data from Shift Register
bits : 0 - 14 (15 bit)
access : read-only
RCI : Receive Control Information from Shift Register
bits : 16 - 19 (4 bit)
access : read-only
Transmit Buffer
address_offset : 0x1294 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0x12DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0x137C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Baud Rate Generator Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKSEL : Clock Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
The fractional divider frequency fFD is selected.
#10 : value3
The trigger signal DX1T defines fPIN. Signal MCLK toggles with fPIN.
#11 : value4
Signal MCLK corresponds to the DX1S signal and the frequency fPIN is derived from the rising edges of DX1S.
End of enumeration elements list.
TMEN : Timing Measurement Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Timing measurement is disabled: The trigger signals DX0T and DX1T are ignored.
#1 : value2
Timing measurement is enabled: The 10-bit counter is incremented by 1 with fPPP and stops counting when reaching its maximum value. If one of the trigger signals DX0T or DX1T become active, the counter value is captured into bit field CTV, the counter is cleared and a transmit shift event is generated.
End of enumeration elements list.
PPPEN : Enable 2:1 Divider for fPPP
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
The 2:1 divider for fPPP is disabled. fPPP = fPIN
#1 : value2
The 2:1 divider for fPPP is enabled. fPPP = fMCLK = fPIN / 2.
End of enumeration elements list.
CTQSEL : Input Selection for CTQ
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : value1
fCTQIN = fPDIV
#01 : value2
fCTQIN = fPPP
#10 : value3
fCTQIN = fSCLK
#11 : value4
fCTQIN = fMCLK
End of enumeration elements list.
PCTQ : Pre-Divider for Time Quanta Counter
bits : 8 - 8 (1 bit)
access : read-write
DCTQ : Denominator for Time Quanta Counter
bits : 10 - 13 (4 bit)
access : read-write
PDIV : Divider Mode: Divider Factor to Generate fPDIV
bits : 16 - 24 (9 bit)
access : read-write
SCLKOSEL : Shift Clock Output Select
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : value1
SCLK from the baud rate generator is selected as the SCLKOUT input source.
#1 : value2
The transmit shift clock from DX1 input stage is selected as the SCLKOUT input source.
End of enumeration elements list.
MCLKCFG : Master Clock Configuration
bits : 29 - 28 (0 bit)
access : read-write
Enumeration:
#0 : value1
The passive level is 0.
#1 : value2
The passive level is 1.
End of enumeration elements list.
SCLKCFG : Shift Clock Output Configuration
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#00 : value1
The passive level is 0 and the delay is disabled.
#01 : value2
The passive level is 1 and the delay is disabled.
#10 : value3
The passive level is 0 and the delay is enabled.
#11 : value4
The passive level is 1 and the delay is enabled.
End of enumeration elements list.
Transmit Buffer
address_offset : 0x1468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0x1488 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0x1558 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0x1638 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0x164C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit Buffer
address_offset : 0x1744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0x17EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Interrupt Node Pointer Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSINP : Transmit Shift Interrupt Node Pointer
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
Output SR0 becomes activated.
#001 : value2
Output SR1 becomes activated.
#010 : value3
Output SR2 becomes activated.
#011 : value4
Output SR3 becomes activated.
#100 : value5
Output SR4 becomes activated.
#101 : value6
Output SR5 becomes activated.
End of enumeration elements list.
TBINP : Transmit Buffer Interrupt Node Pointer
bits : 4 - 5 (2 bit)
access : read-write
RINP : Receive Interrupt Node Pointer
bits : 8 - 9 (2 bit)
access : read-write
AINP : Alternative Receive Interrupt Node Pointer
bits : 12 - 13 (2 bit)
access : read-write
PINP : Transmit Shift Interrupt Node Pointer
bits : 16 - 17 (2 bit)
access : read-write
Transmit Buffer
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit Buffer
address_offset : 0x1840 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0x19A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit FIFO Buffer
address_offset : 0x1B60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Input Control Register 0
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSEL : Data Selection for Input Signal
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
The data input DXnA is selected.
#001 : value2
The data input DXnB is selected.
#010 : value3
The data input DXnC is selected.
#011 : value4
The data input DXnD is selected.
#100 : value5
The data input DXnE is selected.
#101 : value6
The data input DXnF is selected.
#110 : value7
The data input DXnG is selected.
#111 : value8
The data input is always 1.
End of enumeration elements list.
INSW : Input Switch
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input of the data shift unit is controlled by the protocol pre-processor.
#1 : value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
End of enumeration elements list.
DFEN : Digital Filter Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input signal is not digitally filtered.
#1 : value2
The input signal is digitally filtered.
End of enumeration elements list.
DSEN : Data Synchronization Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
The un-synchronized signal can be taken as input for the data shift unit.
#1 : value2
The synchronized signal can be taken as input for the data shift unit.
End of enumeration elements list.
DPOL : Data Polarity for DXn
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input signal is not inverted.
#1 : value2
The input signal is inverted.
End of enumeration elements list.
SFSEL : Sampling Frequency Selection
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : value1
The sampling frequency is fPB.
#1 : value2
The sampling frequency is fFD.
End of enumeration elements list.
CM : Combination Mode
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
The trigger activation is disabled.
#01 : value2
A rising edge activates DXnT.
#10 : value3
A falling edge activates DXnT.
#11 : value4
Both edges activate DXnT.
End of enumeration elements list.
DXS : Synchronized Data Value
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : value1
The current value of DXnS is 0.
#1 : value2
The current value of DXnS is 1.
End of enumeration elements list.
Transmit FIFO Buffer
address_offset : 0x1D20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit FIFO Buffer
address_offset : 0x1EE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Input Control Register 1
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSEL : Data Selection for Input Signal
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
The data input DX1A is selected.
#001 : value2
The data input DX1B is selected.
#010 : value3
The data input DX1C is selected.
#011 : value4
The data input DX1D is selected.
#100 : value5
The data input DX1E is selected.
#101 : value6
The data input DX1F is selected.
#110 : value7
The data input DX1G is selected.
#111 : value8
The data input is always 1.
End of enumeration elements list.
DCEN : Delay Compensation Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
The receive shift clock is dependent on INSW selection.
#1 : value2
The receive shift clock is connected to the selected data input line. This setting is used if delay compensation is required in SSC and IIS protocols, else DCEN should always be 0.
End of enumeration elements list.
INSW : Input Switch
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input of the data shift unit is controlled by the protocol pre-processor.
#1 : value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
End of enumeration elements list.
DFEN : Digital Filter Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input signal is not digitally filtered.
#1 : value2
The input signal is digitally filtered.
End of enumeration elements list.
DSEN : Data Synchronization Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
The un-synchronized signal can be taken as input for the data shift unit.
#1 : value2
The synchronized signal can be taken as input for the data shift unit.
End of enumeration elements list.
DPOL : Data Polarity for DXn
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input signal is not inverted.
#1 : value2
The input signal is inverted.
End of enumeration elements list.
SFSEL : Sampling Frequency Selection
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : value1
The sampling frequency is fPB.
#1 : value2
The sampling frequency is fFD.
End of enumeration elements list.
CM : Combination Mode
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
The trigger activation is disabled.
#01 : value2
A rising edge activates DX1T.
#10 : value3
A falling edge activates DX1T.
#11 : value4
Both edges activate DX1T.
End of enumeration elements list.
DXS : Synchronized Data Value
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : value1
The current value of DX1S is 0.
#1 : value2
The current value of DX1S is 1.
End of enumeration elements list.
Transmit FIFO Buffer
address_offset : 0x20AC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0x2278 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Input Control Register 2
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSEL : Data Selection for Input Signal
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
The data input DXnA is selected.
#001 : value2
The data input DXnB is selected.
#010 : value3
The data input DXnC is selected.
#011 : value4
The data input DXnD is selected.
#100 : value5
The data input DXnE is selected.
#101 : value6
The data input DXnF is selected.
#110 : value7
The data input DXnG is selected.
#111 : value8
The data input is always 1.
End of enumeration elements list.
INSW : Input Switch
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input of the data shift unit is controlled by the protocol pre-processor.
#1 : value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
End of enumeration elements list.
DFEN : Digital Filter Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input signal is not digitally filtered.
#1 : value2
The input signal is digitally filtered.
End of enumeration elements list.
DSEN : Data Synchronization Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
The un-synchronized signal can be taken as input for the data shift unit.
#1 : value2
The synchronized signal can be taken as input for the data shift unit.
End of enumeration elements list.
DPOL : Data Polarity for DXn
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input signal is not inverted.
#1 : value2
The input signal is inverted.
End of enumeration elements list.
SFSEL : Sampling Frequency Selection
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : value1
The sampling frequency is fPB.
#1 : value2
The sampling frequency is fFD.
End of enumeration elements list.
CM : Combination Mode
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
The trigger activation is disabled.
#01 : value2
A rising edge activates DXnT.
#10 : value3
A falling edge activates DXnT.
#11 : value4
Both edges activate DXnT.
End of enumeration elements list.
DXS : Synchronized Data Value
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : value1
The current value of DXnS is 0.
#1 : value2
The current value of DXnS is 1.
End of enumeration elements list.
Transmit FIFO Buffer
address_offset : 0x2448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit FIFO Buffer
address_offset : 0x261C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit FIFO Buffer
address_offset : 0x27F4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Input Control Register 3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSEL : Data Selection for Input Signal
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
The data input DXnA is selected.
#001 : value2
The data input DXnB is selected.
#010 : value3
The data input DXnC is selected.
#011 : value4
The data input DXnD is selected.
#100 : value5
The data input DXnE is selected.
#101 : value6
The data input DXnF is selected.
#110 : value7
The data input DXnG is selected.
#111 : value8
The data input is always 1.
End of enumeration elements list.
INSW : Input Switch
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input of the data shift unit is controlled by the protocol pre-processor.
#1 : value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
End of enumeration elements list.
DFEN : Digital Filter Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input signal is not digitally filtered.
#1 : value2
The input signal is digitally filtered.
End of enumeration elements list.
DSEN : Data Synchronization Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
The un-synchronized signal can be taken as input for the data shift unit.
#1 : value2
The synchronized signal can be taken as input for the data shift unit.
End of enumeration elements list.
DPOL : Data Polarity for DXn
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input signal is not inverted.
#1 : value2
The input signal is inverted.
End of enumeration elements list.
SFSEL : Sampling Frequency Selection
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : value1
The sampling frequency is fPB.
#1 : value2
The sampling frequency is fFD.
End of enumeration elements list.
CM : Combination Mode
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
The trigger activation is disabled.
#01 : value2
A rising edge activates DXnT.
#10 : value3
A falling edge activates DXnT.
#11 : value4
Both edges activate DXnT.
End of enumeration elements list.
DXS : Synchronized Data Value
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : value1
The current value of DXnS is 0.
#1 : value2
The current value of DXnS is 1.
End of enumeration elements list.
Transmit Buffer
address_offset : 0x298 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0x29D0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit FIFO Buffer
address_offset : 0x2BB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Input Control Register 4
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSEL : Data Selection for Input Signal
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
The data input DXnA is selected.
#001 : value2
The data input DXnB is selected.
#010 : value3
The data input DXnC is selected.
#011 : value4
The data input DXnD is selected.
#100 : value5
The data input DXnE is selected.
#101 : value6
The data input DXnF is selected.
#110 : value7
The data input DXnG is selected.
#111 : value8
The data input is always 1.
End of enumeration elements list.
INSW : Input Switch
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input of the data shift unit is controlled by the protocol pre-processor.
#1 : value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
End of enumeration elements list.
DFEN : Digital Filter Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input signal is not digitally filtered.
#1 : value2
The input signal is digitally filtered.
End of enumeration elements list.
DSEN : Data Synchronization Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
The un-synchronized signal can be taken as input for the data shift unit.
#1 : value2
The synchronized signal can be taken as input for the data shift unit.
End of enumeration elements list.
DPOL : Data Polarity for DXn
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input signal is not inverted.
#1 : value2
The input signal is inverted.
End of enumeration elements list.
SFSEL : Sampling Frequency Selection
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : value1
The sampling frequency is fPB.
#1 : value2
The sampling frequency is fFD.
End of enumeration elements list.
CM : Combination Mode
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
The trigger activation is disabled.
#01 : value2
A rising edge activates DXnT.
#10 : value3
A falling edge activates DXnT.
#11 : value4
Both edges activate DXnT.
End of enumeration elements list.
DXS : Synchronized Data Value
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : value1
The current value of DXnS is 0.
#1 : value2
The current value of DXnS is 1.
End of enumeration elements list.
Transmit FIFO Buffer
address_offset : 0x2D94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit FIFO Buffer
address_offset : 0x2F7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Input Control Register 5
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSEL : Data Selection for Input Signal
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
The data input DXnA is selected.
#001 : value2
The data input DXnB is selected.
#010 : value3
The data input DXnC is selected.
#011 : value4
The data input DXnD is selected.
#100 : value5
The data input DXnE is selected.
#101 : value6
The data input DXnF is selected.
#110 : value7
The data input DXnG is selected.
#111 : value8
The data input is always 1.
End of enumeration elements list.
INSW : Input Switch
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input of the data shift unit is controlled by the protocol pre-processor.
#1 : value2
The input of the data shift unit is connected to the selected data input line. This setting is used if the signals are directly derived from an input pin without treatment by the protocol pre-processor.
End of enumeration elements list.
DFEN : Digital Filter Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input signal is not digitally filtered.
#1 : value2
The input signal is digitally filtered.
End of enumeration elements list.
DSEN : Data Synchronization Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
The un-synchronized signal can be taken as input for the data shift unit.
#1 : value2
The synchronized signal can be taken as input for the data shift unit.
End of enumeration elements list.
DPOL : Data Polarity for DXn
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
The input signal is not inverted.
#1 : value2
The input signal is inverted.
End of enumeration elements list.
SFSEL : Sampling Frequency Selection
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : value1
The sampling frequency is fPB.
#1 : value2
The sampling frequency is fFD.
End of enumeration elements list.
CM : Combination Mode
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
The trigger activation is disabled.
#01 : value2
A rising edge activates DXnT.
#10 : value3
A falling edge activates DXnT.
#11 : value4
Both edges activate DXnT.
End of enumeration elements list.
DXS : Synchronized Data Value
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : value1
The current value of DXnS is 0.
#1 : value2
The current value of DXnS is 1.
End of enumeration elements list.
Transmit FIFO Buffer
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit FIFO Buffer
address_offset : 0x3168 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0x328 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0x3358 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Shift Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDIR : Shift Direction
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Shift LSB first. The first data bit of a data word is located at bit position 0.
#1 : value2
Shift MSB first. The first data bit of a data word is located at the bit position given by bit field SCTR.WLE.
End of enumeration elements list.
PDL : Passive Data Level
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
The passive data level is 0.
#1 : value2
The passive data level is 1.
End of enumeration elements list.
DSM : Data Shift Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#00 : value1
Receive and transmit data is shifted in and out one bit at a time through DX0 and DOUT0.
#10 : value3
Receive and transmit data is shifted in and out two bits at a time through two input stages (DX0 and DX3) and DOUT[1:0] respectively.
#11 : value4
Receive and transmit data is shifted in and out four bits at a time through four input stages (DX0, DX[5:3]) and DOUT[3:0] respectively.
End of enumeration elements list.
HPCDIR : Port Control Direction
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
The pin(s) with hardware pin control enabled are selected to be in input mode.
#1 : value2
The pin(s) with hardware pin control enabled are selected to be in output mode.
End of enumeration elements list.
DOCFG : Data Output Configuration
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : value1
DOUTx = shift data value
#01 : value2
DOUTx = inverted shift data value
End of enumeration elements list.
TRM : Transmission Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
The shift control signal is considered as inactive and data frame transfers are not possible.
#01 : value2
The shift control signal is considered active if it is at 1-level. This is the setting to be programmed to allow data transfers.
#10 : value3
The shift control signal is considered active if it is at 0-level. It is recommended to avoid this setting and to use the inversion in the DX2 stage in case of a low-active signal.
#11 : value4
The shift control signal is considered active without referring to the actual signal level. Data frame transfer is possible after each edge of the signal.
End of enumeration elements list.
FLE : Frame Length
bits : 16 - 20 (5 bit)
access : read-write
WLE : Word Length
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
0x0 : value1
The data word contains 1 data bit located at bit position 0.
0x1 : value2
The data word contains 2 data bits located at bit positions [1:0].
0xE : value3
The data word contains 15 data bits located at bit positions [14:0].
0xF : value4
The data word contains 16 data bits located at bit positions [15:0].
End of enumeration elements list.
Transmit FIFO Buffer
address_offset : 0x354C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit FIFO Buffer
address_offset : 0x3744 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Control/Status Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLEMD : WLE Mode
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The automatic update of SCTR.WLE and TCSR.EOF is disabled.
#1 : value2
The automatic update of SCTR.WLE and TCSR.EOF is enabled.
End of enumeration elements list.
SELMD : Select Mode
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
The automatic update of PCR.CTR[23:16] is disabled.
#1 : value2
The automatic update of PCR.CTR[23:16] is disabled.
End of enumeration elements list.
FLEMD : FLE Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The automatic update of FLE is disabled.
#1 : value2
The automatic update of FLE is enabled.
End of enumeration elements list.
WAMD : WA Mode
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
The automatic update of bit WA is disabled.
#1 : value2
The automatic update of bit WA is enabled.
End of enumeration elements list.
HPCMD : Hardware Port Control Mode
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
The automatic update of bits SCTR.DSM and SCTR.HPCDIR is disabled.
#1 : value2
The automatic update of bits SCTR.DSM and SCTR.HPCDIR is enabled.
End of enumeration elements list.
SOF : Start Of Frame
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
The data word in TBUF is not considered as first word of a frame.
#1 : value2
The data word in TBUF is considered as first word of a frame. A currently running frame is finished and MSLS becomes deactivated (respecting the programmed delays).
End of enumeration elements list.
EOF : End Of Frame
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
The data word in TBUF is not considered as last word of an SSC frame.
#1 : value2
The data word in TBUF is considered as last word of an SSC frame.
End of enumeration elements list.
TDV : Transmit Data Valid
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : value1
The data word in TBUF is not valid for transmission.
#1 : value2
The data word in TBUF is valid for transmission and a transmission start is possible. New data should not be written to a TBUFx input location while TDV = 1.
End of enumeration elements list.
TDSSM : TBUF Data Single Shot Mode
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
The data word in TBUF is not considered as invalid after it has been loaded into the transmit shift register. The loading of the TBUF data into the shift register does not clear TDV.
#1 : value2
The data word in TBUF is considered as invalid after it has been loaded into the shift register. In ASC and IIC mode, TDV is cleared with the TBI event, whereas in SSC and IIS mode, it is cleared with the RSI event. TDSSM = 1 has to be programmed if an optional data buffer is used.
End of enumeration elements list.
TDEN : TBUF Data Enable
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
A transmission start of the data word in TBUF is disabled. If a transmission is started, the passive data level is sent out.
#01 : value2
A transmission of the data word in TBUF can be started if TDV = 1.
#10 : value3
A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 0.
#11 : value4
A transmission of the data word in TBUF can be started if TDV = 1 while DX2S = 1.
End of enumeration elements list.
TDVTR : TBUF Data Valid Trigger
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
Bit TCSR.TE is permanently set.
#1 : value2
Bit TCSR.TE is set if DX2T becomes active while TDV = 1.
End of enumeration elements list.
WA : Word Address
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
The data word in TBUF will be transmitted after a falling edge of WA has been detected (referring to PSR.WA).
#1 : value2
The data word in TBUF will be transmitted after a rising edge of WA has been detected (referring to PSR.WA).
End of enumeration elements list.
TSOF : Transmitted Start Of Frame
bits : 24 - 23 (0 bit)
access : read-only
Enumeration:
#0 : value1
The latest data word transmission has not been started for the first word of a data frame.
#1 : value2
The latest data word transmission has been started for the first word of a data frame.
End of enumeration elements list.
TV : Transmission Valid
bits : 26 - 25 (0 bit)
access : read-only
Enumeration:
#0 : value1
The latest start of a data word transmission has taken place while no valid data was available. As a result, the transmission of a data words with passive level (SCTR.PDL) has been started.
#1 : value2
The latest start of a data word transmission has taken place with valid data from TBUF.
End of enumeration elements list.
TVC : Transmission Valid Cumulated
bits : 27 - 26 (0 bit)
access : read-only
Enumeration:
#0 : value1
Since TVC has been set, at least one data buffer underflow condition has occurred.
#1 : value2
Since TVC has been set, no data buffer underflow condition has occurred.
End of enumeration elements list.
TE : Trigger Event
bits : 28 - 27 (0 bit)
access : read-only
Enumeration:
#0 : value1
The trigger event has not yet been detected. A transmission of the data word in TBUF can not be started.
#1 : value2
The trigger event has been detected (or the trigger mechanism is switched off) and a transmission of the data word in TBUF can not be started.
End of enumeration elements list.
Transmit FIFO Buffer
address_offset : 0x3940 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0x3BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Protocol Control Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTR0 : Protocol Control Bit 0
bits : 0 - -1 (0 bit)
access : read-write
CTR1 : Protocol Control Bit 1
bits : 1 - 0 (0 bit)
access : read-write
CTR2 : Protocol Control Bit 2
bits : 2 - 1 (0 bit)
access : read-write
CTR3 : Protocol Control Bit 3
bits : 3 - 2 (0 bit)
access : read-write
CTR4 : Protocol Control Bit 4
bits : 4 - 3 (0 bit)
access : read-write
CTR5 : Protocol Control Bit 5
bits : 5 - 4 (0 bit)
access : read-write
CTR6 : Protocol Control Bit 6
bits : 6 - 5 (0 bit)
access : read-write
CTR7 : Protocol Control Bit 7
bits : 7 - 6 (0 bit)
access : read-write
CTR8 : Protocol Control Bit 8
bits : 8 - 7 (0 bit)
access : read-write
CTR9 : Protocol Control Bit 9
bits : 9 - 8 (0 bit)
access : read-write
CTR10 : Protocol Control Bit 10
bits : 10 - 9 (0 bit)
access : read-write
CTR11 : Protocol Control Bit 11
bits : 11 - 10 (0 bit)
access : read-write
CTR12 : Protocol Control Bit 12
bits : 12 - 11 (0 bit)
access : read-write
CTR13 : Protocol Control Bit 13
bits : 13 - 12 (0 bit)
access : read-write
CTR14 : Protocol Control Bit 14
bits : 14 - 13 (0 bit)
access : read-write
CTR15 : Protocol Control Bit 15
bits : 15 - 14 (0 bit)
access : read-write
CTR16 : Protocol Control Bit 16
bits : 16 - 15 (0 bit)
access : read-write
CTR17 : Protocol Control Bit 17
bits : 17 - 16 (0 bit)
access : read-write
CTR18 : Protocol Control Bit 18
bits : 18 - 17 (0 bit)
access : read-write
CTR19 : Protocol Control Bit 19
bits : 19 - 18 (0 bit)
access : read-write
CTR20 : Protocol Control Bit 20
bits : 20 - 19 (0 bit)
access : read-write
CTR21 : Protocol Control Bit 21
bits : 21 - 20 (0 bit)
access : read-write
CTR22 : Protocol Control Bit 22
bits : 22 - 21 (0 bit)
access : read-write
CTR23 : Protocol Control Bit 23
bits : 23 - 22 (0 bit)
access : read-write
CTR24 : Protocol Control Bit 24
bits : 24 - 23 (0 bit)
access : read-write
CTR25 : Protocol Control Bit 25
bits : 25 - 24 (0 bit)
access : read-write
CTR26 : Protocol Control Bit 26
bits : 26 - 25 (0 bit)
access : read-write
CTR27 : Protocol Control Bit 27
bits : 27 - 26 (0 bit)
access : read-write
CTR28 : Protocol Control Bit 28
bits : 28 - 27 (0 bit)
access : read-write
CTR29 : Protocol Control Bit 29
bits : 29 - 28 (0 bit)
access : read-write
CTR30 : Protocol Control Bit 30
bits : 30 - 29 (0 bit)
access : read-write
CTR31 : Protocol Control Bit 31
bits : 31 - 30 (0 bit)
access : read-write
Protocol Control Register [ASC Mode]
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PCR
reset_Mask : 0x0
SMD : Sample Mode
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Only one sample is taken per bit time. The current input value is sampled.
#1 : value2
Three samples are taken per bit time and a majority decision is made.
End of enumeration elements list.
STPB : Stop Bits
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
The number of stop bits is 1.
#1 : value2
The number of stop bits is 2.
End of enumeration elements list.
IDM : Idle Detection Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The bus idle detection is switched off and bits PSR.TXIDLE and PSR.RXIDLE are set automatically to enable data transfers without checking the inputs before.
#1 : value2
The bus is considered as idle after a number of consecutive passive bit times defined by SCTR.FLE plus 2 (in the case without parity bit) or plus 3 (in the case with parity bit).
End of enumeration elements list.
SBIEN : Synchronization Break Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
The interrupt generation is disabled.
#1 : value2
The interrupt generation is enabled.
End of enumeration elements list.
CDEN : Collision Detection Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
The collision detection is disabled.
#1 : value2
If a collision is detected, the transmitter stops its data transmission, outputs a 1, sets bit PSR.COL and generates a protocol interrupt. In order to allow data transmission again, PSR.COL has to be cleared by software.
End of enumeration elements list.
RNIEN : Receiver Noise Detection Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
The interrupt generation is disabled.
#1 : value2
The interrupt generation is enabled.
End of enumeration elements list.
FEIEN : Format Error Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
The interrupt generation is disabled.
#1 : value2
The interrupt generation is enabled.
End of enumeration elements list.
FFIEN : Frame Finished Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
The interrupt generation is disabled.
#1 : value2
The interrupt generation is enabled.
End of enumeration elements list.
SP : Sample Point
bits : 8 - 11 (4 bit)
access : read-write
PL : Pulse Length
bits : 13 - 14 (2 bit)
access : read-write
Enumeration:
#000 : value1
The pulse length is equal to the bit length (no shortened 0).
#001 : value2
The pulse length of a 0 bit is 2 time quanta.
#010 : value3
The pulse length of a 0 bit is 3 time quanta.
#111 : value4
The pulse length of a 0 bit is 8 time quanta.
End of enumeration elements list.
RSTEN : Receiver Status Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag PSR[9] is not modified depending on the receiver status.
#1 : value2
Flag PSR[9] is set during the complete reception of a frame.
End of enumeration elements list.
TSTEN : Transmitter Status Enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag PSR[9] is not modified depending on the transmitter status.
#1 : value2
Flag PSR[9] is set during the complete transmission of a frame.
End of enumeration elements list.
MCLK : Master Clock Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : value1
The MCLK generation is disabled and the MCLK signal is 0.
#1 : value2
The MCLK generation is enabled.
End of enumeration elements list.
Protocol Control Register [SSC Mode]
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PCR
reset_Mask : 0x0
MSLSEN : MSLS Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The MSLS generation is disabled (MSLS = 0). This is the setting for SSC slave mode.
#1 : value2
The MSLS generation is enabled. This is the setting for SSC master mode.
End of enumeration elements list.
SELCTR : Select Control
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
The coded select mode is enabled.
#1 : value2
The direct select mode is enabled.
End of enumeration elements list.
SELINV : Select Inversion
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The SELO outputs have the same polarity as the MSLS signal (active high).
#1 : value2
The SELO outputs have the inverted polarity to the MSLS signal (active low).
End of enumeration elements list.
FEM : Frame End Mode
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
The current data frame is considered as finished when the last bit of a data word has been sent out and the transmit buffer TBUF does not contain new data (TDV = 0).
#1 : value2
The MSLS signal is kept active also while no new data is available and no other end of frame condition is reached. In this case, the software can accept delays in delivering the data without automatic deactivation of MSLS in multi-word data frames.
End of enumeration elements list.
CTQSEL1 : Input Frequency Selection
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
fCTQIN = fPDIV
#01 : value2
fCTQIN = fPPP
#10 : value3
fCTQIN = fSCLK
#11 : value4
fCTQIN = fMCLK
End of enumeration elements list.
PCTQ1 : Divider Factor PCTQ1 for Tiw and Tnf
bits : 6 - 6 (1 bit)
access : read-write
DCTQ1 : Divider Factor DCTQ1 for Tiw and Tnf
bits : 8 - 11 (4 bit)
access : read-write
PARIEN : Parity Error Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
A protocol interrupt is not generated with the detection of a parity error.
#1 : value2
A protocol interrupt is generated with the detection of a parity error.
End of enumeration elements list.
MSLSIEN : MSLS Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
A protocol interrupt is not generated if a change of signal MSLS is detected.
#1 : value2
A protocol interrupt is generated if a change of signal MSLS is detected.
End of enumeration elements list.
DX2TIEN : DX2T Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
A protocol interrupt is not generated if DX2T is activated.
#1 : value2
A protocol interrupt is generated if DX2T is activated.
End of enumeration elements list.
SELO : Select Output
bits : 16 - 22 (7 bit)
access : read-write
Enumeration:
#0 : value1
The corresponding SELOx line cannot be activated.
#1 : value2
The corresponding SELOx line can be activated (according to the mode selected by SELCTR).
End of enumeration elements list.
TIWEN : Enable Inter-Word Delay Tiw
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : value1
No delay between data words of the same frame.
#1 : value2
The inter-word delay Tiw is enabled and introduced between data words of the same frame.
End of enumeration elements list.
SLPHSEL : Slave Mode Clock Phase Select
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Data bits are shifted out with the leading edge of the shift clock signal and latched in with the trailing edge.
0b1 : value2
The first data bit is shifted out when the data shift unit receives a low to high transition from the DX2 stage. Subsequent bits are shifted out with the trailing edge of the shift clock signal. Data bits are always latched in with the leading edge.
End of enumeration elements list.
MCLK : Master Clock Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : value1
The MCLK generation is disabled and output MCLK = 0.
#1 : value2
The MCLK generation is enabled.
End of enumeration elements list.
Protocol Control Register [IIC Mode]
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PCR
reset_Mask : 0x0
SLAD : Slave Address
bits : 0 - 14 (15 bit)
access : read-write
ACK00 : Acknowledge 00H
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
The slave device is not sensitive to this address.
#1 : value2
The slave device is sensitive to this address.
End of enumeration elements list.
STIM : Symbol Timing
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
A symbol contains 10 time quanta. The timing is adapted for standard mode (100 kBaud).
#1 : value2
A symbol contains 25 time quanta. The timing is adapted for fast mode (400 kBaud).
End of enumeration elements list.
SCRIEN : Start Condition Received Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
The start condition interrupt is disabled.
#1 : value2
The start condition interrupt is enabled.
End of enumeration elements list.
RSCRIEN : Repeated Start Condition Received Interrupt Enable
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
The repeated start condition interrupt is disabled.
#1 : value2
The repeated start condition interrupt is enabled.
End of enumeration elements list.
PCRIEN : Stop Condition Received Interrupt Enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : value1
The stop condition interrupt is disabled.
#1 : value2
The stop condition interrupt is enabled.
End of enumeration elements list.
NACKIEN : Non-Acknowledge Interrupt Enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : value1
The non-acknowledge interrupt is disabled.
#1 : value2
The non-acknowledge interrupt is enabled.
End of enumeration elements list.
ARLIEN : Arbitration Lost Interrupt Enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : value1
The arbitration lost interrupt is disabled.
#1 : value2
The arbitration lost interrupt is enabled.
End of enumeration elements list.
SRRIEN : Slave Read Request Interrupt Enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : value1
The slave read request interrupt is disabled.
#1 : value2
The slave read request interrupt is enabled.
End of enumeration elements list.
ERRIEN : Error Interrupt Enable
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
#0 : value1
The error interrupt is disabled.
#1 : value2
The error interrupt is enabled.
End of enumeration elements list.
SACKDIS : Slave Acknowledge Disable
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : value1
The generation of an active slave acknowledge is enabled (slave acknowledge with 0 level = more bytes can be received).
#1 : value2
The generation of an active slave acknowledge is disabled (slave acknowledge with 1 level = reception stopped).
End of enumeration elements list.
HDEL : Hardware Delay
bits : 26 - 28 (3 bit)
access : read-write
ACKIEN : Acknowledge Interrupt Enable
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
#0 : value1
The acknowledge interrupt is disabled.
#1 : value2
The acknowledge interrupt is enabled.
End of enumeration elements list.
MCLK : Master Clock Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : value1
The MCLK generation is disabled and MCLK is 0.
#1 : value2
The MCLK generation is enabled.
End of enumeration elements list.
Protocol Control Register [IIS Mode]
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PCR
reset_Mask : 0x0
WAGEN : WA Generation Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The IIS can be used as slave. The generation of the word address signal is disabled. The output signal WA is 0. The MCLKO signal generation depends on PCR.MCLK.
#1 : value2
The IIS can be used as master. The generation of the word address signal is enabled. The signal starts with a 0 after being enabled. The generation of MCLK is enabled, independent of PCR.MCLK. After clearing WAGEN, the USIC module stops the generation of the WA signal within the next 4 WA periods.
End of enumeration elements list.
DTEN : Data Transfers Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
The changes of the WA input signal are ignored and no transfers take place.
#1 : value2
Transfers are enabled.
End of enumeration elements list.
SELINV : Select Inversion
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The SELOx outputs have the same polarity as the WA signal.
#1 : value2
The SELOx outputs have the inverted polarity to the WA signal.
End of enumeration elements list.
WAFEIEN : WA Falling Edge Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
A protocol interrupt is not activated if a falling edge of WA is generated.
#1 : value2
A protocol interrupt is activated if a falling edge of WA is generated.
End of enumeration elements list.
WAREIEN : WA Rising Edge Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
A protocol interrupt is not activated if a rising edge of WA is generated.
#1 : value2
A protocol interrupt is activated if a rising edge of WA is generated.
End of enumeration elements list.
ENDIEN : END Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
A protocol interrupt is not activated.
#1 : value2
A protocol interrupt is activated.
End of enumeration elements list.
DX2TIEN : DX2T Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
A protocol interrupt is not generated if DX2T is active.
#1 : value2
A protocol interrupt is generated if DX2T is active.
End of enumeration elements list.
TDEL : Transfer Delay
bits : 16 - 20 (5 bit)
access : read-write
MCLK : Master Clock Enable
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : value1
The MCLK generation is disabled and MCLK is 0.
#1 : value2
The MCLK generation is enabled.
End of enumeration elements list.
Channel Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSC : SSC Protocol Available
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
The SSC protocol is not available.
#1 : value2
The SSC protocol is available.
End of enumeration elements list.
ASC : ASC Protocol Available
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
The ASC protocol is not available.
#1 : value2
The ASC protocol is available.
End of enumeration elements list.
IIC : IIC Protocol Available
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
The IIC protocol is not available.
#1 : value2
The IIC protocol is available.
End of enumeration elements list.
IIS : IIS Protocol Available
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
The IIS protocol is not available.
#1 : value2
The IIS protocol is available.
End of enumeration elements list.
RB : Receive FIFO Buffer Available
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : value1
A receive FIFO buffer is not available.
#1 : value2
A receive FIFO buffer is available.
End of enumeration elements list.
TB : Transmit FIFO Buffer Available
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
#0 : value1
A transmit FIFO buffer is not available.
#1 : value2
A transmit FIFO buffer is available.
End of enumeration elements list.
Channel Control Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Operating Mode
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0x0 : value1
The USIC channel is disabled. All protocol-related state machines are set to an idle state.
0x1 : value2
The SSC (SPI) protocol is selected.
0x2 : value3
The ASC (SCI, UART) protocol is selected.
0x3 : value4
The IIS protocol is selected.
0x4 : value5
The IIC protocol is selected.
End of enumeration elements list.
HPCEN : Hardware Port Control Enable
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : value1
The hardware port control is disabled.
#01 : value2
The hardware port control is enabled for DX0 and DOUT0.
#10 : value3
The hardware port control is enabled for DX3, DX0 and DOUT[1:0].
#11 : value4
The hardware port control is enabled for DX0, DX[5:3] and DOUT[3:0].
End of enumeration elements list.
PM : Parity Mode
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
The parity generation is disabled.
#10 : value3
Even parity is selected (parity bit = 1 on odd number of 1s in data, parity bit = 0 on even number of 1s in data).
#11 : value4
Odd parity is selected (parity bit = 0 on odd number of 1s in data, parity bit = 1 on even number of 1s in data).
End of enumeration elements list.
RSIEN : Receiver Start Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
The receiver start interrupt is disabled.
#1 : value2
The receiver start interrupt is enabled. In case of a receiver start event, the service request output SRx indicated by INPR.TBINP is activated.
End of enumeration elements list.
DLIEN : Data Lost Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : value1
The data lost interrupt is disabled.
#1 : value2
The data lost interrupt is enabled. In case of a data lost event, the service request output SRx indicated by INPR.PINP is activated.
End of enumeration elements list.
TSIEN : Transmit Shift Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
The transmit shift interrupt is disabled.
#1 : value2
The transmit shift interrupt is enabled. In case of a transmit shift interrupt event, the service request output SRx indicated by INPR.TSINP is activated.
End of enumeration elements list.
TBIEN : Transmit Buffer Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
The transmit buffer interrupt is disabled.
#1 : value2
The transmit buffer interrupt is enabled. In case of a transmit buffer event, the service request output SRx indicated by INPR.TBINP is activated.
End of enumeration elements list.
RIEN : Receive Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
The receive interrupt is disabled.
#1 : value2
The receive interrupt is enabled. In case of a receive event, the service request output SRx indicated by INPR.RINP is activated.
End of enumeration elements list.
AIEN : Alternative Receive Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
The alternative receive interrupt is disabled.
#1 : value2
The alternative receive interrupt is enabled. In case of an alternative receive event, the service request output SRx indicated by INPR.AINP is activated.
End of enumeration elements list.
BRGIEN : Baud Rate Generator Interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
The baud rate generator interrupt is disabled.
#1 : value2
The baud rate generator interrupt is enabled. In case of a baud rate generator event, the service request output SRx indicated by INPR.PINP is activated.
End of enumeration elements list.
Capture Mode Timer Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTV : Captured Timer Value
bits : 0 - 8 (9 bit)
access : read-write
Transmit Buffer
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Protocol Status Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ST0 : Protocol Status Flag 0
bits : 0 - -1 (0 bit)
access : read-write
ST1 : Protocol Status Flag 1
bits : 1 - 0 (0 bit)
access : read-write
ST2 : Protocol Status Flag 2
bits : 2 - 1 (0 bit)
access : read-write
ST3 : Protocol Status Flag 3
bits : 3 - 2 (0 bit)
access : read-write
ST4 : Protocol Status Flag 4
bits : 4 - 3 (0 bit)
access : read-write
ST5 : Protocol Status Flag 5
bits : 5 - 4 (0 bit)
access : read-write
ST6 : Protocol Status Flag 6
bits : 6 - 5 (0 bit)
access : read-write
ST7 : Protocol Status Flag 7
bits : 7 - 6 (0 bit)
access : read-write
ST8 : Protocol Status Flag 8
bits : 8 - 7 (0 bit)
access : read-write
ST9 : Protocol Status Flag 9
bits : 9 - 8 (0 bit)
access : read-write
RSIF : Receiver Start Indication Flag
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
A receiver start event has not occurred.
#1 : value2
A receiver start event has occurred.
End of enumeration elements list.
DLIF : Data Lost Indication Flag
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : value1
A data lost event has not occurred.
#1 : value2
A data lost event has occurred.
End of enumeration elements list.
TSIF : Transmit Shift Indication Flag
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
A transmit shift event has not occurred.
#1 : value2
A transmit shift event has occurred.
End of enumeration elements list.
TBIF : Transmit Buffer Indication Flag
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
A transmit buffer event has not occurred.
#1 : value2
A transmit buffer event has occurred.
End of enumeration elements list.
RIF : Receive Indication Flag
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
A receive event has not occurred.
#1 : value2
A receive event has occurred.
End of enumeration elements list.
AIF : Alternative Receive Indication Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
An alternative receive event has not occurred.
#1 : value2
An alternative receive event has occurred.
End of enumeration elements list.
BRGIF : Baud Rate Generator Indication Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
A baud rate generator event has not occurred.
#1 : value2
A baud rate generator event has occurred.
End of enumeration elements list.
Protocol Status Register [ASC Mode]
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PSR
reset_Mask : 0x0
TXIDLE : Transmission Idle
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The transmitter line has not yet been idle.
#1 : value2
The transmitter line has been idle and frame transmission is possible.
End of enumeration elements list.
RXIDLE : Reception Idle
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
The receiver line has not yet been idle.
#1 : value2
The receiver line has been idle and frame reception is possible.
End of enumeration elements list.
SBD : Synchronization Break Detected
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
A synchronization break has not yet been detected.
#1 : value2
A synchronization break has been detected.
End of enumeration elements list.
COL : Collision Detected
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
A collision has not yet been detected and frame transmission is possible.
#1 : value2
A collision has been detected and frame transmission is not possible.
End of enumeration elements list.
RNS : Receiver Noise Detected
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Receiver noise has not been detected.
#1 : value2
Receiver noise has been detected.
End of enumeration elements list.
FER0 : Format Error in Stop Bit 0
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
A format error 0 has not been detected.
#1 : value2
A format error 0 has been detected.
End of enumeration elements list.
FER1 : Format Error in Stop Bit 1
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
A format error 1 has not been detected.
#1 : value2
A format error 1 has been detected.
End of enumeration elements list.
RFF : Receive Frame Finished
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
The received frame is not yet finished.
#1 : value2
The received frame is finished.
End of enumeration elements list.
TFF : Transmitter Frame Finished
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
The transmitter frame is not yet finished.
#1 : value2
The transmitter frame is finished.
End of enumeration elements list.
BUSY : Transfer Status BUSY
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : value1
A data transfer does not take place.
#1 : value2
A data transfer currently takes place.
End of enumeration elements list.
RSIF : Receiver Start Indication Flag
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
A receiver start event has not occurred.
#1 : value2
A receiver start event has occurred.
End of enumeration elements list.
DLIF : Data Lost Indication Flag
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : value1
A data lost event has not occurred.
#1 : value2
A data lost event has occurred.
End of enumeration elements list.
TSIF : Transmit Shift Indication Flag
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
A transmit shift event has not occurred.
#1 : value2
A transmit shift event has occurred.
End of enumeration elements list.
TBIF : Transmit Buffer Indication Flag
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
A transmit buffer event has not occurred.
#1 : value2
A transmit buffer event has occurred.
End of enumeration elements list.
RIF : Receive Indication Flag
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
A receive event has not occurred.
#1 : value2
A receive event has occurred.
End of enumeration elements list.
AIF : Alternative Receive Indication Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
An alternative receive event has not occurred.
#1 : value2
An alternative receive event has occurred.
End of enumeration elements list.
BRGIF : Baud Rate Generator Indication Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
A baud rate generator event has not occurred.
#1 : value2
A baud rate generator event has occurred.
End of enumeration elements list.
Protocol Status Register [SSC Mode]
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PSR
reset_Mask : 0x0
MSLS : MSLS Status
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The internal signal MSLS is inactive (0).
#1 : value2
The internal signal MSLS is active (1).
End of enumeration elements list.
DX2S : DX2S Status
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
DX2S is 0.
#1 : value2
DX2S is 1.
End of enumeration elements list.
MSLSEV : MSLS Event Detected
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The MSLS signal has not changed its state.
#1 : value2
The MSLS signal has changed its state.
End of enumeration elements list.
DX2TEV : DX2T Event Detected
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
The DX2T signal has not been activated.
#1 : value2
The DX2T signal has been activated.
End of enumeration elements list.
PARERR : Parity Error Event Detected
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
A parity error event has not been activated.
#1 : value2
A parity error event has been activated.
End of enumeration elements list.
RSIF : Receiver Start Indication Flag
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
A receiver start event has not occurred.
#1 : value2
A receiver start event has occurred.
End of enumeration elements list.
DLIF : Data Lost Indication Flag
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : value1
A data lost event has not occurred.
#1 : value2
A data lost event has occurred.
End of enumeration elements list.
TSIF : Transmit Shift Indication Flag
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
A transmit shift event has not occurred.
#1 : value2
A transmit shift event has occurred.
End of enumeration elements list.
TBIF : Transmit Buffer Indication Flag
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
A transmit buffer event has not occurred.
#1 : value2
A transmit buffer event has occurred.
End of enumeration elements list.
RIF : Receive Indication Flag
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
A receive event has not occurred.
#1 : value2
A receive event has occurred.
End of enumeration elements list.
AIF : Alternative Receive Indication Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
An alternative receive event has not occurred.
#1 : value2
An alternative receive event has occurred.
End of enumeration elements list.
BRGIF : Baud Rate Generator Indication Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
A baud rate generator event has not occurred.
#1 : value2
A baud rate generator event has occurred.
End of enumeration elements list.
Protocol Status Register [IIC Mode]
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PSR
reset_Mask : 0x0
SLSEL : Slave Select
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The device is not selected as slave.
#1 : value2
The device is selected as slave.
End of enumeration elements list.
WTDF : Wrong TDF Code Found
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
A wrong TDF code has not been found.
#1 : value2
A wrong TDF code has been found.
End of enumeration elements list.
SCR : Start Condition Received
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
A start condition has not yet been detected.
#1 : value2
A start condition has been detected.
End of enumeration elements list.
RSCR : Repeated Start Condition Received
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
A repeated start condition has not yet been detected.
#1 : value2
A repeated start condition has been detected.
End of enumeration elements list.
PCR : Stop Condition Received
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
A stop condition has not yet been detected.
#1 : value2
A stop condition has been detected.
End of enumeration elements list.
NACK : Non-Acknowledge Received
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
A non-acknowledge has not been received.
#1 : value2
A non-acknowledge has been received.
End of enumeration elements list.
ARL : Arbitration Lost
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
An arbitration has not been lost.
#1 : value2
An arbitration has been lost.
End of enumeration elements list.
SRR : Slave Read Request
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
A slave read request has not been detected.
#1 : value2
A slave read request has been detected.
End of enumeration elements list.
ERR : Error
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
An IIC error has not been detected.
#1 : value2
An IIC error has been detected.
End of enumeration elements list.
ACK : Acknowledge Received
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : value1
An acknowledge has not been received.
#1 : value2
An acknowledge has been received.
End of enumeration elements list.
RSIF : Receiver Start Indication Flag
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
A receiver start event has not occurred.
#1 : value2
A receiver start event has occurred.
End of enumeration elements list.
DLIF : Data Lost Indication Flag
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : value1
A data lost event has not occurred.
#1 : value2
A data lost event has occurred.
End of enumeration elements list.
TSIF : Transmit Shift Indication Flag
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
A transmit shift event has not occurred.
#1 : value2
A transmit shift event has occurred.
End of enumeration elements list.
TBIF : Transmit Buffer Indication Flag
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
A transmit buffer event has not occurred.
#1 : value2
A transmit buffer event has occurred.
End of enumeration elements list.
RIF : Receive Indication Flag
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
A receive event has not occurred.
#1 : value2
A receive event has occurred.
End of enumeration elements list.
AIF : Alternative Receive Indication Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
An alternative receive event has not occurred.
#1 : value2
An alternative receive event has occurred.
End of enumeration elements list.
BRGIF : Baud Rate Generator Indication Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
A baud rate generator event has not occurred.
#1 : value2
A baud rate generator event has occurred.
End of enumeration elements list.
Protocol Status Register [IIS Mode]
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : PSR
reset_Mask : 0x0
WA : Word Address
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
WA has been sampled 0.
#1 : value2
WA has been sampled 1.
End of enumeration elements list.
DX2S : DX2S Status
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
DX2S is 0.
#1 : value2
DX2S is 1.
End of enumeration elements list.
DX2TEV : DX2T Event Detected
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
The DX2T signal has not been activated.
#1 : value2
The DX2T signal has been activated.
End of enumeration elements list.
WAFE : WA Falling Edge Event
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
A WA falling edge has not been generated.
#1 : value2
A WA falling edge has been generated.
End of enumeration elements list.
WARE : WA Rising Edge Event
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
A WA rising edge has not been generated.
#1 : value2
A WA rising edge has been generated.
End of enumeration elements list.
END : WA Generation End
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
The WA generation has not yet ended (if it is running and WAGEN has been cleared).
#1 : value2
The WA generation has ended (if it has been running).
End of enumeration elements list.
RSIF : Receiver Start Indication Flag
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
A receiver start event has not occurred.
#1 : value2
A receiver start event has occurred.
End of enumeration elements list.
DLIF : Data Lost Indication Flag
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : value1
A data lost event has not occurred.
#1 : value2
A data lost event has occurred.
End of enumeration elements list.
TSIF : Transmit Shift Indication Flag
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
A transmit shift event has not occurred.
#1 : value2
A transmit shift event has occurred.
End of enumeration elements list.
TBIF : Transmit Buffer Indication Flag
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
A transmit buffer event has not occurred.
#1 : value2
A transmit buffer event has occurred.
End of enumeration elements list.
RIF : Receive Indication Flag
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
A receive event has not occurred.
#1 : value2
A receive event has occurred.
End of enumeration elements list.
AIF : Alternative Receive Indication Flag
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
An alternative receive event has not occurred.
#1 : value2
An alternative receive event has occurred.
End of enumeration elements list.
BRGIF : Baud Rate Generator Indication Flag
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
A baud rate generator event has not occurred.
#1 : value2
A baud rate generator event has occurred.
End of enumeration elements list.
Transmit FIFO Buffer
address_offset : 0x484 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Protocol Status Clear Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CST0 : Clear Status Flag 0 in PSR
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.STx is cleared.
End of enumeration elements list.
CST1 : Clear Status Flag 1 in PSR
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.STx is cleared.
End of enumeration elements list.
CST2 : Clear Status Flag 2 in PSR
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.STx is cleared.
End of enumeration elements list.
CST3 : Clear Status Flag 3 in PSR
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.STx is cleared.
End of enumeration elements list.
CST4 : Clear Status Flag 4 in PSR
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.STx is cleared.
End of enumeration elements list.
CST5 : Clear Status Flag 5 in PSR
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.STx is cleared.
End of enumeration elements list.
CST6 : Clear Status Flag 6 in PSR
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.STx is cleared.
End of enumeration elements list.
CST7 : Clear Status Flag 7 in PSR
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.STx is cleared.
End of enumeration elements list.
CST8 : Clear Status Flag 8 in PSR
bits : 8 - 7 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.STx is cleared.
End of enumeration elements list.
CST9 : Clear Status Flag 9 in PSR
bits : 9 - 8 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.STx is cleared.
End of enumeration elements list.
CRSIF : Clear Receiver Start Indication Flag
bits : 10 - 9 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.RSIF is cleared.
End of enumeration elements list.
CDLIF : Clear Data Lost Indication Flag
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.DLIF is cleared.
End of enumeration elements list.
CTSIF : Clear Transmit Shift Indication Flag
bits : 12 - 11 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.TSIF is cleared.
End of enumeration elements list.
CTBIF : Clear Transmit Buffer Indication Flag
bits : 13 - 12 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.TBIF is cleared.
End of enumeration elements list.
CRIF : Clear Receive Indication Flag
bits : 14 - 13 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.RIF is cleared.
End of enumeration elements list.
CAIF : Clear Alternative Receive Indication Flag
bits : 15 - 14 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.AIF is cleared.
End of enumeration elements list.
CBRGIF : Clear Baud Rate Generator Indication Flag
bits : 16 - 15 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action
#1 : value2
Flag PSR.BRGIF is cleared.
End of enumeration elements list.
Transmit Buffer
address_offset : 0x4F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Receiver Buffer Status Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLEN : Received Data Word Length in RBUF or RBUFD
bits : 0 - 2 (3 bit)
access : read-only
SOF : Start of Frame in RBUF or RBUFD
bits : 6 - 5 (0 bit)
access : read-only
PAR : Protocol-Related Argument in RBUF or RBUFD
bits : 8 - 7 (0 bit)
access : read-only
PERR : Protocol-related Error in RBUF or RBUFD
bits : 9 - 8 (0 bit)
access : read-only
RDV0 : Receive Data Valid in RBUF or RBUFD
bits : 13 - 12 (0 bit)
access : read-only
RDV1 : Receive Data Valid in RBUF or RBUFD
bits : 14 - 13 (0 bit)
access : read-only
DS : Data Source of RBUF or RBUFD
bits : 15 - 14 (0 bit)
access : read-only
Receiver Buffer Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSR : Received Data
bits : 0 - 14 (15 bit)
access : read-only
Receiver Buffer Register for Debugger
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSR : Data from Shift Register
bits : 0 - 14 (15 bit)
access : read-only
Transmit Buffer
address_offset : 0x590 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Receiver Buffer Register 0
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSR0 : Data of Shift Registers 0[3:0]
bits : 0 - 14 (15 bit)
access : read-only
Receiver Buffer Register 1
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DSR1 : Data of Shift Registers 1[3:0]
bits : 0 - 14 (15 bit)
access : read-only
Transmit FIFO Buffer
address_offset : 0x60C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0x634 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Receiver Buffer 01 Status Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WLEN0 : Received Data Word Length in RBUF0
bits : 0 - 2 (3 bit)
access : read-only
SOF0 : Start of Frame in RBUF0
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : value1
The data in RBUF0 has not been the first data word of a data frame.
#1 : value2
The data in RBUF0 has been the first data word of a data frame.
End of enumeration elements list.
PAR0 : Protocol-Related Argument in RBUF0
bits : 8 - 7 (0 bit)
access : read-only
PERR0 : Protocol-related Error in RBUF0
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : value1
The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt.
#1 : value2
The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt.
End of enumeration elements list.
RDV00 : Receive Data Valid in RBUF0
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : value1
Register RBUF0 does not contain data that has not yet been read out.
#1 : value2
Register RBUF0 contains data that has not yet been read out.
End of enumeration elements list.
RDV01 : Receive Data Valid in RBUF1
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
#0 : value1
Register RBUF1 does not contain data that has not yet been read out.
#1 : value2
Register RBUF1 contains data that has not yet been read out.
End of enumeration elements list.
DS0 : Data Source
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
#0 : value1
The register RBUF contains the data of RBUF0 (same for associated status information).
#1 : value2
The register RBUF contains the data of RBUF1 (same for associated status information).
End of enumeration elements list.
WLEN1 : Received Data Word Length in RBUF1
bits : 16 - 18 (3 bit)
access : read-only
Enumeration:
0x0 : value1
One bit has been received.
0xF : value2
Sixteen bits have been received.
End of enumeration elements list.
SOF1 : Start of Frame in RBUF1
bits : 22 - 21 (0 bit)
access : read-only
Enumeration:
#0 : value1
The data in RBUF1 has not been the first data word of a data frame.
#1 : value2
The data in RBUF1 has been the first data word of a data frame.
End of enumeration elements list.
PAR1 : Protocol-Related Argument in RBUF1
bits : 24 - 23 (0 bit)
access : read-only
PERR1 : Protocol-related Error in RBUF1
bits : 25 - 24 (0 bit)
access : read-only
Enumeration:
#0 : value1
The received protocol-related argument PAR matches the expected value. The reception of the data word sets bit PSR.RIF and can generate a receive interrupt.
#1 : value2
The received protocol-related argument PAR does not match the expected value. The reception of the data word sets bit PSR.AIF and can generate an alternative receive interrupt.
End of enumeration elements list.
RDV10 : Receive Data Valid in RBUF0
bits : 29 - 28 (0 bit)
access : read-only
Enumeration:
#0 : value1
Register RBUF0 does not contain data that has not yet been read out.
#1 : value2
Register RBUF0 contains data that has not yet been read out.
End of enumeration elements list.
RDV11 : Receive Data Valid in RBUF1
bits : 30 - 29 (0 bit)
access : read-only
Enumeration:
#0 : value1
Register RBUF1 does not contain data that has not yet been read out.
#1 : value2
Register RBUF1 contains data that has not yet been read out.
End of enumeration elements list.
DS1 : Data Source
bits : 31 - 30 (0 bit)
access : read-only
Enumeration:
#0 : value1
The register RBUF contains the data of RBUF0 (same for associated status information).
#1 : value2
The register RBUF contains the data of RBUF1 (same for associated status information).
End of enumeration elements list.
Flag Modification Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MTDV : Modify Transmit Data Valid
bits : 0 - 0 (1 bit)
access : write-only
Enumeration:
#00 : value1
No action.
#01 : value2
Bit TDV is set, TE is unchanged.
#10 : value3
Bits TDV and TE are cleared.
End of enumeration elements list.
ATVC : Activate Bit TVC
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action.
#1 : value2
Bit TCSR.TVC is set.
End of enumeration elements list.
CRDV0 : Clear Bits RDV for RBUF0
bits : 14 - 13 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action.
#1 : value2
Bits RBUF01SR.RDV00 and RBUF01SR.RDV10 are cleared.
End of enumeration elements list.
CRDV1 : Clear Bit RDV for RBUF1
bits : 15 - 14 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action.
#1 : value2
Bits RBUF01SR.RDV01 and RBUF01SR.RDV11 are cleared.
End of enumeration elements list.
SIO0 : Set Interrupt Output SRx
bits : 16 - 15 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action.
#1 : value2
The service request output SRx is activated.
End of enumeration elements list.
SIO1 : Set Interrupt Output SRx
bits : 17 - 16 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action.
#1 : value2
The service request output SRx is activated.
End of enumeration elements list.
SIO2 : Set Interrupt Output SRx
bits : 18 - 17 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action.
#1 : value2
The service request output SRx is activated.
End of enumeration elements list.
SIO3 : Set Interrupt Output SRx
bits : 19 - 18 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action.
#1 : value2
The service request output SRx is activated.
End of enumeration elements list.
SIO4 : Set Interrupt Output SRx
bits : 20 - 19 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action.
#1 : value2
The service request output SRx is activated.
End of enumeration elements list.
SIO5 : Set Interrupt Output SRx
bits : 21 - 20 (0 bit)
access : write-only
Enumeration:
#0 : value1
No action.
#1 : value2
The service request output SRx is activated.
End of enumeration elements list.
Transmit Buffer
address_offset : 0x6DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit Buffer
address_offset : 0x788 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0x798 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0x838 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit Buffer
address_offset : 0x8EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0x928 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0x9A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit Buffer
address_offset : 0xA60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0xABC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0xB20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit Buffer
address_offset : 0xBE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Kernel State Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODEN : Module Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The module is switched off immediately (without respecting a stop condition). It does not react on mode control actions and the module clock is switched off. The module does not react on read accesses and ignores write accesses (except to KSCFG).
#1 : value2
The module is switched on and can operate. After writing 1 to MODEN, it is recommended to read register KSCFG to avoid pipeline effects in the control block before accessing other Service Request Processing registers.
End of enumeration elements list.
BPMODEN : Bit Protection for MODEN
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
MODEN is not changed.
#1 : value2
MODEN is updated with the written value.
End of enumeration elements list.
NOMCFG : Normal Operation Mode Configuration
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
Run mode 0 is selected.
#01 : value2
Run mode 1 is selected.
#10 : value3
Stop mode 0 is selected.
#11 : value4
Stop mode 1 is selected.
End of enumeration elements list.
BPNOM : Bit Protection for NOMCFG
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
#0 : value1
NOMCFG is not changed.
#1 : value2
NOMCFG is updated with the written value.
End of enumeration elements list.
SUMCFG : Suspend Mode Configuration
bits : 8 - 8 (1 bit)
access : read-write
BPSUM : Bit Protection for SUMCFG
bits : 11 - 10 (0 bit)
access : write-only
Enumeration:
#0 : value1
SUMCFG is not changed.
#1 : value2
SUMCFG is updated with the written value.
End of enumeration elements list.
Transmit FIFO Buffer
address_offset : 0xC54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0xCAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit Buffer
address_offset : 0xD78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0xDF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0xE48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit Buffer
address_offset : 0xF1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
Transmit FIFO Buffer
address_offset : 0xF90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : write-only
Transmit Buffer
address_offset : 0xFF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TDATA : Transmit Data
bits : 0 - 14 (15 bit)
access : read-write
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