\n

DLR

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

OVRSTAT

LNEN

OVRCLR

SRSEL0


OVRSTAT

Overrun Status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OVRSTAT OVRSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LN0 LN1 LN2 LN3 LN4 LN5 LN6 LN7

LN0 : Line 0 Overrun Status
bits : 0 - -1 (0 bit)
access : read-only

LN1 : Line 1 Overrun Status
bits : 1 - 0 (0 bit)
access : read-only

LN2 : Line 2 Overrun Status
bits : 2 - 1 (0 bit)
access : read-only

LN3 : Line 3 Overrun Status
bits : 3 - 2 (0 bit)
access : read-only

LN4 : Line 4 Overrun Status
bits : 4 - 3 (0 bit)
access : read-only

LN5 : Line 5 Overrun Status
bits : 5 - 4 (0 bit)
access : read-only

LN6 : Line 6 Overrun Status
bits : 6 - 5 (0 bit)
access : read-only

LN7 : Line 7 Overrun Status
bits : 7 - 6 (0 bit)
access : read-only


LNEN

Line Enable
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LNEN LNEN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LN0 LN1 LN2 LN3 LN4 LN5 LN6 LN7

LN0 : Line 0 Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disables the line

#1 : value2

Enables the line and resets a pending request

End of enumeration elements list.

LN1 : Line 1 Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disables the line

#1 : value2

Enables the line and resets a pending request

End of enumeration elements list.

LN2 : Line 2 Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disables the line

#1 : value2

Enables the line and resets a pending request

End of enumeration elements list.

LN3 : Line 3 Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disables the line

#1 : value2

Enables the line and resets a pending request

End of enumeration elements list.

LN4 : Line 4 Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disables the line

#1 : value2

Enables the line and resets a pending request

End of enumeration elements list.

LN5 : Line 5 Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disables the line

#1 : value2

Enables the line and resets a pending request

End of enumeration elements list.

LN6 : Line 6 Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disables the line

#1 : value2

Enables the line and resets a pending request

End of enumeration elements list.

LN7 : Line 7 Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disables the line

#1 : value2

Enables the line and resets a pending request

End of enumeration elements list.


OVRCLR

Overrun Clear
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OVRCLR OVRCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LN0 LN1 LN2 LN3 LN4 LN5 LN6 LN7

LN0 : Line 0 Overrun Status Clear
bits : 0 - -1 (0 bit)
access : write-only

LN1 : Line 1 Overrun Status Clear
bits : 1 - 0 (0 bit)
access : write-only

LN2 : Line 2 Overrun Status Clear
bits : 2 - 1 (0 bit)
access : write-only

LN3 : Line 3 Overrun Status Clear
bits : 3 - 2 (0 bit)
access : write-only

LN4 : Line 4 Overrun Status Clear
bits : 4 - 3 (0 bit)
access : write-only

LN5 : Line 5 Overrun Status Clear
bits : 5 - 4 (0 bit)
access : write-only

LN6 : Line 6 Overrun Status Clear
bits : 6 - 5 (0 bit)
access : write-only

LN7 : Line 7 Overrun Status Clear
bits : 7 - 6 (0 bit)
access : write-only


SRSEL0

Service Request Selection 0
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRSEL0 SRSEL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RS0 RS1 RS2 RS3 RS4 RS5 RS6 RS7

RS0 : Request Source for Line 0
bits : 0 - 2 (3 bit)
access : read-write

RS1 : Request Source for Line 1
bits : 4 - 6 (3 bit)
access : read-write

RS2 : Request Source for Line 2
bits : 8 - 10 (3 bit)
access : read-write

RS3 : Request Source for Line 3
bits : 12 - 14 (3 bit)
access : read-write

RS4 : Request Source for Line 4
bits : 16 - 18 (3 bit)
access : read-write

RS5 : Request Source for Line 5
bits : 20 - 22 (3 bit)
access : read-write

RS6 : Request Source for Line 6
bits : 24 - 26 (3 bit)
access : read-write

RS7 : Request Source for Line 7
bits : 28 - 30 (3 bit)
access : read-write



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