\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
interrupt status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
GIF1 : Channel x global interrupt flag (x = 1 ..7)
bits : 0 - 0 (1 bit)
TCIF1 : Channel x transfer complete flag (x = 1 ..7)
bits : 1 - 1 (1 bit)
HTIF1 : Channel x half transfer flag (x = 1 ..7)
bits : 2 - 2 (1 bit)
TEIF1 : Channel x transfer error flag (x = 1 ..7)
bits : 3 - 3 (1 bit)
GIF2 : Channel x global interrupt flag (x = 1 ..7)
bits : 4 - 4 (1 bit)
TCIF2 : Channel x transfer complete flag (x = 1 ..7)
bits : 5 - 5 (1 bit)
HTIF2 : Channel x half transfer flag (x = 1 ..7)
bits : 6 - 6 (1 bit)
TEIF2 : Channel x transfer error flag (x = 1 ..7)
bits : 7 - 7 (1 bit)
GIF3 : Channel x global interrupt flag (x = 1 ..7)
bits : 8 - 8 (1 bit)
TCIF3 : Channel x transfer complete flag (x = 1 ..7)
bits : 9 - 9 (1 bit)
HTIF3 : Channel x half transfer flag (x = 1 ..7)
bits : 10 - 10 (1 bit)
TEIF3 : Channel x transfer error flag (x = 1 ..7)
bits : 11 - 11 (1 bit)
GIF4 : Channel x global interrupt flag (x = 1 ..7)
bits : 12 - 12 (1 bit)
TCIF4 : Channel x transfer complete flag (x = 1 ..7)
bits : 13 - 13 (1 bit)
HTIF4 : Channel x half transfer flag (x = 1 ..7)
bits : 14 - 14 (1 bit)
TEIF4 : Channel x transfer error flag (x = 1 ..7)
bits : 15 - 15 (1 bit)
GIF5 : Channel x global interrupt flag (x = 1 ..7)
bits : 16 - 16 (1 bit)
TCIF5 : Channel x transfer complete flag (x = 1 ..7)
bits : 17 - 17 (1 bit)
HTIF5 : Channel x half transfer flag (x = 1 ..7)
bits : 18 - 18 (1 bit)
TEIF5 : Channel x transfer error flag (x = 1 ..7)
bits : 19 - 19 (1 bit)
GIF6 : Channel x global interrupt flag (x = 1 ..7)
bits : 20 - 20 (1 bit)
TCIF6 : Channel x transfer complete flag (x = 1 ..7)
bits : 21 - 21 (1 bit)
HTIF6 : Channel x half transfer flag (x = 1 ..7)
bits : 22 - 22 (1 bit)
TEIF6 : Channel x transfer error flag (x = 1 ..7)
bits : 23 - 23 (1 bit)
GIF7 : Channel x global interrupt flag (x = 1 ..7)
bits : 24 - 24 (1 bit)
TCIF7 : Channel x transfer complete flag (x = 1 ..7)
bits : 25 - 25 (1 bit)
HTIF7 : Channel x half transfer flag (x = 1 ..7)
bits : 26 - 26 (1 bit)
TEIF7 : Channel x transfer error flag (x = 1 ..7)
bits : 27 - 27 (1 bit)
channel x peripheral address register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
channel x configuration register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : Data transfer direction
bits : 4 - 4 (1 bit)
CIRC : Circular mode
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : Memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size
bits : 8 - 9 (2 bit)
MSIZE : Memory size
bits : 10 - 11 (2 bit)
PL : Channel priority level
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)
channel x number of data register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer
bits : 0 - 15 (16 bit)
channel x peripheral address register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
channel x configuration register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : Data transfer direction
bits : 4 - 4 (1 bit)
CIRC : Circular mode
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : Memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size
bits : 8 - 9 (2 bit)
MSIZE : Memory size
bits : 10 - 11 (2 bit)
PL : Channel priority level
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)
channel x number of data register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer
bits : 0 - 15 (16 bit)
channel x peripheral address register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
interrupt flag clear register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CGIF1 : Channel x global interrupt clear (x = 1 ..7)
bits : 0 - 0 (1 bit)
CTCIF1 : Channel x transfer complete clear (x = 1 ..7)
bits : 1 - 1 (1 bit)
CHTIF1 : Channel x half transfer clear (x = 1 ..7)
bits : 2 - 2 (1 bit)
CTEIF1 : Channel x transfer error clear (x = 1 ..7)
bits : 3 - 3 (1 bit)
CGIF2 : Channel x global interrupt clear (x = 1 ..7)
bits : 4 - 4 (1 bit)
CTCIF2 : Channel x transfer complete clear (x = 1 ..7)
bits : 5 - 5 (1 bit)
CHTIF2 : Channel x half transfer clear (x = 1 ..7)
bits : 6 - 6 (1 bit)
CTEIF2 : Channel x transfer error clear (x = 1 ..7)
bits : 7 - 7 (1 bit)
CGIF3 : Channel x global interrupt clear (x = 1 ..7)
bits : 8 - 8 (1 bit)
CTCIF3 : Channel x transfer complete clear (x = 1 ..7)
bits : 9 - 9 (1 bit)
CHTIF3 : Channel x half transfer clear (x = 1 ..7)
bits : 10 - 10 (1 bit)
CTEIF3 : Channel x transfer error clear (x = 1 ..7)
bits : 11 - 11 (1 bit)
CGIF4 : Channel x global interrupt clear (x = 1 ..7)
bits : 12 - 12 (1 bit)
CTCIF4 : Channel x transfer complete clear (x = 1 ..7)
bits : 13 - 13 (1 bit)
CHTIF4 : Channel x half transfer clear (x = 1 ..7)
bits : 14 - 14 (1 bit)
CTEIF4 : Channel x transfer error clear (x = 1 ..7)
bits : 15 - 15 (1 bit)
CGIF5 : Channel x global interrupt clear (x = 1 ..7)
bits : 16 - 16 (1 bit)
CTCIF5 : Channel x transfer complete clear (x = 1 ..7)
bits : 17 - 17 (1 bit)
CHTIF5 : Channel x half transfer clear (x = 1 ..7)
bits : 18 - 18 (1 bit)
CTEIF5 : Channel x transfer error clear (x = 1 ..7)
bits : 19 - 19 (1 bit)
CGIF6 : Channel x global interrupt clear (x = 1 ..7)
bits : 20 - 20 (1 bit)
CTCIF6 : Channel x transfer complete clear (x = 1 ..7)
bits : 21 - 21 (1 bit)
CHTIF6 : Channel x half transfer clear (x = 1 ..7)
bits : 22 - 22 (1 bit)
CTEIF6 : Channel x transfer error clear (x = 1 ..7)
bits : 23 - 23 (1 bit)
CGIF7 : Channel x global interrupt clear (x = 1 ..7)
bits : 24 - 24 (1 bit)
CTCIF7 : Channel x transfer complete clear (x = 1 ..7)
bits : 25 - 25 (1 bit)
CHTIF7 : Channel x half transfer clear (x = 1 ..7)
bits : 26 - 26 (1 bit)
CTEIF7 : Channel x transfer error clear (x = 1 ..7)
bits : 27 - 27 (1 bit)
channel x configuration register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : Data transfer direction
bits : 4 - 4 (1 bit)
CIRC : Circular mode
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : Memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size
bits : 8 - 9 (2 bit)
MSIZE : Memory size
bits : 10 - 11 (2 bit)
PL : Channel priority level
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)
channel x number of data register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer
bits : 0 - 15 (16 bit)
channel x peripheral address register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
channel x configuration register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : Data transfer direction
bits : 4 - 4 (1 bit)
CIRC : Circular mode
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : Memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size
bits : 8 - 9 (2 bit)
MSIZE : Memory size
bits : 10 - 11 (2 bit)
PL : Channel priority level
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)
channel x number of data register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer
bits : 0 - 15 (16 bit)
channel x peripheral address register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
channel x configuration register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : Data transfer direction
bits : 4 - 4 (1 bit)
CIRC : Circular mode
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : Memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size
bits : 8 - 9 (2 bit)
MSIZE : Memory size
bits : 10 - 11 (2 bit)
PL : Channel priority level
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)
channel x number of data register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer
bits : 0 - 15 (16 bit)
channel x peripheral address register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
channel x configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : Data transfer direction
bits : 4 - 4 (1 bit)
CIRC : Circular mode
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : Memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size
bits : 8 - 9 (2 bit)
MSIZE : Memory size
bits : 10 - 11 (2 bit)
PL : Channel priority level
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)
channel x configuration register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Channel enable
bits : 0 - 0 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 1 - 1 (1 bit)
HTIE : Half transfer interrupt enable
bits : 2 - 2 (1 bit)
TEIE : Transfer error interrupt enable
bits : 3 - 3 (1 bit)
DIR : Data transfer direction
bits : 4 - 4 (1 bit)
CIRC : Circular mode
bits : 5 - 5 (1 bit)
PINC : Peripheral increment mode
bits : 6 - 6 (1 bit)
MINC : Memory increment mode
bits : 7 - 7 (1 bit)
PSIZE : Peripheral size
bits : 8 - 9 (2 bit)
MSIZE : Memory size
bits : 10 - 11 (2 bit)
PL : Channel priority level
bits : 12 - 13 (2 bit)
MEM2MEM : Memory to memory mode
bits : 14 - 14 (1 bit)
channel x number of data register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer
bits : 0 - 15 (16 bit)
channel x peripheral address register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PA : Peripheral address
bits : 0 - 31 (32 bit)
channel x memory address register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MA : Memory address
bits : 0 - 31 (32 bit)
channel selection register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C1S : DMA channel 1 selection
bits : 0 - 3 (4 bit)
C2S : DMA channel 2 selection
bits : 4 - 7 (4 bit)
C3S : DMA channel 3 selection
bits : 8 - 11 (4 bit)
C4S : DMA channel 4 selection
bits : 12 - 15 (4 bit)
C5S : DMA channel 5 selection
bits : 16 - 19 (4 bit)
C6S : DMA channel 6 selection
bits : 20 - 23 (4 bit)
C7S : DMA channel 7 selection
bits : 24 - 27 (4 bit)
channel x number of data register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NDT : Number of data to transfer
bits : 0 - 15 (16 bit)
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