\n

USB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x40000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

GOTGCTL

GRSTCTL

HPTXFSIZ

DIEPTXF1

DIEPTXF2

DIEPTXF3

DIEPTXF4

DIEPTXF5

DIEPTXF6

GINTSTS_HOSTMODE

GINTSTS_DEVICEMODE

GINTMSK_HOSTMODE

GINTMSK_DEVICEMODE

GRXSTSR_HOSTMODE

GRXSTSR_DEVICEMODE

GRXSTSP_DEVICEMODE

GRXSTSP_HOSTMODE

GRXFSIZ

GNPTXFSIZ_HOSTMODE

GNPTXFSIZ_DEVICEMODE

GNPTXSTS

GUID

GOTGINT

HCFG

HFIR

HFNUM

HPTXSTS

HAINT

HAINTMSK

HFLBADDR

HPRT

GDFIFOCFG

GAHBCFG

DCFG

DCTL

DSTS

DIEPMSK

DOEPMSK

DAINT

DAINTMSK

DVBUSDIS

DVBUSPULSE

DIEPEMPMSK

GUSBCFG

PCGCCTL


GOTGCTL

Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GOTGCTL GOTGCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SesReqScs SesReq VbvalidOvEn VbvalidOvVal AvalidOvEn AvalidOvVal BvalidOvEn BvalidOvVal HstNegScs HNPReq HstSetHNPEn DevHNPEn ConlDSts DbncTime ASesVId BSesVld OTGVer

SesReqScs : Session Request Success
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Session request failure

#1 : value2

Session request success

End of enumeration elements list.

SesReq : Session Request
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

No session request

#1 : value2

Session request

End of enumeration elements list.

VbvalidOvEn : VBUS Valid Override Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Override is disabled and vbus valid signal from the PHY is used internally by the core.

#1 : value2

Internally vbus valid received from the PHY is overridden with GOTGCTL.VbvalidOvVal.

End of enumeration elements list.

VbvalidOvVal : VBUS Valid Override Value
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

vbusvalid value is 0# when GOTGCTL.VbvalidOvEn = 1

#1 : value2

vbusvalid value is 1# when GOTGCTL.VbvalidOvEn = 1

End of enumeration elements list.

AvalidOvEn : A-Peripheral Session Valid Override Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Override is disabled and Avalid signal from the PHY is used internally by the core.

#1 : value2

Internally Avalid received from the PHY is overridden with GOTGCTL.AvalidOvVal.

End of enumeration elements list.

AvalidOvVal : A-Peripheral Session Valid Override Value
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Avalid value is 0# when GOTGCTL.AvalidOvEn = 1

#1 : value2

Avalid value is 1# when GOTGCTL.AvalidOvEn = 1

End of enumeration elements list.

BvalidOvEn : B-Peripheral Session Valid Override Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Override is disabled and Bvalid signal from the PHY is used internally by the core.

#1 : value2

Internally Bvalid received from the PHY is overridden with GOTGCTL.BvalidOvVal.

End of enumeration elements list.

BvalidOvVal : B-Peripheral Session Valid Override Value
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Bvalid value is 0# when GOTGCTL.BvalidOvEn = 1

#1 : value2

Bvalid value is 1# when GOTGCTL.BvalidOvEn = 1

End of enumeration elements list.

HstNegScs : Host Negotiation Success
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

Host negotiation failure

#1 : value2

Host negotiation success

End of enumeration elements list.

HNPReq : HNP Request
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : value1

No HNP request

#1 : value2

HNP request

End of enumeration elements list.

HstSetHNPEn : Host Set HNP Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

Host Set HNP is not enabled

#1 : value2

Host Set HNP is enabled

End of enumeration elements list.

DevHNPEn : Device HNP Enabled
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

HNP is not enabled in the application

#1 : value2

HNP is enabled in the application

End of enumeration elements list.

ConlDSts : Connector ID Status
bits : 16 - 15 (0 bit)
access : read-only

Enumeration:

#0 : value1

The USB core is in A-Device mode

#1 : value2

The USB core is in B-Device mode

End of enumeration elements list.

DbncTime : Long/Short Debounce Time
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

#0 : value1

Long debounce time, used for physical connections (100 ms + 2.5 us)

#1 : value2

Short debounce time, used for soft connections (2.5 us)

End of enumeration elements list.

ASesVId : A-Session Valid
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

#0 : value1

A-session is not valid

#1 : value2

A-session is valid

End of enumeration elements list.

BSesVld : B-Session Valid
bits : 19 - 18 (0 bit)
access : read-only

Enumeration:

#0 : value1

B-session is not valid.

#1 : value2

B-session is valid.

End of enumeration elements list.

OTGVer : OTG Version
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : value1

OTG Version 1.3. In this version the core supports Data line pulsing and VBus pulsing for SRP.

#1 : value2

OTG Version 2.0. In this version the core supports only Data line pulsing for SRP.

End of enumeration elements list.


GRSTCTL

Reset Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRSTCTL GRSTCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CSftRst FrmCntrRst RxFFlsh TxFFlsh TxFNum DMAReq AHBIdle

CSftRst : Core Soft Reset
bits : 0 - -1 (0 bit)
access : read-write

FrmCntrRst : Host Frame Counter Reset
bits : 2 - 1 (0 bit)
access : read-write

RxFFlsh : RxFIFO Flush
bits : 4 - 3 (0 bit)
access : read-write

TxFFlsh : TxFIFO Flush
bits : 5 - 4 (0 bit)
access : read-write

TxFNum : TxFIFO Number
bits : 6 - 9 (4 bit)
access : read-write

Enumeration:

0x00 : value1

Non-periodic TxFIFO flush in Host mode or Tx FIFO 0 flush in device mode

0x01 : value2

Periodic TxFIFO flush in Host mode or Tx FIFO 1 flush in device mode

0x02 : value3

Tx FIFO 2 flush in device mode

0x0F : value4

Tx FIFO 15 flush in device mode

0x10 : value5

Flush all the transmit FIFOs in device or host mode.

End of enumeration elements list.

DMAReq : DMA Request Signal
bits : 30 - 29 (0 bit)
access : read-only

AHBIdle : AHB Master Idle
bits : 31 - 30 (0 bit)
access : read-only


HPTXFSIZ

Host Periodic Transmit FIFO Size Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPTXFSIZ HPTXFSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTxFStAddr PTxFSize

PTxFStAddr : Host Periodic TxFIFO Start Address
bits : 0 - 14 (15 bit)
access : read-write

PTxFSize : Host Periodic TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write


DIEPTXF1

Device IN Endpoint Transmit FIFO Size Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF1 DIEPTXF1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPnTxFStAddr INEPnTxFDep

INEPnTxFStAddr : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write

INEPnTxFDep : IN Endpoint TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write


DIEPTXF2

Device IN Endpoint Transmit FIFO Size Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF2 DIEPTXF2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPnTxFStAddr INEPnTxFDep

INEPnTxFStAddr : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write

INEPnTxFDep : IN Endpoint TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write


DIEPTXF3

Device IN Endpoint Transmit FIFO Size Register
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF3 DIEPTXF3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPnTxFStAddr INEPnTxFDep

INEPnTxFStAddr : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write

INEPnTxFDep : IN Endpoint TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write


DIEPTXF4

Device IN Endpoint Transmit FIFO Size Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF4 DIEPTXF4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPnTxFStAddr INEPnTxFDep

INEPnTxFStAddr : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write

INEPnTxFDep : IN Endpoint TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write


DIEPTXF5

Device IN Endpoint Transmit FIFO Size Register
address_offset : 0x114 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF5 DIEPTXF5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPnTxFStAddr INEPnTxFDep

INEPnTxFStAddr : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write

INEPnTxFDep : IN Endpoint TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write


DIEPTXF6

Device IN Endpoint Transmit FIFO Size Register
address_offset : 0x118 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPTXF6 DIEPTXF6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPnTxFStAddr INEPnTxFDep

INEPnTxFStAddr : IN Endpoint FIFOn Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write

INEPnTxFDep : IN Endpoint TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write


GINTSTS_HOSTMODE

Interrupt Register [HOSTMODE]
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GINTSTS_HOSTMODE GINTSTS_HOSTMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CurMod ModeMis OTGInt Sof RxFLvl incomplP PrtInt HChInt PTxFEmp ConIDStsChng DisconnInt SessReqInt WkUpInt

CurMod : Current Mode of Operation
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Device mode

#1 : value2

Host mode

End of enumeration elements list.

ModeMis : Mode Mismatch Interrupt
bits : 1 - 0 (0 bit)
access : read-write

OTGInt : OTG Interrupt
bits : 2 - 1 (0 bit)
access : read-only

Sof : Start of Frame
bits : 3 - 2 (0 bit)
access : read-write

RxFLvl : RxFIFO Non-Empty
bits : 4 - 3 (0 bit)
access : read-only

incomplP : Incomplete Periodic Transfer
bits : 21 - 20 (0 bit)
access : read-write

PrtInt : Host Port Interrupt
bits : 24 - 23 (0 bit)
access : read-only

HChInt : Host Channels Interrupt
bits : 25 - 24 (0 bit)
access : read-only

PTxFEmp : Periodic TxFIFO Empty
bits : 26 - 25 (0 bit)
access : read-only

ConIDStsChng : Connector ID Status Change
bits : 28 - 27 (0 bit)
access : read-write

DisconnInt : Disconnect Detected Interrupt
bits : 29 - 28 (0 bit)
access : read-write

SessReqInt : Session Request/New Session Detected Interrupt
bits : 30 - 29 (0 bit)
access : read-write

WkUpInt : Resume/Remote Wakeup Detected Interrupt
bits : 31 - 30 (0 bit)
access : read-write


GINTSTS_DEVICEMODE

Interrupt Register [DEVICEMODE]
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : GINTSTS_HOSTMODE
reset_Mask : 0x0

GINTSTS_DEVICEMODE GINTSTS_DEVICEMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CurMod ModeMis OTGInt Sof RxFLvl GINNakEff GOUTNakEff ErlySusp USBSusp USBRst EnumDone ISOOutDrop EOPF IEPInt OEPInt incompISOIN incomplSOOUT ConIDStsChng SessReqInt WkUpInt

CurMod : Current Mode of Operation
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Device mode

#1 : value2

Host mode

End of enumeration elements list.

ModeMis : Mode Mismatch Interrupt
bits : 1 - 0 (0 bit)
access : read-write

OTGInt : OTG Interrupt
bits : 2 - 1 (0 bit)
access : read-only

Sof : Start of Frame
bits : 3 - 2 (0 bit)
access : read-write

RxFLvl : RxFIFO Non-Empty
bits : 4 - 3 (0 bit)
access : read-only

GINNakEff : Global IN Non-Periodic NAK Effective
bits : 6 - 5 (0 bit)
access : read-only

GOUTNakEff : Global OUT NAK Effective
bits : 7 - 6 (0 bit)
access : read-only

ErlySusp : Early Suspend
bits : 10 - 9 (0 bit)
access : read-write

USBSusp : USB Suspend
bits : 11 - 10 (0 bit)
access : read-write

USBRst : USB Reset
bits : 12 - 11 (0 bit)
access : read-write

EnumDone : Enumeration Done
bits : 13 - 12 (0 bit)
access : read-write

ISOOutDrop : Isochronous OUT Packet Dropped Interrupt
bits : 14 - 13 (0 bit)
access : read-write

EOPF : End of Periodic Frame Interrupt
bits : 15 - 14 (0 bit)
access : read-write

IEPInt : IN Endpoints Interrupt
bits : 18 - 17 (0 bit)
access : read-only

OEPInt : OUT Endpoints Interrupt
bits : 19 - 18 (0 bit)
access : read-only

incompISOIN : Incomplete Isochronous IN Transfer
bits : 20 - 19 (0 bit)
access : read-write

incomplSOOUT : Incomplete Isochronous OUT Transfer
bits : 21 - 20 (0 bit)
access : read-write

ConIDStsChng : Connector ID Status Change
bits : 28 - 27 (0 bit)
access : read-write

SessReqInt : Session Request/New Session Detected Interrupt
bits : 30 - 29 (0 bit)
access : read-write

WkUpInt : Resume/Remote Wakeup Detected Interrupt
bits : 31 - 30 (0 bit)
access : read-write


GINTMSK_HOSTMODE

Interrupt Mask Register [HOSTMODE]
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GINTMSK_HOSTMODE GINTMSK_HOSTMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ModeMisMsk OTGIntMsk SofMsk RxFLvlMsk incomplPMsk PrtIntMsk HChIntMsk PTxFEmpMsk ConIDStsChngMsk DisconnIntMsk SessReqIntMsk WkUpIntMsk

ModeMisMsk : Mode Mismatch Interrupt Mask
bits : 1 - 0 (0 bit)
access : read-write

OTGIntMsk : OTG Interrupt Mask
bits : 2 - 1 (0 bit)
access : read-write

SofMsk : Start of Frame Mask
bits : 3 - 2 (0 bit)
access : read-write

RxFLvlMsk : Receive FIFO Non-Empty Mask
bits : 4 - 3 (0 bit)
access : read-write

incomplPMsk : Incomplete Periodic Transfer Mask
bits : 21 - 20 (0 bit)
access : read-write

PrtIntMsk : Host Port Interrupt Mask
bits : 24 - 23 (0 bit)
access : read-write

HChIntMsk : Host Channels Interrupt Mask
bits : 25 - 24 (0 bit)
access : read-write

PTxFEmpMsk : Periodic TxFIFO Empty Mask
bits : 26 - 25 (0 bit)
access : read-write

ConIDStsChngMsk : Connector ID Status Change Mask
bits : 28 - 27 (0 bit)
access : read-write

DisconnIntMsk : Disconnect Detected Interrupt Mask
bits : 29 - 28 (0 bit)
access : read-write

SessReqIntMsk : Session Request/New Session Detected Interrupt Mask
bits : 30 - 29 (0 bit)
access : read-write

WkUpIntMsk : Resume/Remote Wakeup Detected Interrupt Mask
bits : 31 - 30 (0 bit)
access : read-write


GINTMSK_DEVICEMODE

Interrupt Mask Register [DEVICEMODE]
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : GINTMSK_HOSTMODE
reset_Mask : 0x0

GINTMSK_DEVICEMODE GINTMSK_DEVICEMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ModeMisMsk OTGIntMsk SofMsk RxFLvlMsk GINNakEffMsk GOUTNakEffMsk ErlySuspMsk USBSuspMsk USBRstMsk EnumDoneMsk ISOOutDropMsk EOPFMsk IEPIntMsk OEPIntMsk incompISOINMsk incomplSOOUTMsk ConIDStsChngMsk DisconnIntMsk SessReqIntMsk WkUpIntMsk

ModeMisMsk : Mode Mismatch Interrupt Mask
bits : 1 - 0 (0 bit)
access : read-write

OTGIntMsk : OTG Interrupt Mask
bits : 2 - 1 (0 bit)
access : read-write

SofMsk : Start of Frame Mask
bits : 3 - 2 (0 bit)
access : read-write

RxFLvlMsk : Receive FIFO Non-Empty Mask
bits : 4 - 3 (0 bit)
access : read-write

GINNakEffMsk : Global Non-periodic IN NAK Effective Mask
bits : 6 - 5 (0 bit)
access : read-write

GOUTNakEffMsk : Global OUT NAK Effective Mask
bits : 7 - 6 (0 bit)
access : read-write

ErlySuspMsk : Early Suspend Mask
bits : 10 - 9 (0 bit)
access : read-write

USBSuspMsk : USB Suspend Mask
bits : 11 - 10 (0 bit)
access : read-write

USBRstMsk : USB Reset Mask
bits : 12 - 11 (0 bit)
access : read-write

EnumDoneMsk : Enumeration Done Mask
bits : 13 - 12 (0 bit)
access : read-write

ISOOutDropMsk : Isochronous OUT Packet Dropped Interrupt Mask
bits : 14 - 13 (0 bit)
access : read-write

EOPFMsk : End of Periodic Frame Interrupt Mask
bits : 15 - 14 (0 bit)
access : read-write

IEPIntMsk : IN Endpoints Interrupt Mask
bits : 18 - 17 (0 bit)
access : read-write

OEPIntMsk : OUT Endpoints Interrupt Mask
bits : 19 - 18 (0 bit)
access : read-write

incompISOINMsk : Incomplete Isochronous IN Transfer Mask
bits : 20 - 19 (0 bit)
access : read-write

incomplSOOUTMsk : Incomplete Isochronous OUT Transfer Mask
bits : 21 - 20 (0 bit)
access : read-write

ConIDStsChngMsk : Connector ID Status Change Mask
bits : 28 - 27 (0 bit)
access : read-write

DisconnIntMsk : Disconnect Detected Interrupt Mask
bits : 29 - 28 (0 bit)
access : read-write

SessReqIntMsk : Session Request/New Session Detected Interrupt Mask
bits : 30 - 29 (0 bit)
access : read-write

WkUpIntMsk : Resume/Remote Wakeup Detected Interrupt Mask
bits : 31 - 30 (0 bit)
access : read-write


GRXSTSR_HOSTMODE

Receive Status Debug Read Register [HOSTMODE]
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRXSTSR_HOSTMODE GRXSTSR_HOSTMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ChNum BCnt DPID PktSts

ChNum : Channel Number
bits : 0 - 2 (3 bit)
access : read-only

BCnt : Byte Count
bits : 4 - 13 (10 bit)
access : read-only

DPID : Data PID
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#00 : value1

DATA0

#10 : value2

DATA1

#01 : value3

DATA2

#11 : value4

MDATA

End of enumeration elements list.

PktSts : Packet Status
bits : 17 - 19 (3 bit)
access : read-only

Enumeration:

#0010 : value1

IN data packet received

#0011 : value2

IN transfer completed (triggers an interrupt)

#0101 : value3

Data toggle error (triggers an interrupt)

#0111 : value4

Channel halted (triggers an interrupt)

End of enumeration elements list.


GRXSTSR_DEVICEMODE

Receive Status Debug Read Register [DEVICEMODE]
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : GRXSTSR_HOSTMODE
reset_Mask : 0x0

GRXSTSR_DEVICEMODE GRXSTSR_DEVICEMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPNum BCnt DPID PktSts FN

EPNum : Endpoint Number
bits : 0 - 2 (3 bit)
access : read-only

BCnt : Byte Count
bits : 4 - 13 (10 bit)
access : read-only

DPID : Data PID
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#00 : value1

DATA0

#10 : value2

DATA1

#01 : value3

DATA2

#11 : value4

MDATA

End of enumeration elements list.

PktSts : Packet Status
bits : 17 - 19 (3 bit)
access : read-only

Enumeration:

#0001 : value1

Global OUT NAK (triggers an interrupt)

#0010 : value2

OUT data packet received

#0011 : value3

OUT transfer completed (triggers an interrupt)

#0100 : value4

SETUP transaction completed (triggers an interrupt)

#0110 : value5

SETUP data packet received

End of enumeration elements list.

FN : Frame Number
bits : 21 - 23 (3 bit)
access : read-only


GRXSTSP_DEVICEMODE

Receive Status Read and Pop Register [DEVICEMODE]
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRXSTSP_DEVICEMODE GRXSTSP_DEVICEMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EPNum BCnt DPID PktSts FN

EPNum : Endpoint Number
bits : 0 - 2 (3 bit)
access : read-only

BCnt : Byte Count
bits : 4 - 13 (10 bit)
access : read-only

DPID : Data PID
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#00 : value1

DATA0

#10 : value2

DATA1

#01 : value3

DATA2

#11 : value4

MDATA

End of enumeration elements list.

PktSts : Packet Status
bits : 17 - 19 (3 bit)
access : read-only

Enumeration:

#0001 : value1

Global OUT NAK (triggers an interrupt)

#0010 : value2

OUT data packet received

#0011 : value3

OUT transfer completed (triggers an interrupt)

#0100 : value4

SETUP transaction completed (triggers an interrupt)

#0110 : value5

SETUP data packet received

End of enumeration elements list.

FN : Frame Number
bits : 21 - 23 (3 bit)
access : read-only


GRXSTSP_HOSTMODE

Receive Status Read and Pop Register [HOSTMODE]
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : GRXSTSP_DEVICEMODE
reset_Mask : 0x0

GRXSTSP_HOSTMODE GRXSTSP_HOSTMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ChNum BCnt DPID PktSts

ChNum : Channel Number
bits : 0 - 2 (3 bit)
access : read-only

BCnt : Byte Count
bits : 4 - 13 (10 bit)
access : read-only

DPID : Data PID
bits : 15 - 15 (1 bit)
access : read-only

Enumeration:

#00 : value1

DATA0

#10 : value2

DATA1

#01 : value3

DATA2

#11 : value4

MDATA

End of enumeration elements list.

PktSts : Packet Status
bits : 17 - 19 (3 bit)
access : read-only

Enumeration:

#0010 : value1

IN data packet received

#0011 : value2

IN transfer completed (triggers an interrupt)

#0101 : value3

Data toggle error (triggers an interrupt)

#0111 : value4

Channel halted (triggers an interrupt)

End of enumeration elements list.


GRXFSIZ

Receive FIFO Size Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GRXFSIZ GRXFSIZ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RxFDep

RxFDep : RxFIFO Depth
bits : 0 - 14 (15 bit)
access : read-write


GNPTXFSIZ_HOSTMODE

Non-Periodic Transmit FIFO Size Register [HOSTMODE]
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GNPTXFSIZ_HOSTMODE GNPTXFSIZ_HOSTMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPTxFStAddr NPTxFDep

NPTxFStAddr : Non-periodic Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write

NPTxFDep : Non-periodic TxFIFO Depth
bits : 16 - 30 (15 bit)
access : read-write


GNPTXFSIZ_DEVICEMODE

Non-Periodic Transmit FIFO Size Register [DEVICEMODE]
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : GNPTXFSIZ_HOSTMODE
reset_Mask : 0x0

GNPTXFSIZ_DEVICEMODE GNPTXFSIZ_DEVICEMODE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INEPTxF0StAddr INEPTxF0Dep

INEPTxF0StAddr : IN Endpoint FIFO0 Transmit RAM Start Address
bits : 0 - 14 (15 bit)
access : read-write

INEPTxF0Dep : IN Endpoint TxFIFO 0 Depth
bits : 16 - 30 (15 bit)
access : read-write


GNPTXSTS

Non-Periodic Transmit FIFO/Queue Status Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GNPTXSTS GNPTXSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NPTxFSpcAvail NPTxQSpcAvail NPTxQTop

NPTxFSpcAvail : Non-periodic TxFIFO Space Avail
bits : 0 - 14 (15 bit)
access : read-only

Enumeration:

0x0 : value1

Non-periodic TxFIFO is full

0x1 : value2

1 word available

0x2 : value3

2 words available

End of enumeration elements list.

NPTxQSpcAvail : Non-periodic Transmit Request Queue Space Available
bits : 16 - 22 (7 bit)
access : read-only

Enumeration:

0x0 : value1

Non-periodic Transmit Request Queue is full

0x1 : value2

1 location available

0x2 : value3

2 locations available

End of enumeration elements list.

NPTxQTop : Top of the Non-periodic Transmit Request Queue
bits : 24 - 29 (6 bit)
access : read-only

Enumeration:

#00 : value1

IN/OUT token

#01 : value2

Zero-length transmit packet (device IN/host OUT)

#11 : value4

Channel halt command

End of enumeration elements list.


GUID

USB Module Identification Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GUID GUID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MOD_REV MOD_TYPE MOD_NUMBER

MOD_REV : Module Revision
bits : 0 - 6 (7 bit)
access : read-write

MOD_TYPE : Module Type
bits : 8 - 14 (7 bit)
access : read-write

MOD_NUMBER : Module Number
bits : 16 - 30 (15 bit)
access : read-write


GOTGINT

OTG Interrupt Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GOTGINT GOTGINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SesEndDet SesReqSucStsChng HstNegSucStsChng HstNegDet ADevTOUTChg DbnceDone

SesEndDet : Session End Detected
bits : 2 - 1 (0 bit)
access : read-write

SesReqSucStsChng : Session Request Success Status Change
bits : 8 - 7 (0 bit)
access : read-write

HstNegSucStsChng : Host Negotiation Success Status Change
bits : 9 - 8 (0 bit)
access : read-write

HstNegDet : Host Negotiation Detected
bits : 17 - 16 (0 bit)
access : read-write

ADevTOUTChg : A-Device Timeout Change
bits : 18 - 17 (0 bit)
access : read-write

DbnceDone : Debounce Done
bits : 19 - 18 (0 bit)
access : read-write


HCFG

Host Configuration Register
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HCFG HCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FSLSPclkSel FSLSSupp DescDMA FrListEn PerSchedEna

FSLSPclkSel : FS PHY Clock Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#01 : value1

PHY clock is running at 48 MHz

End of enumeration elements list.

FSLSSupp : FS-Only Support
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

FS-only, connected device can supports also only FS.

#1 : value2

FS-only, even if the connected device can support HS

End of enumeration elements list.

DescDMA : Enable Scatter/gather DMA in Host mode
bits : 23 - 22 (0 bit)
access : read-write

FrListEn : Frame List Entries
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#00 : value1

8 Entries

#01 : value2

16 Entries

#10 : value3

32 Entries

#11 : value4

64 Entries

End of enumeration elements list.

PerSchedEna : Enable Periodic Scheduling
bits : 26 - 25 (0 bit)
access : read-write


HFIR

Host Frame Interval Register
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFIR HFIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FrInt HFIRRldCtrl

FrInt : Frame Interval
bits : 0 - 14 (15 bit)
access : read-write

HFIRRldCtrl : Reload Control
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : value1

HFIR cannot be reloaded dynamically

#1 : value2

HFIR can be dynamically reloaded during runtime

End of enumeration elements list.


HFNUM

Host Frame Number/Frame Time Remaining Register
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFNUM HFNUM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FrNum FrRem

FrNum : Frame Number
bits : 0 - 14 (15 bit)
access : read-write

FrRem : Frame Time Remaining
bits : 16 - 30 (15 bit)
access : read-only


HPTXSTS

Host Periodic Transmit FIFO/ Queue Status Register
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPTXSTS HPTXSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PTxFSpcAvail PTxQSpcAvail PTxQTop

PTxFSpcAvail : Periodic Transmit Data FIFO Space Available
bits : 0 - 14 (15 bit)
access : read-write

Enumeration:

#0 : value1

Periodic TxFIFO is full

0x1 : value2

1 word available

0x2 : value3

2 words available

End of enumeration elements list.

PTxQSpcAvail : Periodic Transmit Request Queue Space Available
bits : 16 - 22 (7 bit)
access : read-only

Enumeration:

0x0 : value1

Periodic Transmit Request Queue is full

0x1 : value2

1 location available

0x2 : value3

2 locations available

End of enumeration elements list.

PTxQTop : Top of the Periodic Transmit Request Queue
bits : 24 - 30 (7 bit)
access : read-only


HAINT

Host All Channels Interrupt Register
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HAINT HAINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAINT

HAINT : Channel Interrupts
bits : 0 - 12 (13 bit)
access : read-only


HAINTMSK

Host All Channels Interrupt Mask Register
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HAINTMSK HAINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HAINTMsk

HAINTMsk : Channel Interrupt Mask
bits : 0 - 12 (13 bit)
access : read-write


HFLBADDR

Host Frame List Base Address Register
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFLBADDR HFLBADDR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Starting_Address

Starting_Address : Starting Address
bits : 0 - 30 (31 bit)
access : read-write


HPRT

Host Port Control and Status Register
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HPRT HPRT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PrtConnSts PrtConnDet PrtEna PrtEnChng PrtOvrCurrAct PrtOvrCurrChng PrtRes PrtSusp PrtRst PrtLnSts PrtPwr PrtSpd

PrtConnSts : Port Connect Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

No device is attached to the port.

#1 : value2

A device is attached to the port.

End of enumeration elements list.

PrtConnDet : Port Connect Detected
bits : 1 - 0 (0 bit)
access : read-write

PrtEna : Port Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Port disabled

#1 : value2

Port enabled

End of enumeration elements list.

PrtEnChng : Port Enable/Disable Change
bits : 3 - 2 (0 bit)
access : read-write

PrtOvrCurrAct : Port Overcurrent Active
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : value1

No overcurrent condition

#1 : value2

Overcurrent condition

End of enumeration elements list.

PrtOvrCurrChng : Port Overcurrent Change
bits : 5 - 4 (0 bit)
access : read-write

PrtRes : Port Resume
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

No resume driven

#1 : value2

Resume driven

End of enumeration elements list.

PrtSusp : Port Suspend
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Port not in Suspend mode

#1 : value2

Port in Suspend mode

End of enumeration elements list.

PrtRst : Port Reset
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

Port not in reset

#1 : value2

Port in reset

End of enumeration elements list.

PrtLnSts : Port Line Status
bits : 10 - 10 (1 bit)
access : read-only

PrtPwr : Port Power
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : value1

Power off

#1 : value2

Power on

End of enumeration elements list.

PrtSpd : Port Speed
bits : 17 - 17 (1 bit)
access : read-only

Enumeration:

#01 : value1

Full speed

End of enumeration elements list.


GDFIFOCFG

Global DFIFO Software Config Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GDFIFOCFG GDFIFOCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GDFIFOCfg EPInfoBaseAddr

GDFIFOCfg : GDFIFOCfg
bits : 0 - 14 (15 bit)
access : read-write

EPInfoBaseAddr : EPInfoBaseAddr
bits : 16 - 30 (15 bit)
access : read-write


GAHBCFG

AHB Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GAHBCFG GAHBCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GlblIntrMsk HBstLen DMAEn NPTxFEmpLvl PTxFEmpLvl AHBSingle

GlblIntrMsk : Global Interrupt Mask
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Mask the interrupt assertion to the application.

#1 : value2

Unmask the interrupt assertion to the application.

End of enumeration elements list.

HBstLen : Burst Length/Type
bits : 1 - 3 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Single

#0001 : value2

INCR

#0011 : value3

INCR4

#0101 : value4

INCR8

#0111 : value5

INCR16

End of enumeration elements list.

DMAEn : DMA Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Core operates in Slave mode

#1 : value2

Core operates in a DMA mode

End of enumeration elements list.

NPTxFEmpLvl : Non-Periodic TxFIFO Empty Level
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

DIEPINTx.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is half empty

#1 : value2

DIEPINTx.TxFEmp interrupt indicates that the IN Endpoint TxFIFO is completely empty

End of enumeration elements list.

PTxFEmpLvl : Periodic TxFIFO Empty Level
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is half empty

#1 : value2

GINTSTS.PTxFEmp interrupt indicates that the Periodic TxFIFO is completely empty

End of enumeration elements list.

AHBSingle : AHB Single Support
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

#0 : value1

The remaining data in a transfer is sent using INCR burst size. This is the default mode.

#1 : value2

The remaining data in a transfer is sent using single burst size.

End of enumeration elements list.


DCFG

Device Configuration Register
address_offset : 0x800 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCFG DCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DevSpd NZStsOUTHShk DevAddr PerFrInt DescDMA PerSchIntvl

DevSpd : Device Speed
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#11 : value4

Full speed (USB 1.1 transceiver clock is 48 MHz)

End of enumeration elements list.

NZStsOUTHShk : Non-Zero-Length Status OUT Handshake
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#1 : value1

Send a STALL handshake on a nonzero-length status OUT transaction and do not send the received OUT packet to the application.

#0 : value2

Send the received OUT packet to the application (zero-length or nonzero-length) and send a handshake based on the NAK and STALL bits for the endpoint in the Device Endpoint Control register.

End of enumeration elements list.

DevAddr : Device Address
bits : 4 - 9 (6 bit)
access : read-write

PerFrInt : Periodic Frame Interval
bits : 11 - 11 (1 bit)
access : read-write

Enumeration:

#00 : value1

80% of the frame interval

#01 : value2

85%

#10 : value3

90%

#11 : value4

95%

End of enumeration elements list.

DescDMA : Enable Scatter/Gather DMA in Device mode.
bits : 23 - 22 (0 bit)
access : read-write

PerSchIntvl : Periodic Scheduling Interval
bits : 24 - 24 (1 bit)
access : read-write

Enumeration:

#00 : value1

25% of frame.

#01 : value2

50% of frame.

#10 : value3

75% of frame.

End of enumeration elements list.


DCTL

Device Control Register
address_offset : 0x804 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DCTL DCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RmtWkUpSig SftDiscon GNPINNakSts GOUTNakSts SGNPInNak CGNPInNak SGOUTNak CGOUTNak GMC IgnrFrmNum NakOnBble EnContOnBNA

RmtWkUpSig : Remote Wakeup Signaling
bits : 0 - -1 (0 bit)
access : read-write

SftDiscon : Soft Disconnect
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal operation. When this bit is cleared after a soft disconnect, the core drives a device connect event to the USB host. When the device is reconnected, the USB host restarts device enumeration.

#1 : value2

The core drives a device disconnect event to the USB host.

End of enumeration elements list.

GNPINNakSts : Global Non-periodic IN NAK Status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : value1

A handshake is sent out based on the data availability in the transmit FIFO.

#1 : value2

A NAK handshake is sent out on all non-periodic IN endpoints, irrespective of the data availability in the transmit FIFO.

End of enumeration elements list.

GOUTNakSts : Global OUT NAK Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : value1

A handshake is sent based on the FIFO Status and the NAK and STALL bit settings.

#1 : value2

No data is written to the RxFIFO, irrespective of space availability. Sends a NAK handshake on all packets, except on SETUP transactions. All isochronous OUT packets are dropped.

End of enumeration elements list.

SGNPInNak : Set Global Non-periodic IN NAK
bits : 7 - 6 (0 bit)
access : write-only

CGNPInNak : Clear Global Non-periodic IN NAK
bits : 8 - 7 (0 bit)
access : write-only

SGOUTNak : Set Global OUT NAK
bits : 9 - 8 (0 bit)
access : write-only

CGOUTNak : Clear Global OUT NAK
bits : 10 - 9 (0 bit)
access : write-only

GMC : Global Multi Count
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#00 : value1

Invalid.

#01 : value2

1 packet.

#10 : value3

2 packets.

#11 : value4

3 packets.

End of enumeration elements list.

IgnrFrmNum : Ignore frame number for isochronous endpoints in case of Scatter/Gather DMA
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : value1

Scatter/Gather enabled: The core transmits the packets only in the frame number in which they are intended to be transmitted. Scatter/Gather disabled: Periodic transfer interrupt feature is disabled; the application must program transfers for periodic endpoints every frame

#1 : value2

Scatter/Gather enabled: The core ignores the frame number, sending packets immediately as the packets are ready. Scatter/Gather disabled: Periodic transfer interrupt feature is enabled; the application can program transfers for multiple frames for periodic endpoints.

End of enumeration elements list.

NakOnBble : Set NAK automatically on babble
bits : 16 - 15 (0 bit)
access : read-write

EnContOnBNA : Enable continue on BNA
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : value1

After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the DOEPDMA descriptor.

#1 : value2

After receiving BNA interrupt, the core disables the endpoint. When the endpoint is re-enabled by the application, the core starts processing from the descriptor that received the BNA interrupt.

End of enumeration elements list.


DSTS

Device Status Register
address_offset : 0x808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DSTS DSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SuspSts EnumSpd ErrticErr SOFFN

SuspSts : Suspend Status
bits : 0 - -1 (0 bit)
access : read-only

EnumSpd : Enumerated Speed
bits : 1 - 1 (1 bit)
access : read-only

Enumeration:

#11 : value4

Full speed (PHY clock is running at 48 MHz)

End of enumeration elements list.

ErrticErr : Erratic Error
bits : 3 - 2 (0 bit)
access : read-only

SOFFN : Frame Number of the Received SOF
bits : 8 - 20 (13 bit)
access : read-only


DIEPMSK

Device IN Endpoint Common Interrupt Mask Register
address_offset : 0x810 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPMSK DIEPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XferComplMsk EPDisbldMsk AHBErrMsk TimeOUTMsk INTknTXFEmpMsk INEPNakEffMsk TxfifoUndrnMsk BNAInIntrMsk NAKMsk

XferComplMsk : Transfer Completed Interrupt Mask
bits : 0 - -1 (0 bit)
access : read-write

EPDisbldMsk : Endpoint Disabled Interrupt Mask
bits : 1 - 0 (0 bit)
access : read-write

AHBErrMsk : AHB Error Mask
bits : 2 - 1 (0 bit)
access : read-write

TimeOUTMsk : Timeout Condition Mask
bits : 3 - 2 (0 bit)
access : read-write

INTknTXFEmpMsk : IN Token Received When TxFIFO Empty Mask
bits : 4 - 3 (0 bit)
access : read-write

INEPNakEffMsk : IN Endpoint NAK Effective Mask
bits : 6 - 5 (0 bit)
access : read-write

TxfifoUndrnMsk : Fifo Underrun Mask
bits : 8 - 7 (0 bit)
access : read-write

BNAInIntrMsk : BNA Interrupt Mask
bits : 9 - 8 (0 bit)
access : read-write

NAKMsk : NAK interrupt Mask
bits : 13 - 12 (0 bit)
access : read-write


DOEPMSK

Device OUT Endpoint Common Interrupt Mask Register
address_offset : 0x814 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DOEPMSK DOEPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XferComplMsk EPDisbldMsk AHBErrMsk SetUPMsk OUTTknEPdisMsk Back2BackSETup OutPktErrMsk BnaOutIntrMsk BbleErrMsk NAKMsk NYETMsk

XferComplMsk : Transfer Completed Interrupt Mask
bits : 0 - -1 (0 bit)
access : read-write

EPDisbldMsk : Endpoint Disabled Interrupt Mask
bits : 1 - 0 (0 bit)
access : read-write

AHBErrMsk : AHB Error
bits : 2 - 1 (0 bit)
access : read-write

SetUPMsk : SETUP Phase Done Mask
bits : 3 - 2 (0 bit)
access : read-write

OUTTknEPdisMsk : OUT Token Received when Endpoint Disabled Mask
bits : 4 - 3 (0 bit)
access : read-write

Back2BackSETup : Back-to-Back SETUP Packets Received Mask
bits : 6 - 5 (0 bit)
access : read-write

OutPktErrMsk : OUT Packet Error Mask
bits : 8 - 7 (0 bit)
access : read-write

BnaOutIntrMsk : BNA interrupt Mask
bits : 9 - 8 (0 bit)
access : read-write

BbleErrMsk : Babble Interrupt Mask
bits : 12 - 11 (0 bit)
access : read-write

NAKMsk : NAK Interrupt Mask
bits : 13 - 12 (0 bit)
access : read-write

NYETMsk : NYET Interrupt Mask
bits : 14 - 13 (0 bit)
access : read-write


DAINT

Device All Endpoints Interrupt Register
address_offset : 0x818 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAINT DAINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InEpInt OutEPInt

InEpInt : IN Endpoint Interrupt Bits
bits : 0 - 14 (15 bit)
access : read-only

OutEPInt : OUT Endpoint Interrupt Bits
bits : 16 - 30 (15 bit)
access : read-only


DAINTMSK

Device All Endpoints Interrupt Mask Register
address_offset : 0x81C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAINTMSK DAINTMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InEpMsk OutEpMsk

InEpMsk : IN EP Interrupt Mask Bits
bits : 0 - 14 (15 bit)
access : read-write

OutEpMsk : OUT EP Interrupt Mask Bits
bits : 16 - 30 (15 bit)
access : read-write


DVBUSDIS

Device VBUS Discharge Time Register
address_offset : 0x828 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVBUSDIS DVBUSDIS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DVBUSDis

DVBUSDis : Device Vbus Discharge Time
bits : 0 - 14 (15 bit)
access : read-write


DVBUSPULSE

Device VBUS Pulsing Time Register
address_offset : 0x82C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DVBUSPULSE DVBUSPULSE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DVBUSPulse

DVBUSPulse : Device Vbus Pulsing Time
bits : 0 - 10 (11 bit)
access : read-write


DIEPEMPMSK

Device IN Endpoint FIFO Empty Interrupt Mask Register
address_offset : 0x834 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIEPEMPMSK DIEPEMPMSK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 InEpTxfEmpMsk

InEpTxfEmpMsk : IN EP Tx FIFO Empty Interrupt Mask Bits
bits : 0 - 14 (15 bit)
access : read-write


GUSBCFG

USB Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GUSBCFG GUSBCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TOutCal PHYSel SRPCap HNPCap USBTrdTim OtgI2CSel TxEndDelay ForceHstMode ForceDevMode CTP

TOutCal : FS Timeout Calibration
bits : 0 - 1 (2 bit)
access : read-write

PHYSel : USB 1.1 Full-Speed Serial Transceiver Select
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#1 : value2

USB 1.1 full-speed serial transceiver

End of enumeration elements list.

SRPCap : SRP-Capable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

SRP capability is not enabled.

#1 : value2

SRP capability is enabled.

End of enumeration elements list.

HNPCap : HNP-Capable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : value1

HNP capability is not enabled.

#1 : value2

HNP capability is enabled.

End of enumeration elements list.

USBTrdTim : USB Turnaround Time
bits : 10 - 12 (3 bit)
access : read-write

OtgI2CSel : UTMIFS Interface Select
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : value1

UTMI USB 1.1 Full-Speed interface for OTG signals

End of enumeration elements list.

TxEndDelay : Tx End Delay
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal mode

#1 : value2

Introduce Tx end delay timers

End of enumeration elements list.

ForceHstMode : Force Host Mode
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal Mode

#1 : value2

Force Host Mode

End of enumeration elements list.

ForceDevMode : Force Device Mode
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal Mode

#1 : value2

Force Device Mode

End of enumeration elements list.

CTP : Corrupt Tx packet
bits : 31 - 30 (0 bit)
access : read-write


PCGCCTL

Power and Clock Gating Control Register
address_offset : 0xE00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCGCCTL PCGCCTL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 StopPclk GateHclk

StopPclk : Stop Pclk
bits : 0 - -1 (0 bit)
access : read-write

GateHclk : Gate Hclk
bits : 1 - 0 (0 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.