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DSD

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

MODCFG

FCFGC

FCFGA

IWCTR

BOUNDSEL

RESM

OFFM

RESA

TSTMP

DICFG

CGSYNC

RECTCFG


MODCFG

Modulator Configuration Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MODCFG MODCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVM DWC

DIVM : Divider Factor for Modulator Clock
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

0x0 : value1

fMOD = fCLK / 2

0x1 : value2

fMOD = fCLK / 4

0x2 : value3

fMOD = fCLK / 6

0xF : value4

fMOD = fCLK / 32

End of enumeration elements list.

DWC : Write Control for Divider Factor
bits : 23 - 22 (0 bit)
access : write-only

Enumeration:

#0 : value1

No write access to divider factor

#1 : value2

Bitfield DIVM can be written

End of enumeration elements list.


FCFGC

Filter Configuration Register, Main CIC Filter
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCFGC FCFGC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFMDF CFMC CFEN SRGM CFMSV CFMDCNT

CFMDF : CIC Filter (Main Chain) Decimation Factor
bits : 0 - 6 (7 bit)
access : read-write

CFMC : CIC Filter (Main Chain) Configuration
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

CIC1

#01 : value2

CIC2

#10 : value3

CIC3

#11 : value4

CICF

End of enumeration elements list.

CFEN : CIC Filter Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

CIC filter disabled and bypassed

#1 : value2

Enable CIC filter

End of enumeration elements list.

SRGM : Service Request Generation Main Chain
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#00 : value1

Never, service requests disabled

#11 : value4

Always, for each new result value

End of enumeration elements list.

CFMSV : CIC Filter (Main Chain) Start Value
bits : 16 - 22 (7 bit)
access : read-write

CFMDCNT : CIC Filter (Main Chain) Decimation Counter
bits : 24 - 30 (7 bit)
access : read-only


FCFGA

Filter Configuration Register, Auxiliary Filter
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FCFGA FCFGA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CFADF CFAC SRGA ESEL EGT CFADCNT

CFADF : CIC Filter (Auxiliary) Decimation Factor
bits : 0 - 6 (7 bit)
access : read-write

CFAC : CIC Filter (Auxiliary) Configuration
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

CIC1

#01 : value2

CIC2

#10 : value3

CIC3

#11 : value4

CICF

End of enumeration elements list.

SRGA : Service Request Generation Auxiliary Filter
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#00 : value1

Never, service requests disabled

#01 : value2

Auxiliary filter: As selected by bitfield ESEL

#10 : value3

Alternate source: Capturing of a sign delay value to register CGSYNCx (x = 0 - 3)

End of enumeration elements list.

ESEL : Event Select
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#00 : value1

Always, for each new result value

#01 : value2

If result is inside the boundary band

#10 : value3

If result is outside the boundary band

End of enumeration elements list.

EGT : Event Gating
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : value1

Separate: generate events according to ESEL

#1 : value2

Coupled: generate events only when the integrator is enabled and after the discard phase defined by bitfield NVALDIS

End of enumeration elements list.

CFADCNT : CIC Filter (Auxiliary) Decimation Counter
bits : 24 - 30 (7 bit)
access : read-only


IWCTR

Integration Window Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IWCTR IWCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NVALCNT INTEN REPCNT REPVAL NVALDIS IWS NVALINT

NVALCNT : Number of Values Counted
bits : 0 - 4 (5 bit)
access : read-only

INTEN : Integration Enable
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : value1

Integration stopped. INTEN is cleared at the end of the integration window, i.e. upon the inverse trigger event transition of the external trigger signal.

#1 : value2

Integration enabled. INTEN is set upon the defined trigger event.

End of enumeration elements list.

REPCNT : Integration Cycle Counter
bits : 8 - 10 (3 bit)
access : read-only

REPVAL : Number of Integration Cycles
bits : 12 - 14 (3 bit)
access : read-write

NVALDIS : Number of Values Discarded
bits : 16 - 20 (5 bit)
access : read-write

IWS : Integration Window SIze
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

#0 : value1

Internal control: stop integrator after REPVAL+1 integration cycles

#1 : value2

External control: stop integrator when bit INTEN becomes 0

End of enumeration elements list.

NVALINT : Number of Values Integrated
bits : 24 - 28 (5 bit)
access : read-write


BOUNDSEL

Boundary Select Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOUNDSEL BOUNDSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOUNDARYL BOUNDARYU

BOUNDARYL : Lower Boundary Value for Limit Checking
bits : 0 - 14 (15 bit)
access : read-write

BOUNDARYU : Upper Boundary Value for Limit Checking
bits : 16 - 30 (15 bit)
access : read-write


RESM

Result Register, Main Filter
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESM RESM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT

RESULT : Result of most recent conversion
bits : 0 - 14 (15 bit)
access : read-only


OFFM

Offset Register, Main Filter
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

OFFM OFFM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OFFSET

OFFSET : Offset Value
bits : 0 - 14 (15 bit)
access : read-write


RESA

Result Register, Auxiliary Filter
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESA RESA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT

RESULT : Result of most recent conversion
bits : 0 - 14 (15 bit)
access : read-only


TSTMP

Time-Stamp Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TSTMP TSTMP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT CFMDCNT NVALCNT

RESULT : Result of most recent conversion
bits : 0 - 14 (15 bit)
access : read-only

CFMDCNT : CIC Filter (Main Chain) Decimation Counter
bits : 16 - 22 (7 bit)
access : read-only

NVALCNT : Number of Values Counted
bits : 24 - 28 (5 bit)
access : read-only


DICFG

Demodulator Input Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DICFG DICFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DSRC DSWC ITRMODE TSTRMODE TRSEL TRWC CSRC STROBE SCWC

DSRC : Input Data Source Select
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#000X : value1

Disconnected

#0010 : value2

External, from input A, direct

#0011 : value3

External, from input A, inverted

#0100 : value4

External, from input B, direct

#0101 : value5

External, from input B, inverted

End of enumeration elements list.

DSWC : Write Control for Data Selection
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

No write access to data parameters

#1 : value2

Bitfield DSRC can be written

End of enumeration elements list.

ITRMODE : Integrator Trigger Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

No integration trigger, integrator bypassed

#01 : value2

Trigger event upon a falling edge

#10 : value3

Trigger event upon a rising edge

#11 : value4

No trigger, integrator active all the time

End of enumeration elements list.

TSTRMODE : Timestamp Trigger Mode
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#00 : value1

No timestamp trigger

#01 : value2

Trigger event upon a falling edge

#10 : value3

Trigger event upon a rising edge

#11 : value4

Trigger event upon each edge

End of enumeration elements list.

TRSEL : Trigger Select
bits : 12 - 13 (2 bit)
access : read-write

TRWC : Write Control for Trigger Parameters
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

No write access to trigger parameters

#1 : value2

Bitfields TRSEL, TSTRMODE, ITRMODE can be written

End of enumeration elements list.

CSRC : Sample Clock Source Select
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#0001 : value2

External, from input A

#0010 : value3

External, from input B

#0011 : value4

External, from input C

#0100 : value5

External, from input D

#1111 : value6

Internal clock

End of enumeration elements list.

STROBE : Data Strobe Generatoion Mode
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#0000 : value1

No data strobe

#0001 : value2

Direct clock, a sample trigger is generated at each rising clock edge

#0010 : value3

Direct clock, a sample trigger is generated at each falling clock edge

#0011 : value4

Double data, a sample trigger is generated at each rising and falling clock edge

#0101 : value6

Double clock, a sample trigger is generated at every 2nd rising clock edge

#0110 : value7

Double clock, a sample trigger is generated at every 2nd falling clock edge

End of enumeration elements list.

SCWC : Write Control for Strobe/Clock Selection
bits : 31 - 30 (0 bit)
access : write-only

Enumeration:

#0 : value1

No write access to strobe/clock parameters

#1 : value2

Bitfields STROBE, CSRC can be written

End of enumeration elements list.


CGSYNC

Carrier Generator Synchronization Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CGSYNC CGSYNC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDCOUNT SDCAP SDPOS SDNEG

SDCOUNT : Sign Delay Counter
bits : 0 - 6 (7 bit)
access : read-only

SDCAP : Sign Delay Capture Value
bits : 8 - 14 (7 bit)
access : read-only

SDPOS : Sign Delay Value for Positive Halfwave
bits : 16 - 22 (7 bit)
access : read-write

SDNEG : Sign Delay Value for Negative Halfwave
bits : 24 - 30 (7 bit)
access : read-write


RECTCFG

Rectification Configuration Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RECTCFG RECTCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RFEN SSRC SDVAL SGNCS SGND

RFEN : Rectification Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

No rectification, data not altered

#1 : value2

Data are rectified according to SGND

End of enumeration elements list.

SSRC : Sign Source
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

On-chip carrier generator

#01 : value2

Sign of result of next channel

#10 : value3

External sign signal A

#11 : value4

External sign signal B

End of enumeration elements list.

SDVAL : Valid Flag
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield SDCAP has been updated with a new captured value and has not yet been read

End of enumeration elements list.

SGNCS : Selected Carrier Sign Signal
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Positive values

#1 : value2

Negative values

End of enumeration elements list.

SGND : Sign Signal Delayed
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

Positive values

#1 : value2

Negative values

End of enumeration elements list.



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