\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Bias and suspend configuration
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SUSCFG : Suspend configuration
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
Suspend is ignored.
#001 : value2
CSGy and HRCy units are halted.
#010 : value3
Comparator outputs, HRPWMx.CyO are clamped to passive level and the CSGy units are halted. High resolution channel outputs, HRPWMx.HROUTy0 and HRPWMx.HROUTy1, are clamped to passive state and the HRCy units are halted.
#011 : value4
CSGy units are halted. High resolution channel outputs, HRPWMx.HROUTy0 and HRPWMx.HROUTy1, are clamped to passive state and the HRCy units are halted.
End of enumeration elements list.
HRBE : HRPWM bias enable
bits : 8 - 7 (0 bit)
access : read-write
Global Analog Configuration
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLDLY : Delay of lock detection
bits : 0 - 0 (1 bit)
access : read-write
FUP : Force chargepump up
bits : 2 - 1 (0 bit)
access : read-write
FDN : Force chargepump down
bits : 3 - 2 (0 bit)
access : read-write
SLCP : HRCs chargepump current selection
bits : 6 - 7 (2 bit)
access : read-write
SLIBLDO : HRCs LDO bias current
bits : 9 - 9 (1 bit)
access : read-write
SLIBLF : HRCs loop filter bias current
bits : 11 - 11 (1 bit)
access : read-write
SLVREF : Reference voltage for chargepump and loop filter
bits : 13 - 14 (2 bit)
access : read-write
TRIBIAS : Bias trimming
bits : 16 - 16 (1 bit)
access : read-write
GHREN : Force chargepump down
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
Global high resolution generation is enabled
#1 : value2
Global high resolution generation is disabled
End of enumeration elements list.
Global CSG configuration
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C0PM : CSG0 Power Mode
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
CSG0 unit is powered OFF
#01 : value2
CSG0 unit is set in Low Speed Mode
#11 : value4
CSG0 unit is set in High Speed Mode
End of enumeration elements list.
C1PM : CSG1 Power Mode
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#00 : value1
CSG1 unit is powered OFF
#01 : value2
CSG1 unit is set in Low Speed Mode
#11 : value4
CSG1 unit is set in High Speed Mode
End of enumeration elements list.
C2PM : CSG2 Power Mode
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
CSG2 unit is powered OFF
#01 : value2
CSG2 unit is set in Low Speed Mode
#11 : value4
CSG2 unit is set in High Speed Mode
End of enumeration elements list.
C0CD : CSG0 Clock disable
bits : 16 - 15 (0 bit)
access : read-write
C1CD : CSG1 Clock disable
bits : 17 - 16 (0 bit)
access : read-write
C2CD : CSG2 Clock disable
bits : 18 - 17 (0 bit)
access : read-write
Global CSG run bit set
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SD0R : DAC0 run bit set
bits : 0 - -1 (0 bit)
access : write-only
SC0R : CMP0 run bit set
bits : 1 - 0 (0 bit)
access : write-only
SC0P : CMP0 passive level set
bits : 2 - 1 (0 bit)
access : write-only
SD1R : DAC1 run bit set
bits : 4 - 3 (0 bit)
access : write-only
SC1R : CMP1 run bit set
bits : 5 - 4 (0 bit)
access : write-only
SC1P : CMP1 passive level set
bits : 6 - 5 (0 bit)
access : write-only
SD2R : DAC2 run bit set
bits : 8 - 7 (0 bit)
access : write-only
SC2R : CMP2 run bit set
bits : 9 - 8 (0 bit)
access : write-only
SC2P : CMP2 passive level set
bits : 10 - 9 (0 bit)
access : write-only
Global CSG run bit clear
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CD0R : DAC0 run bit clear
bits : 0 - -1 (0 bit)
access : write-only
CC0R : CMP0 run bit clear
bits : 1 - 0 (0 bit)
access : write-only
CC0P : CMP0 passive level clear
bits : 2 - 1 (0 bit)
access : write-only
CD1R : DAC1 run bit clear
bits : 4 - 3 (0 bit)
access : write-only
CC1R : CMP1 run bit clear
bits : 5 - 4 (0 bit)
access : write-only
CC1P : CMP1 passive level clear
bits : 6 - 5 (0 bit)
access : write-only
CD2R : DAC2 run bit clear
bits : 8 - 7 (0 bit)
access : write-only
CC2R : CMP2 run bit clear
bits : 9 - 8 (0 bit)
access : write-only
CC2P : CMP2 passive level clear
bits : 10 - 9 (0 bit)
access : write-only
Global CSG run bit status
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0RB : DAC0 run bit status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
DAC0 is not running (control logic is disabled)
#1 : value2
DAC0 is running
End of enumeration elements list.
C0RB : CMP0 run bit status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
CMP0 functionality is disabled
#1 : value2
CMP0 functionality is enabled
End of enumeration elements list.
PSLS0 : CMP0 output passive status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
CMP0 output is not clamped
#1 : value2
CMP0 output is clamped
End of enumeration elements list.
D1RB : DAC1 run bit status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
DAC1 is not running (control logic is disabled)
#1 : value2
DAC1 is running
End of enumeration elements list.
C1RB : CMP1 run bit status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : value1
CMP1 functionality is disabled
#1 : value2
CMP1 functionality is enabled
End of enumeration elements list.
PSLS1 : CMP1 output passive status
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
#0 : value1
CMP1 output is not clamped
#1 : value2
CMP1 output is clamped
End of enumeration elements list.
D2RB : DAC2 run bit status
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : value1
DAC2 is not running (control logic is disabled)
#1 : value2
DAC1 is running
End of enumeration elements list.
C2RB : CMP2 run bit status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : value1
CMP2 functionality is disabled
#1 : value2
CMP2 functionality is enabled
End of enumeration elements list.
PSLS2 : CMP2 output passive status
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
#0 : value1
CMP2 output is not clamped
#1 : value2
CMP2 output is clamped
End of enumeration elements list.
Global CSG slope/prescaler control
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S0STR : Slope 0 start
bits : 0 - -1 (0 bit)
access : write-only
S0STP : Slope 0 stop
bits : 1 - 0 (0 bit)
access : write-only
PS0STR : Prescaler 0 start
bits : 2 - 1 (0 bit)
access : write-only
PS0STP : Prescaler 0 stop
bits : 3 - 2 (0 bit)
access : write-only
PS0CLR : Prescaler 0 clear
bits : 4 - 3 (0 bit)
access : write-only
S1STR : Slope 1 start
bits : 8 - 7 (0 bit)
access : write-only
S1STP : Slope 1 stop
bits : 9 - 8 (0 bit)
access : write-only
PS1STR : Prescaler 1 start
bits : 10 - 9 (0 bit)
access : write-only
PS1STP : Prescaler 1 stop
bits : 11 - 10 (0 bit)
access : write-only
PS1CLR : Prescaler 1 clear
bits : 12 - 11 (0 bit)
access : write-only
S2STR : Slope 2 start
bits : 16 - 15 (0 bit)
access : write-only
S2STP : Slope 2 stop
bits : 17 - 16 (0 bit)
access : write-only
PS2STR : Prescaler 2 start
bits : 18 - 17 (0 bit)
access : write-only
PS2STP : Prescaler 2 stop
bits : 19 - 18 (0 bit)
access : write-only
PS2CLR : Prescaler 2 clear
bits : 20 - 19 (0 bit)
access : write-only
Global CSG slope/prescaler status
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
S0RB : DAC0 slope generation status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Slope generation is stopped.
#1 : value2
Slope generation is running.
End of enumeration elements list.
P0RB : CSG0 prescaler status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
Prescaler is stopped. The clock used for the slope generation is halted and therefore the slope is frozen.
#1 : value2
Prescaler is running.
End of enumeration elements list.
S1RB : DAC1 slope generation status
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : value1
Slope generation is stopped.
#1 : value2
Slope generation is running.
End of enumeration elements list.
P1RB : CSG1 prescaler status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : value1
Prescaler is stopped. The clock used for the slope generation is halted and therefore the slope is frozen.
#1 : value2
Prescaler is running.
End of enumeration elements list.
S2RB : DAC2 slope generation status
bits : 16 - 15 (0 bit)
access : read-only
Enumeration:
#0 : value1
Slope generation is stopped.
#1 : value2
Slope generation is running.
End of enumeration elements list.
P2RB : CSG2 prescaler status
bits : 17 - 16 (0 bit)
access : read-only
Enumeration:
#0 : value1
Prescaler is stopped. The clock used for the slope generation is halted and therefore the slope is frozen.
#1 : value2
Prescaler is running.
End of enumeration elements list.
Global CSG shadow/switch trigger
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SES : DAC0 shadow transfer enable set
bits : 0 - -1 (0 bit)
access : write-only
D0SVS : CMP0 inverting input switch request
bits : 1 - 0 (0 bit)
access : write-only
D1SES : DAC1 shadow transfer enable set
bits : 4 - 3 (0 bit)
access : write-only
D1SVS : CMP1 inverting input switch request
bits : 5 - 4 (0 bit)
access : write-only
D2SES : DAC2 shadow transfer enable set
bits : 8 - 7 (0 bit)
access : write-only
D2SVS : CMP2 inverting input switch request
bits : 9 - 8 (0 bit)
access : write-only
Global CSG shadow trigger clear
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0SEC : DAC0 shadow transfer enable clear
bits : 0 - -1 (0 bit)
access : write-only
D1SEC : DAC1 shadow transfer enable clear
bits : 4 - 3 (0 bit)
access : write-only
D2SEC : DAC2 shadow transfer enable clear
bits : 8 - 7 (0 bit)
access : write-only
Global CSG shadow/switch status
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
D0STE : DAC0 shadow transfer enable
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Shadow transfer has been performed.
#1 : value2
Shadow transfer has been requested but is still pending completion.
End of enumeration elements list.
SW0ST : CMP0 inverting input connection status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
Inverting input connected to HRPWMx.C0I[A]
#1 : value2
Inverting input connected to HRPWMx.C0I[B]
End of enumeration elements list.
D1STE : DAC1 shadow transfer enable
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
Shadow transfer has been performed.
#1 : value2
Shadow transfer has been requested but is still pending completion.
End of enumeration elements list.
SW1ST : CMP1 inverting input connection status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : value1
Inverting input connected to HRPWMx.C1I[A]
#1 : value2
Inverting input connected to HRPWMx.C1I[B]
End of enumeration elements list.
D2STE : DAC2 shadow transfer enable
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : value1
Shadow transfer has been performed.
#1 : value2
Shadow transfer has been requested but is still pending completion.
End of enumeration elements list.
SW2ST : CMP2 inverting input connection status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : value1
Inverting input connected to HRPWMx.C2I[A]
#1 : value2
Inverting input connected to HRPWMx.C2I[B]
End of enumeration elements list.
Global HRC configuration
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HRCPM : High resolution channels power mode
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
High resolution generation logic is OFF. It is not possible to generate high resolution signals throughout any of the high resolution channels, HRCy.
#1 : value2
High resolution generation logic is ON. In this mode it is possible to generate a high resolution signal placement with the HRCy subunits.
End of enumeration elements list.
HRC0E : HRC0 high resolution enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRC0 High Resolution Path is disabled. In this mode, is not possible to use the High Resolution Path inside of HRC0 to generate an output PWM signal.
#1 : value2
HRC0 High Resolution Path is enabled. In this mode it is possible to generate a high resolution PWM signal if HRCPM = 1#.
End of enumeration elements list.
HRC1E : HRC1 high resolution channel enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRC1 High Resolution Path is disabled. In this mode, is not possible to use the High Resolution Path inside of HRC1 to generate an output PWM signal.
#1 : value2
HRC1 High Resolution Path is enabled. In this mode it is possible to generate a high resolution PWM signal if HRCPM = 1#.
End of enumeration elements list.
HRC2E : HRC2 high resolution channel enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRC2 High Resolution Path is disabled. In this mode, is not possible to use the High Resolution Path inside of HRC2 to generate an output PWM signal.
#1 : value2
HRC2 High Resolution Path is enabled. In this mode it is possible to generate a high resolution PWM signal if HRCPM = 1#.
End of enumeration elements list.
HRC3E : HRC3 high resolution channel enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRC3 High Resolution Path is disabled. In this mode, is not possible to use the High Resolution Path inside of HRC3 to generate an output PWM signal.
#1 : value2
HRC3 High Resolution Path is enabled. In this mode it is possible to generate a high resolution PWM signal if HRCPM = 1#.
End of enumeration elements list.
CLKC : Clock information control
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#000 : value1
No clock frequency is selected
#001 : value2
Module clock frequency is 180 MHz
#010 : value3
Module clock frequency is 120 MHz
#011 : value4
Module clock frequency is 80 MHz
End of enumeration elements list.
LRC0E : HRC0 low resolution channel enable
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRC0 Low Resolution Path is disabled. In this mode, is not possible to use the Low Resolution Path inside of HRC0 to generate an output PWM signal.
#1 : value2
HRC0 Low Resolution Path is enabled. In this mode it is possible to generate a an output PWM signal via the Low Resolution Path.
End of enumeration elements list.
LRC1E : HRC1 low resolution channel enable
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRC1 Low Resolution Path is disabled. In this mode, is not possible to use the Low Resolution Path inside of HRC1 to generate an output PWM signal.
#1 : value2
HRC1 Low Resolution Path is enabled. In this mode it is possible to generate a an output PWM signal via the Low Resolution Path.
End of enumeration elements list.
LRC2E : HRC2 low resolution channel enable
bits : 22 - 21 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRC2 Low Resolution Path is disabled. In this mode, is not possible to use the Low Resolution Path inside of HRC2 to generate an output PWM signal.
#1 : value2
HRC2 Low Resolution Path is enabled. In this mode it is possible to generate a an output PWM signal via the Low Resolution Path.
End of enumeration elements list.
LRC3E : HRC3 low resolution channel enable
bits : 23 - 22 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRC3 Low Resolution Path is disabled. In this mode, is not possible to use the Low Resolution Path inside of HRC3 to generate an output PWM signal.
#1 : value2
HRC3 Low Resolution Path is enabled. In this mode it is possible to generate a an output PWM signal via the Low Resolution Path.
End of enumeration elements list.
Global HRC shadow trigger set
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H0ES : HRC0 high resolution values shadow transfer Enable Set
bits : 0 - -1 (0 bit)
access : write-only
H0DES : HRC0 dead time value shadow transfer enable set
bits : 1 - 0 (0 bit)
access : write-only
H1ES : HRC1 high resolution values shadow transfer Enable Set
bits : 4 - 3 (0 bit)
access : write-only
H1DES : HRC0 dead time value shadow transfer enable set
bits : 5 - 4 (0 bit)
access : write-only
H2ES : HRC2 high resolution values shadow transfer Enable Set
bits : 8 - 7 (0 bit)
access : write-only
H2DES : HRC0 dead time value shadow transfer enable set
bits : 9 - 8 (0 bit)
access : write-only
H3ES : HRC3 high resolution values shadow transfer Enable Set
bits : 12 - 11 (0 bit)
access : write-only
H3DES : HRC0 dead time value shadow transfer enable set
bits : 13 - 12 (0 bit)
access : write-only
Global HRC shadow trigger clear
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H0EC : HRC0 high resolution values shadow transfer Enable Clear
bits : 0 - -1 (0 bit)
access : write-only
H0DEC : HRC0 dead time value shadow transfer Enable Clear
bits : 1 - 0 (0 bit)
access : write-only
H1EC : HRC1 high resolution values shadow transfer Enable Clear
bits : 4 - 3 (0 bit)
access : write-only
H1DEC : HRC1 dead time value shadow transfer Enable Clear
bits : 5 - 4 (0 bit)
access : write-only
H2CEC : HRC2 high resolution values shadow transfer Enable Clear
bits : 8 - 7 (0 bit)
access : write-only
H2DEC : HRC2 dead time value shadow transfer Enable Clear
bits : 9 - 8 (0 bit)
access : write-only
H3EC : HRC3 high resolution values shadow transfer Enable Clear
bits : 12 - 11 (0 bit)
access : write-only
H3DEC : HRC3 dead time value shadow transfer Enable Clear
bits : 13 - 12 (0 bit)
access : write-only
Global HRC shadow transfer status
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
H0STE : HRC0 high resolution values shadow transfer status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
No shadow transfer pending for HRCyCR1This register holds the value for the rising edge high resolution signal placement. the update of this value should be done via the associated shadow register, . and HRCyCR2This register holds the value for the falling edge high resolution signal placement. the update of this value should be done via the associated shadow register, . values
#1 : value2
Shadow transfer pending for HRCyCR1This register holds the value for the rising edge high resolution signal placement. the update of this value should be done via the associated shadow register, . and HRCyCR2This register holds the value for the falling edge high resolution signal placement. the update of this value should be done via the associated shadow register, . values
End of enumeration elements list.
H0DSTE : HRC0 dead time value shadow transfer status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
No shadow transfer pending for HRCyDCRThis register holds the dead time value that is going to be inserted whenever a rising transition on the output latch is sensed. and HRCyDCFThis register holds the dead time value that is going to be inserted whenever a falling transition on the output latch is sensed. values
#1 : value2
Shadow transfer pending for HRCyDCRThis register holds the dead time value that is going to be inserted whenever a rising transition on the output latch is sensed. and HRCyDCFThis register holds the dead time value that is going to be inserted whenever a falling transition on the output latch is sensed. values
End of enumeration elements list.
H1STE : HRC1 high resolution values shadow transfer status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
No shadow transfer pending for HRCyCR1This register holds the value for the rising edge high resolution signal placement. the update of this value should be done via the associated shadow register, . and HRCyCR2This register holds the value for the falling edge high resolution signal placement. the update of this value should be done via the associated shadow register, . values
#1 : value2
Shadow transfer pending for HRCyCR1This register holds the value for the rising edge high resolution signal placement. the update of this value should be done via the associated shadow register, . and HRCyCR2This register holds the value for the falling edge high resolution signal placement. the update of this value should be done via the associated shadow register, . values
End of enumeration elements list.
H1DSTE : HRC1 dead time value shadow transfer status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : value1
No shadow transfer pending for HRCyDCRThis register holds the dead time value that is going to be inserted whenever a rising transition on the output latch is sensed. and HRCyDCFThis register holds the dead time value that is going to be inserted whenever a falling transition on the output latch is sensed. values
#1 : value2
Shadow transfer pending for HRCyDCRThis register holds the dead time value that is going to be inserted whenever a rising transition on the output latch is sensed. and HRCyDCFThis register holds the dead time value that is going to be inserted whenever a falling transition on the output latch is sensed. values
End of enumeration elements list.
H2STE : HRC2 high resolution values shadow transfer status
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
#0 : value1
No shadow transfer pending for HRCyCR1This register holds the value for the rising edge high resolution signal placement. the update of this value should be done via the associated shadow register, . and HRCyCR2This register holds the value for the falling edge high resolution signal placement. the update of this value should be done via the associated shadow register, . values
#1 : value2
Shadow transfer pending for HRCyCR1This register holds the value for the rising edge high resolution signal placement. the update of this value should be done via the associated shadow register, . and HRCyCR2This register holds the value for the falling edge high resolution signal placement. the update of this value should be done via the associated shadow register, . values
End of enumeration elements list.
H2DSTE : HRC2 dead time value shadow transfer status
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
#0 : value1
No shadow transfer pending for HRCyDCRThis register holds the dead time value that is going to be inserted whenever a rising transition on the output latch is sensed. and HRCyDCFThis register holds the dead time value that is going to be inserted whenever a falling transition on the output latch is sensed. values
#1 : value2
Shadow transfer pending for HRCyDCRThis register holds the dead time value that is going to be inserted whenever a rising transition on the output latch is sensed. and HRCyDCFThis register holds the dead time value that is going to be inserted whenever a falling transition on the output latch is sensed. values
End of enumeration elements list.
H3STE : HRC3 high resolution values shadow transfer status
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
#0 : value1
No shadow transfer pending for HRCyCR1This register holds the value for the rising edge high resolution signal placement. the update of this value should be done via the associated shadow register, . and HRCyCR2This register holds the value for the falling edge high resolution signal placement. the update of this value should be done via the associated shadow register, . values
#1 : value2
Shadow transfer pending for HRCyCR1This register holds the value for the rising edge high resolution signal placement. the update of this value should be done via the associated shadow register, . and HRCyCR2This register holds the value for the falling edge high resolution signal placement. the update of this value should be done via the associated shadow register, . values
End of enumeration elements list.
H3DSTE : HRC3 dead time value shadow transfer status
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
#0 : value1
No shadow transfer pending for HRCyDCRThis register holds the dead time value that is going to be inserted whenever a rising transition on the output latch is sensed. and HRCyDCFThis register holds the dead time value that is going to be inserted whenever a falling transition on the output latch is sensed. values
#1 : value2
Shadow transfer pending for HRCyDCRThis register holds the dead time value that is going to be inserted whenever a rising transition on the output latch is sensed. and HRCyDCFThis register holds the dead time value that is going to be inserted whenever a falling transition on the output latch is sensed. values
End of enumeration elements list.
High Resolution Generation Status
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HRGR : High Resolution Generation Ready
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
High resolution logic is not working
#1 : value2
High resolution logic is working
End of enumeration elements list.
Module identification register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODR : Module Revision
bits : 0 - 6 (7 bit)
access : read-only
MODT : Module Type
bits : 8 - 14 (7 bit)
access : read-only
MODN : Module Number
bits : 16 - 30 (15 bit)
access : read-only
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