\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
HRC mode configuration
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HRM0 : HRCy high resolution mode configuration for source selector 0
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
Rising edge high resolution signal positioning enabled
#01 : value2
Falling edge high resolution signal positioning enabled
#10 : value3
Both edges high resolution signal positioning is enabled
#11 : value4
No high resolution positioning
End of enumeration elements list.
HRM1 : HRCy high resolution mode configuration for source selector 1
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#00 : value1
Rising edge high resolution signal positioning enabled
#01 : value2
Falling edge high resolution signal positioning enabled
#10 : value3
Both edges high resolution signal positioning is enabled
#11 : value4
No high resolution positioning
End of enumeration elements list.
DTE : HRCy dead time enable
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
#0 : value1
Dead time insertion is disabled
#1 : value2
Dead time insertion is enabled
End of enumeration elements list.
TR0E : HRCy trap enable
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap function for HRPWMx.HROUTy0 is disabled
#1 : value2
Trap function for HRPWMx.HROUTy0 is enabled
End of enumeration elements list.
TR1E : HRCy complementary trap enable
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
Trap function for HRPWMx.HROUTy1 is disabled
#1 : value2
Trap function for HRPWMx.HROUTy1 is enabled
End of enumeration elements list.
STC : HRCy shadow transfer configuration
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRCy shadow transfer enable for HRCyCR1This register holds the value for the rising edge high resolution signal placement. the update of this value should be done via the associated shadow register, . and HRCyCR2This register holds the value for the falling edge high resolution signal placement. the update of this value should be done via the associated shadow register, . values is not linked with the specific Capture/Compare Unit timer.
#1 : value2
HRCy shadow transfer enable for HRCyCR1This register holds the value for the rising edge high resolution signal placement. the update of this value should be done via the associated shadow register, . and HRCyCR2This register holds the value for the falling edge high resolution signal placement. the update of this value should be done via the associated shadow register, . values is linked with the specific Capture/Compare Unit timer.
End of enumeration elements list.
DSTC : HRCy dead time shadow transfer configuration
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRCy shadow transfer enable for HRCyDCRThis register holds the dead time value that is going to be inserted whenever a rising transition on the output latch is sensed. and HRCyDCFThis register holds the dead time value that is going to be inserted whenever a falling transition on the output latch is sensed. values is not linked with the specific Capture/Compare Unit timer.
#1 : value2
HRCy shadow transfer enable for HRCyDCRThis register holds the dead time value that is going to be inserted whenever a rising transition on the output latch is sensed. and HRCyDCFThis register holds the dead time value that is going to be inserted whenever a falling transition on the output latch is sensed. values is linked with the specific Capture/Compare Unit timer.
End of enumeration elements list.
OCS0 : HRPWMx.OUTy0 channel selector
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRPWMx.OUTy0 is connected to the latch Q channel
#1 : value2
HRPWMx.OUTy0 is connected to the latch Qn channel
End of enumeration elements list.
OCS1 : HRPWMx.OUTy1 channel selector
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRPWMx.OUTy1 is connected to the latch Qn channel
#1 : value2
HRPWMx.OUTy1 is connected to the latch Q channel
End of enumeration elements list.
DTUS : Dead Time update trigger selector
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
The update of the values is done with the trigger generated by the timers. This is the same trigger that is used to update the HRCyCR1This register holds the value for the rising edge high resolution signal placement. the update of this value should be done via the associated shadow register, . and HRCyCR2This register holds the value for the falling edge high resolution signal placement. the update of this value should be done via the associated shadow register, ..
#1 : value2
The update of the dead time values is done when the dead time counter is not running, independently of the HRCyCR1This register holds the value for the rising edge high resolution signal placement. the update of this value should be done via the associated shadow register, . and HRCyCR2This register holds the value for the falling edge high resolution signal placement. the update of this value should be done via the associated shadow register, . registers.
End of enumeration elements list.
HRC current source for shadow
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ST : Source selector for the shadow transfer
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Shadow transfer signals (shadow transfer trigger and shadow transfer enable) are linked with the timer CC8y connected to the Source Selector 0.
#1 : value2
Shadow transfer signals (shadow transfer trigger and shadow transfer enable) are linked with the timer CC8y connected to the Source Selector 1.
End of enumeration elements list.
HRC dead time rising value
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTRV : Dead time rising value
bits : 0 - 14 (15 bit)
access : read-only
HRC dead time falling value
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DTFV : Dead time falling value
bits : 0 - 14 (15 bit)
access : read-only
HRC rising edge value
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR1 : High resolution rising edge value
bits : 0 - 6 (7 bit)
access : read-only
HRC falling edge value
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CR2 : High resolution falling edge value
bits : 0 - 6 (7 bit)
access : read-only
HRC next source for shadow
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SST : Source selector for the shadow transfer
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Next shadow transfer signals (shadow transfer trigger and shadow transfer enable) are linked with the timer CC8y connected to the Source Selector 0.
#1 : value2
Next shadow transfer signals (shadow transfer trigger and shadow transfer enable) are linked with the timer CC8y connected to the Source Selector 1.
End of enumeration elements list.
HRC shadow dead time rising
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDTRV : Shadow dead time rising value
bits : 0 - 14 (15 bit)
access : read-write
HRC shadow dead time falling
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDTFV : Shadow dead time falling value
bits : 0 - 14 (15 bit)
access : read-write
HRC shadow rising edge value
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCR1 : High resolution falling edge value
bits : 0 - 6 (7 bit)
access : read-write
HRC shadow falling edge value
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SCR2 : High resolution rising edge value
bits : 0 - 6 (7 bit)
access : read-write
HRC output passive level
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PSL0 : HRPWMx.OUTy0 passive level
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRPWMx.OUTy0 output passive level is set to LOW
#1 : value2
HRPWMx.OUTy0 output passive level is set to HIGH
End of enumeration elements list.
PSL1 : HRPWMx.OUTy1 passive level
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
HRPWMx.OUTy1 output passive level is set to LOW
#1 : value2
HRPWMx.OUTy1 output passive level is set to HIGH
End of enumeration elements list.
HRC global control selection
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
C0SS : Source selector 0 comparator set configuration
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
CMP output of CSG0 unit can be used as set source for the output latch
#001 : value2
CMP output of CSG1 unit can be used as set source for the output latch
#010 : value3
CMP output of CSG2 unit can be used as set source for the output latch
End of enumeration elements list.
C0CS : Source selector 0 comparator clear configuration
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#000 : value1
CMP output of CSG0 unit can be used as clear source for the output latch
#001 : value2
CMP output of CSG1 unit can be used as clear source for the output latch
#010 : value3
CMP output of CSG2 unit can be used as clear source for the output latch
End of enumeration elements list.
S0M : Source selector 0 set configuration
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : value1
Set from source selector 0 is controlled via the Capture/Compare Unit timer, CCSTy signal
#01 : value2
Set from source selector 0 is controlled via the CMP output from the CSGy unit. Which unit is being used is configured via the C0SS field.
End of enumeration elements list.
C0M : Source selector 0 clear configuration
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
Clear from source selector 0 is controlled via the Capture/Compare Unit timer, CCSTy signal
#01 : value2
Clear from source selector 0 is controlled via the CMP output from the CSGy unit. Which unit is being used is configured via the C0CS field.
End of enumeration elements list.
S0ES : Source selector 0 set edge configuration
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
Generation of the set signal is disabled
#01 : value2
Set signal is generated on a LOW to HIGH transition of the selected input
#10 : value3
Set signal is generated on a HIGH to LOW transition of the selected input
#11 : value4
Set signal is generated on both transitions of the selected input
End of enumeration elements list.
C0ES : Source selector 0 clear edge configuration
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#00 : value1
Generation of the clear signal is disabled
#01 : value2
Clear signal is generated on a LOW to HIGH transition of the selected input
#10 : value3
Clear signal is generated on a HIGH to LOW transition of the selected input
#11 : value4
Clear signal is generated on both transitions of the selected input
End of enumeration elements list.
C1SS : Source selector 1 comparator set configuration
bits : 16 - 17 (2 bit)
access : read-write
Enumeration:
#000 : value1
CMP output of CSG0 unit can be used as set source for the output latch
#001 : value2
CMP output of CSG2 unit can be used as set source for the output latch
#010 : value3
CMP output of CSG2 unit can be used as set source for the output latch
End of enumeration elements list.
C1CS : Source selector 1 comparator clear configuration
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
#000 : value1
CMP output of CSG0 unit can be used as clear source for the output latch
#001 : value2
CMP output of CSG2 unit can be used as clear source for the output latch
#010 : value3
CMP output of CSG2 unit can be used as clear source for the output latch
End of enumeration elements list.
S1M : Source selector 1 set configuration
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#00 : value1
Set from source selector 1 is controlled via the Capture/Compare Unit timer, CCSTy signal
#01 : value2
Set from source selector 1 is controlled via the CMP output from the CSGy unit. Which unit is being used is configured via the C1SS field.
End of enumeration elements list.
C1M : Source selector 1 clear configuration
bits : 24 - 24 (1 bit)
access : read-write
Enumeration:
#00 : value1
Clear from source selector 1 is controlled via the Capture/Compare Unit timer, CCSTy signal
#01 : value2
Clear from source selector 1 is controlled via the CMP output from the CSGy unit. Which unit is being used is configured via the C1CS field.
End of enumeration elements list.
S1ES : Source selector 1 set edge configuration
bits : 26 - 26 (1 bit)
access : read-write
Enumeration:
#00 : value1
Generation of the set signal is disabled
#01 : value2
Set signal is generated on a LOW to HIGH transition of the selected input
#10 : value3
Set signal is generated on a HIGH to LOW transition of the selected input
#11 : value4
Set signal is generated on both transitions of the selected input
End of enumeration elements list.
C1ES : Source selector 1 clear edge configuration
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#00 : value1
Generation of the clear signal is disabled
#01 : value2
Clear signal is generated on a LOW to HIGH transition of the selected input
#10 : value3
Clear signal is generated on a HIGH to LOW transition of the selected input
#11 : value4
Clear signal is generated on both transitions of the selected input
End of enumeration elements list.
HRC timer selection
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TSEL0 : Source Selector 0 Timer connection
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
Source Selector 0 is connected to Capture/Compare Unit Timer 0 (CCST0 can be used)
#001 : value2
Source Selector 0 is connected to Capture/Compare Unit Timer 1 (CCST1 can be used)
#010 : value3
Source Selector 0 is connected to Capture/Compare Unit Timer 2 (CCST2 can be used)
#011 : value4
Source Selector 0 is connected to Capture/Compare Unit Timer 3 (CCST3 can be used)
End of enumeration elements list.
TSEL1 : Source Selector 1 Timer connection
bits : 3 - 4 (2 bit)
access : read-write
Enumeration:
#000 : value1
Source Selector 1 is connected to Capture/Compare Unit Timer 0 (CCST0 can be used)
#001 : value2
Source Selector 1 is connected to Capture/Compare Unit Timer 1 (CCST1 can be used)
#010 : value3
Source Selector 1 is connected to Capture/Compare Unit Timer 2 (CCST2 can be used)
#011 : value4
Source Selector 1 is connected to Capture/Compare Unit Timer 3 (CCST3 can be used)
End of enumeration elements list.
TS0E : Source selector 0 TRAP enable
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
TRAP signal generated from the Timer connected to Source Selector 0 is disabled.
#1 : value2
TRAP signal generated from the Timer connected to Source Selector 0 is enabled.
End of enumeration elements list.
TS1E : Source selector 1 TRAP enable
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
TRAP signal generated from the Timer connected to Source Selector 1 is disabled.
#1 : value2
TRAP signal generated from the Timer connected to Source Selector 1 is enabled.
End of enumeration elements list.
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