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GPDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x3D40 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RAWTFR

RAWSRCTRAN

TYPE

VERSION

RAWDSTTRAN

RAWERR

STATUSTFR

STATUSBLOCK

STATUSSRCTRAN

STATUSDSTTRAN

STATUSERR

MASKTFR

MASKBLOCK

MASKSRCTRAN

MASKDSTTRAN

MASKERR

CLEARTFR

RAWBLOCK

CLEARBLOCK

CLEARSRCTRAN

CLEARDSTTRAN

CLEARERR

STATUSINT

REQSRCREG

REQDSTREG

SGLREQSRCREG

SGLREQDSTREG

LSTSRCREG

LSTDSTREG

DMACFGREG

CHENREG

ID


RAWTFR

Raw IntTfr Status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAWTFR RAWTFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Raw Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-write

CH1 : Raw Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-write

CH2 : Raw Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-write

CH3 : Raw Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-write

CH4 : Raw Interrupt Status for channel 4
bits : 4 - 3 (0 bit)
access : read-write

CH5 : Raw Interrupt Status for channel 5
bits : 5 - 4 (0 bit)
access : read-write

CH6 : Raw Interrupt Status for channel 6
bits : 6 - 5 (0 bit)
access : read-write

CH7 : Raw Interrupt Status for channel 7
bits : 7 - 6 (0 bit)
access : read-write


RAWSRCTRAN

Raw IntSrcTran Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAWSRCTRAN RAWSRCTRAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Raw Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-write

CH1 : Raw Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-write

CH2 : Raw Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-write

CH3 : Raw Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-write

CH4 : Raw Interrupt Status for channel 4
bits : 4 - 3 (0 bit)
access : read-write

CH5 : Raw Interrupt Status for channel 5
bits : 5 - 4 (0 bit)
access : read-write

CH6 : Raw Interrupt Status for channel 6
bits : 6 - 5 (0 bit)
access : read-write

CH7 : Raw Interrupt Status for channel 7
bits : 7 - 6 (0 bit)
access : read-write


TYPE

GPDMA Component Type
address_offset : 0x138 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TYPE TYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Component Type
bits : 0 - 30 (31 bit)
access : read-only


VERSION

DMA Component Version
address_offset : 0x13C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VERSION VERSION read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Version number of the component
bits : 0 - 30 (31 bit)
access : read-only


RAWDSTTRAN

Raw IntBlock Status
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAWDSTTRAN RAWDSTTRAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Raw Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-write

CH1 : Raw Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-write

CH2 : Raw Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-write

CH3 : Raw Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-write

CH4 : Raw Interrupt Status for channel 4
bits : 4 - 3 (0 bit)
access : read-write

CH5 : Raw Interrupt Status for channel 5
bits : 5 - 4 (0 bit)
access : read-write

CH6 : Raw Interrupt Status for channel 6
bits : 6 - 5 (0 bit)
access : read-write

CH7 : Raw Interrupt Status for channel 7
bits : 7 - 6 (0 bit)
access : read-write


RAWERR

Raw IntErr Status
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAWERR RAWERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Raw Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-write

CH1 : Raw Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-write

CH2 : Raw Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-write

CH3 : Raw Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-write

CH4 : Raw Interrupt Status for channel 4
bits : 4 - 3 (0 bit)
access : read-write

CH5 : Raw Interrupt Status for channel 5
bits : 5 - 4 (0 bit)
access : read-write

CH6 : Raw Interrupt Status for channel 6
bits : 6 - 5 (0 bit)
access : read-write

CH7 : Raw Interrupt Status for channel 7
bits : 7 - 6 (0 bit)
access : read-write


STATUSTFR

IntTfr Status
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUSTFR STATUSTFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-only

CH1 : Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-only

CH2 : Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-only

CH3 : Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-only

CH4 : Interrupt Status for channel 4
bits : 4 - 3 (0 bit)
access : read-only

CH5 : Interrupt Status for channel 5
bits : 5 - 4 (0 bit)
access : read-only

CH6 : Interrupt Status for channel 6
bits : 6 - 5 (0 bit)
access : read-only

CH7 : Interrupt Status for channel 7
bits : 7 - 6 (0 bit)
access : read-only


STATUSBLOCK

IntBlock Status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUSBLOCK STATUSBLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-only

CH1 : Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-only

CH2 : Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-only

CH3 : Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-only

CH4 : Interrupt Status for channel 4
bits : 4 - 3 (0 bit)
access : read-only

CH5 : Interrupt Status for channel 5
bits : 5 - 4 (0 bit)
access : read-only

CH6 : Interrupt Status for channel 6
bits : 6 - 5 (0 bit)
access : read-only

CH7 : Interrupt Status for channel 7
bits : 7 - 6 (0 bit)
access : read-only


STATUSSRCTRAN

IntSrcTran Status
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUSSRCTRAN STATUSSRCTRAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-only

CH1 : Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-only

CH2 : Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-only

CH3 : Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-only

CH4 : Interrupt Status for channel 4
bits : 4 - 3 (0 bit)
access : read-only

CH5 : Interrupt Status for channel 5
bits : 5 - 4 (0 bit)
access : read-only

CH6 : Interrupt Status for channel 6
bits : 6 - 5 (0 bit)
access : read-only

CH7 : Interrupt Status for channel 7
bits : 7 - 6 (0 bit)
access : read-only


STATUSDSTTRAN

IntBlock Status
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUSDSTTRAN STATUSDSTTRAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-only

CH1 : Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-only

CH2 : Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-only

CH3 : Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-only

CH4 : Interrupt Status for channel 4
bits : 4 - 3 (0 bit)
access : read-only

CH5 : Interrupt Status for channel 5
bits : 5 - 4 (0 bit)
access : read-only

CH6 : Interrupt Status for channel 6
bits : 6 - 5 (0 bit)
access : read-only

CH7 : Interrupt Status for channel 7
bits : 7 - 6 (0 bit)
access : read-only


STATUSERR

IntErr Status
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUSERR STATUSERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-only

CH1 : Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-only

CH2 : Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-only

CH3 : Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-only

CH4 : Interrupt Status for channel 4
bits : 4 - 3 (0 bit)
access : read-only

CH5 : Interrupt Status for channel 5
bits : 5 - 4 (0 bit)
access : read-only

CH6 : Interrupt Status for channel 6
bits : 6 - 5 (0 bit)
access : read-only

CH7 : Interrupt Status for channel 7
bits : 7 - 6 (0 bit)
access : read-only


MASKTFR

Mask for Raw IntTfr Status
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASKTFR MASKTFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 WE_CH0 WE_CH1 WE_CH2 WE_CH3 WE_CH4 WE_CH5 WE_CH6 WE_CH7

CH0 : Mask bit for channel 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH1 : Mask bit for channel 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH2 : Mask bit for channel 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH3 : Mask bit for channel 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH4 : Mask bit for channel 4
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH5 : Mask bit for channel 5
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH6 : Mask bit for channel 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH7 : Mask bit for channel 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

WE_CH0 : Write enable for mask bit of channel 0
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH1 : Write enable for mask bit of channel 1
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH2 : Write enable for mask bit of channel 2
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH3 : Write enable for mask bit of channel 3
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH4 : Write enable for mask bit of channel 4
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH5 : Write enable for mask bit of channel 5
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH6 : Write enable for mask bit of channel 6
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH7 : Write enable for mask bit of channel 7
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.


MASKBLOCK

Mask for Raw IntBlock Status
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASKBLOCK MASKBLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 WE_CH0 WE_CH1 WE_CH2 WE_CH3 WE_CH4 WE_CH5 WE_CH6 WE_CH7

CH0 : Mask bit for channel 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH1 : Mask bit for channel 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH2 : Mask bit for channel 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH3 : Mask bit for channel 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH4 : Mask bit for channel 4
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH5 : Mask bit for channel 5
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH6 : Mask bit for channel 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH7 : Mask bit for channel 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

WE_CH0 : Write enable for mask bit of channel 0
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH1 : Write enable for mask bit of channel 1
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH2 : Write enable for mask bit of channel 2
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH3 : Write enable for mask bit of channel 3
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH4 : Write enable for mask bit of channel 4
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH5 : Write enable for mask bit of channel 5
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH6 : Write enable for mask bit of channel 6
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH7 : Write enable for mask bit of channel 7
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.


MASKSRCTRAN

Mask for Raw IntSrcTran Status
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASKSRCTRAN MASKSRCTRAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 WE_CH0 WE_CH1 WE_CH2 WE_CH3 WE_CH4 WE_CH5 WE_CH6 WE_CH7

CH0 : Mask bit for channel 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH1 : Mask bit for channel 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH2 : Mask bit for channel 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH3 : Mask bit for channel 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH4 : Mask bit for channel 4
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH5 : Mask bit for channel 5
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH6 : Mask bit for channel 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH7 : Mask bit for channel 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

WE_CH0 : Write enable for mask bit of channel 0
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH1 : Write enable for mask bit of channel 1
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH2 : Write enable for mask bit of channel 2
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH3 : Write enable for mask bit of channel 3
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH4 : Write enable for mask bit of channel 4
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH5 : Write enable for mask bit of channel 5
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH6 : Write enable for mask bit of channel 6
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH7 : Write enable for mask bit of channel 7
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.


MASKDSTTRAN

Mask for Raw IntBlock Status
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASKDSTTRAN MASKDSTTRAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 WE_CH0 WE_CH1 WE_CH2 WE_CH3 WE_CH4 WE_CH5 WE_CH6 WE_CH7

CH0 : Mask bit for channel 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH1 : Mask bit for channel 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH2 : Mask bit for channel 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH3 : Mask bit for channel 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH4 : Mask bit for channel 4
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH5 : Mask bit for channel 5
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH6 : Mask bit for channel 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH7 : Mask bit for channel 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

WE_CH0 : Write enable for mask bit of channel 0
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH1 : Write enable for mask bit of channel 1
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH2 : Write enable for mask bit of channel 2
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH3 : Write enable for mask bit of channel 3
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH4 : Write enable for mask bit of channel 4
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH5 : Write enable for mask bit of channel 5
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH6 : Write enable for mask bit of channel 6
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH7 : Write enable for mask bit of channel 7
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.


MASKERR

Mask for Raw IntErr Status
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MASKERR MASKERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 WE_CH0 WE_CH1 WE_CH2 WE_CH3 WE_CH4 WE_CH5 WE_CH6 WE_CH7

CH0 : Mask bit for channel 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH1 : Mask bit for channel 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH2 : Mask bit for channel 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH3 : Mask bit for channel 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH4 : Mask bit for channel 4
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH5 : Mask bit for channel 5
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH6 : Mask bit for channel 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

CH7 : Mask bit for channel 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

masked

#1 : value2

unmasked

End of enumeration elements list.

WE_CH0 : Write enable for mask bit of channel 0
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH1 : Write enable for mask bit of channel 1
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH2 : Write enable for mask bit of channel 2
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH3 : Write enable for mask bit of channel 3
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH4 : Write enable for mask bit of channel 4
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH5 : Write enable for mask bit of channel 5
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH6 : Write enable for mask bit of channel 6
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH7 : Write enable for mask bit of channel 7
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.


CLEARTFR

IntTfr Status
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLEARTFR CLEARTFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Clear Interrupt Status and Raw Status for channel 0
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH1 : Clear Interrupt Status and Raw Status for channel 1
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH2 : Clear Interrupt Status and Raw Status for channel 2
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH3 : Clear Interrupt Status and Raw Status for channel 3
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH4 : Clear Interrupt Status and Raw Status for channel 4
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH5 : Clear Interrupt Status and Raw Status for channel 5
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH6 : Clear Interrupt Status and Raw Status for channel 6
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH7 : Clear Interrupt Status and Raw Status for channel 7
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.


RAWBLOCK

Raw IntBlock Status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RAWBLOCK RAWBLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Raw Interrupt Status for channel 0
bits : 0 - -1 (0 bit)
access : read-write

CH1 : Raw Interrupt Status for channel 1
bits : 1 - 0 (0 bit)
access : read-write

CH2 : Raw Interrupt Status for channel 2
bits : 2 - 1 (0 bit)
access : read-write

CH3 : Raw Interrupt Status for channel 3
bits : 3 - 2 (0 bit)
access : read-write

CH4 : Raw Interrupt Status for channel 4
bits : 4 - 3 (0 bit)
access : read-write

CH5 : Raw Interrupt Status for channel 5
bits : 5 - 4 (0 bit)
access : read-write

CH6 : Raw Interrupt Status for channel 6
bits : 6 - 5 (0 bit)
access : read-write

CH7 : Raw Interrupt Status for channel 7
bits : 7 - 6 (0 bit)
access : read-write


CLEARBLOCK

IntBlock Status
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLEARBLOCK CLEARBLOCK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Clear Interrupt Status and Raw Status for channel 0
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH1 : Clear Interrupt Status and Raw Status for channel 1
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH2 : Clear Interrupt Status and Raw Status for channel 2
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH3 : Clear Interrupt Status and Raw Status for channel 3
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH4 : Clear Interrupt Status and Raw Status for channel 4
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH5 : Clear Interrupt Status and Raw Status for channel 5
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH6 : Clear Interrupt Status and Raw Status for channel 6
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH7 : Clear Interrupt Status and Raw Status for channel 7
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.


CLEARSRCTRAN

IntSrcTran Status
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLEARSRCTRAN CLEARSRCTRAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Clear Interrupt Status and Raw Status for channel 0
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH1 : Clear Interrupt Status and Raw Status for channel 1
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH2 : Clear Interrupt Status and Raw Status for channel 2
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH3 : Clear Interrupt Status and Raw Status for channel 3
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH4 : Clear Interrupt Status and Raw Status for channel 4
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH5 : Clear Interrupt Status and Raw Status for channel 5
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH6 : Clear Interrupt Status and Raw Status for channel 6
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH7 : Clear Interrupt Status and Raw Status for channel 7
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.


CLEARDSTTRAN

IntBlock Status
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLEARDSTTRAN CLEARDSTTRAN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Clear Interrupt Status and Raw Status for channel 0
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH1 : Clear Interrupt Status and Raw Status for channel 1
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH2 : Clear Interrupt Status and Raw Status for channel 2
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH3 : Clear Interrupt Status and Raw Status for channel 3
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH4 : Clear Interrupt Status and Raw Status for channel 4
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH5 : Clear Interrupt Status and Raw Status for channel 5
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH6 : Clear Interrupt Status and Raw Status for channel 6
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH7 : Clear Interrupt Status and Raw Status for channel 7
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.


CLEARERR

IntErr Status
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CLEARERR CLEARERR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

CH0 : Clear Interrupt Status and Raw Status for channel 0
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH1 : Clear Interrupt Status and Raw Status for channel 1
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH2 : Clear Interrupt Status and Raw Status for channel 2
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH3 : Clear Interrupt Status and Raw Status for channel 3
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH4 : Clear Interrupt Status and Raw Status for channel 4
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH5 : Clear Interrupt Status and Raw Status for channel 5
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH6 : Clear Interrupt Status and Raw Status for channel 6
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.

CH7 : Clear Interrupt Status and Raw Status for channel 7
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

clear status

End of enumeration elements list.


STATUSINT

Combined Interrupt Status Register
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STATUSINT STATUSINT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TFR BLOCK SRCT DSTT ERR

TFR : OR of the contents of STATUSTFR register
bits : 0 - -1 (0 bit)
access : read-only

BLOCK : OR of the contents of STATUSBLOCK register
bits : 1 - 0 (0 bit)
access : read-only

SRCT : OR of the contents of STATUSSRCTRAN register
bits : 2 - 1 (0 bit)
access : read-only

DSTT : OR of the contents of STATUSDSTTRAN register
bits : 3 - 2 (0 bit)
access : read-only

ERR : OR of the contents of STATUSERR register
bits : 4 - 3 (0 bit)
access : read-only


REQSRCREG

Source Software Transaction Request Register
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REQSRCREG REQSRCREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 WE_CH0 WE_CH1 WE_CH2 WE_CH3 WE_CH4 WE_CH5 WE_CH6 WE_CH7

CH0 : Source request for channel 0
bits : 0 - -1 (0 bit)
access : read-write

CH1 : Source request for channel 1
bits : 1 - 0 (0 bit)
access : read-write

CH2 : Source request for channel 2
bits : 2 - 1 (0 bit)
access : read-write

CH3 : Source request for channel 3
bits : 3 - 2 (0 bit)
access : read-write

CH4 : Source request for channel 4
bits : 4 - 3 (0 bit)
access : read-write

CH5 : Source request for channel 5
bits : 5 - 4 (0 bit)
access : read-write

CH6 : Source request for channel 6
bits : 6 - 5 (0 bit)
access : read-write

CH7 : Source request for channel 7
bits : 7 - 6 (0 bit)
access : read-write

WE_CH0 : Source request write enable for channel 0
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH1 : Source request write enable for channel 1
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH2 : Source request write enable for channel 2
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH3 : Source request write enable for channel 3
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH4 : Source request write enable for channel 4
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH5 : Source request write enable for channel 5
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH6 : Source request write enable for channel 6
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH7 : Source request write enable for channel 7
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.


REQDSTREG

Destination Software Transaction Request Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REQDSTREG REQDSTREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 WE_CH0 WE_CH1 WE_CH2 WE_CH3 WE_CH4 WE_CH5 WE_CH6 WE_CH7

CH0 : Source request for channel 0
bits : 0 - -1 (0 bit)
access : read-write

CH1 : Source request for channel 1
bits : 1 - 0 (0 bit)
access : read-write

CH2 : Source request for channel 2
bits : 2 - 1 (0 bit)
access : read-write

CH3 : Source request for channel 3
bits : 3 - 2 (0 bit)
access : read-write

CH4 : Source request for channel 4
bits : 4 - 3 (0 bit)
access : read-write

CH5 : Source request for channel 5
bits : 5 - 4 (0 bit)
access : read-write

CH6 : Source request for channel 6
bits : 6 - 5 (0 bit)
access : read-write

CH7 : Source request for channel 7
bits : 7 - 6 (0 bit)
access : read-write

WE_CH0 : Source request write enable for channel 0
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH1 : Source request write enable for channel 1
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH2 : Source request write enable for channel 2
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH3 : Source request write enable for channel 3
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH4 : Source request write enable for channel 4
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH5 : Source request write enable for channel 5
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH6 : Source request write enable for channel 6
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH7 : Source request write enable for channel 7
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.


SGLREQSRCREG

Single Source Transaction Request Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SGLREQSRCREG SGLREQSRCREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 WE_CH0 WE_CH1 WE_CH2 WE_CH3 WE_CH4 WE_CH5 WE_CH6 WE_CH7

CH0 : Source request for channel 0
bits : 0 - -1 (0 bit)
access : read-write

CH1 : Source request for channel 1
bits : 1 - 0 (0 bit)
access : read-write

CH2 : Source request for channel 2
bits : 2 - 1 (0 bit)
access : read-write

CH3 : Source request for channel 3
bits : 3 - 2 (0 bit)
access : read-write

CH4 : Source request for channel 4
bits : 4 - 3 (0 bit)
access : read-write

CH5 : Source request for channel 5
bits : 5 - 4 (0 bit)
access : read-write

CH6 : Source request for channel 6
bits : 6 - 5 (0 bit)
access : read-write

CH7 : Source request for channel 7
bits : 7 - 6 (0 bit)
access : read-write

WE_CH0 : Source request write enable for channel 0
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH1 : Source request write enable for channel 1
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH2 : Source request write enable for channel 2
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH3 : Source request write enable for channel 3
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH4 : Source request write enable for channel 4
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH5 : Source request write enable for channel 5
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH6 : Source request write enable for channel 6
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH7 : Source request write enable for channel 7
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.


SGLREQDSTREG

Single Destination Transaction Request Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SGLREQDSTREG SGLREQDSTREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 WE_CH0 WE_CH1 WE_CH2 WE_CH3 WE_CH4 WE_CH5 WE_CH6 WE_CH7

CH0 : Source request for channel 0
bits : 0 - -1 (0 bit)
access : read-write

CH1 : Source request for channel 1
bits : 1 - 0 (0 bit)
access : read-write

CH2 : Source request for channel 2
bits : 2 - 1 (0 bit)
access : read-write

CH3 : Source request for channel 3
bits : 3 - 2 (0 bit)
access : read-write

CH4 : Source request for channel 4
bits : 4 - 3 (0 bit)
access : read-write

CH5 : Source request for channel 5
bits : 5 - 4 (0 bit)
access : read-write

CH6 : Source request for channel 6
bits : 6 - 5 (0 bit)
access : read-write

CH7 : Source request for channel 7
bits : 7 - 6 (0 bit)
access : read-write

WE_CH0 : Source request write enable for channel 0
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH1 : Source request write enable for channel 1
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH2 : Source request write enable for channel 2
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH3 : Source request write enable for channel 3
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH4 : Source request write enable for channel 4
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH5 : Source request write enable for channel 5
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH6 : Source request write enable for channel 6
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH7 : Source request write enable for channel 7
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.


LSTSRCREG

Last Source Transaction Request Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LSTSRCREG LSTSRCREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 WE_CH0 WE_CH1 WE_CH2 WE_CH3 WE_CH4 WE_CH5 WE_CH6 WE_CH7

CH0 : Source last request for channel 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH1 : Source last request for channel 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH2 : Source last request for channel 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH3 : Source last request for channel 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH4 : Source last request for channel 4
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH5 : Source last request for channel 5
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH6 : Source last request for channel 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH7 : Source last request for channel 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

WE_CH0 : Source last transaction request write enable for channel 0
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH1 : Source last transaction request write enable for channel 1
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH2 : Source last transaction request write enable for channel 2
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH3 : Source last transaction request write enable for channel 3
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH4 : Source last transaction request write enable for channel 4
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH5 : Source last transaction request write enable for channel 5
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH6 : Source last transaction request write enable for channel 6
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH7 : Source last transaction request write enable for channel 7
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.


LSTDSTREG

Last Destination Transaction Request Register
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LSTDSTREG LSTDSTREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 WE_CH0 WE_CH1 WE_CH2 WE_CH3 WE_CH4 WE_CH5 WE_CH6 WE_CH7

CH0 : Destination last request for channel 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH1 : Destination last request for channel 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH2 : Destination last request for channel 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH3 : Destination last request for channel 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH4 : Destination last request for channel 4
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH5 : Destination last request for channel 5
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH6 : Destination last request for channel 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

CH7 : Destination last request for channel 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not last transaction in current block

#1 : value2

Last transaction in current block

End of enumeration elements list.

WE_CH0 : Destination last transaction request write enable for channel 0
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH1 : Destination last transaction request write enable for channel 1
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH2 : Destination last transaction request write enable for channel 2
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH3 : Destination last transaction request write enable for channel 3
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH4 : Destination last transaction request write enable for channel 4
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH5 : Destination last transaction request write enable for channel 5
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH6 : Destination last transaction request write enable for channel 6
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.

WE_CH7 : Destination last transaction request write enable for channel 7
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

write disabled

#1 : value2

write enabled

End of enumeration elements list.


DMACFGREG

GPDMA Configuration Register
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DMACFGREG DMACFGREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_EN

DMA_EN : GPDMA Enable bit.
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

GPDMA Disabled

#1 : value2

GPDMA Enabled.

End of enumeration elements list.


CHENREG

GPDMA Channel Enable Register
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHENREG CHENREG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH WE_CH

CH : Enables/Disables the channel
bits : 0 - 6 (7 bit)
access : read-write

Enumeration:

#0 : value1

Disable the Channel

#1 : value2

Enable the Channel

End of enumeration elements list.

WE_CH : Channel enable write enable
bits : 8 - 14 (7 bit)
access : write-only


ID

GPDMA0 ID Register
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ID ID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Hardcoded GPDMA Peripheral ID
bits : 0 - 30 (31 bit)
access : read-only



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