Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Clock Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBCST : USB Clock Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Clock disabled
#1 : value2
Clock enabled
End of enumeration elements list.
MMCCST : MMC Clock Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
Clock disabled
#1 : value2
Clock enabled
End of enumeration elements list.
ETH0CST : Ethernet Clock Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Clock disabled
#1 : value2
Clock enabled
End of enumeration elements list.
EBUCST : EBU Clock Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
Clock disabled
#1 : value2
Clock enabled
End of enumeration elements list.
CCUCST : CCU Clock Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
#0 : value1
Clock disabled
#1 : value2
Clock enabled
End of enumeration elements list.
WDTCST : WDT Clock Status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
#0 : value1
Clock disabled
#1 : value2
Clock enabled
End of enumeration elements list.
CPU Clock Control Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CPUDIV : CPU Clock Divider Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
fCPU = fSYS
#1 : value2
fCPU = fSYS / 2
End of enumeration elements list.
Peripheral Bus Clock Control Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBDIV : PB Clock Divider Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
fPERIPH = fCPU
#1 : value2
fPERIPH = fCPU / 2
End of enumeration elements list.
USB Clock Control Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBDIV : USB Clock Divider Value
bits : 0 - 1 (2 bit)
access : read-write
USBSEL : USB Clock Selection Value
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
USB PLL Clock
#1 : value2
PLL Clock
End of enumeration elements list.
EBU Clock Control Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EBUDIV : EBU Clock Divider Value
bits : 0 - 4 (5 bit)
access : read-write
CCU Clock Control Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCUDIV : CCU Clock Divider Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
fCCU = fSYS
#1 : value2
fCCU = fSYS / 2
End of enumeration elements list.
WDT Clock Control Register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTDIV : WDT Clock Divider Value
bits : 0 - 6 (7 bit)
access : read-write
WDTSEL : WDT Clock Selection Value
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : value1
fOFI clock
#01 : value2
fSTDBY clock
#10 : value3
fPLL clock
End of enumeration elements list.
External Clock Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECKSEL : External Clock Selection Value
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
fSYS clock
#10 : value3
fUSB clock
#11 : value4
fPLL clock divided according to ECKDIV bit field configuration
End of enumeration elements list.
ECKDIV : External Clock Divider Value
bits : 16 - 23 (8 bit)
access : read-write
Sleep Control Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSSEL : System Clock Selection Value
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
fOFI clock
#1 : value2
fPLL clock
End of enumeration elements list.
USBCR : USB Clock Control
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
MMCCR : MMC Clock Control
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
ETH0CR : Ethernet Clock Control
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
EBUCR : EBU Clock Control
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
CCUCR : CCU Clock Control
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
WDTCR : WDT Clock Control
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
Deep Sleep Control Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSSEL : System Clock Selection Value
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#0 : value1
fOFI clock
#1 : value2
fPLL clock
End of enumeration elements list.
FPDN : Flash Power Down
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#1 : value1
Flash power down module
#0 : value2
No effect
End of enumeration elements list.
PLLPDN : PLL Power Down
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#1 : value1
Switch off main PLL
#0 : value2
No effect
End of enumeration elements list.
VCOPDN : VCO Power Down
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#1 : value1
Switch off VCO of main PLL
#0 : value2
No effect
End of enumeration elements list.
USBCR : USB Clock Control
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
MMCCR : MMC Clock Control
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
ETH0CR : Ethernet Clock Control
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
EBUCR : EBU Clock Control
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
CCUCR : CCU Clock Control
bits : 20 - 19 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
WDTCR : WDT Clock Control
bits : 21 - 20 (0 bit)
access : read-write
Enumeration:
#0 : value1
Disable
#1 : value2
Enable
End of enumeration elements list.
CLK Set Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBCEN : USB Clock Enable
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Enable
End of enumeration elements list.
MMCCEN : MMC Clock Enable
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Enable
End of enumeration elements list.
ETH0CEN : Ethernet Clock Enable
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Enable
End of enumeration elements list.
EBUCEN : EBU Clock Enable
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Enable
End of enumeration elements list.
CCUCEN : CCU Clock Enable
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Enable
End of enumeration elements list.
WDTCEN : WDT Clock Enable
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Enable
End of enumeration elements list.
CLK Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
USBCDI : USB Clock Disable
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Disable clock
End of enumeration elements list.
MMCCDI : MMC Clock Disable
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Disable clock
End of enumeration elements list.
ETH0CDI : Ethernet Clock Disable
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Disable clock
End of enumeration elements list.
EBUCDI : EBU Clock Disable
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Disable clock
End of enumeration elements list.
CCUCDI : CCU Clock Disable
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Disable clock
End of enumeration elements list.
WDTCDI : WDT Clock Disable
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
#0 : value1
No effect
#1 : value2
Disable clock
End of enumeration elements list.
System Clock Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSDIV : System Clock Division Value
bits : 0 - 6 (7 bit)
access : read-write
SYSSEL : System Clock Selection Value
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
fOFI clock
#1 : value2
fPLL clock
End of enumeration elements list.
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