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VADC

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected

Registers

QCTRL0

QMR0

CHCTR[6]

QSR0

Q0R0

QINR0

QBUR0

RESD[3]

RCR[5]

ASCTRL

RES[4]

ASMR

CHCTR[7]

ASSEL

ASPND

ICLASS[0]

RCR[6]

RESD[4]

RES[5]

RCR[7]

CEFLAG

REFLAG

RES[6]

SEFLAG

RESD[5]

CEFCLR

REFCLR

SEFCLR

RCR[8]

CEVNP0

REVNP0

REVNP1

RES[7]

SEVNP

RCR[9]

RESD[6]

SRACT

ICLASS[1]

RES[8]

RCR[10]

EMUXCTR

VFR

RESD[7]

RCR[11]

RES[9]

RESD[8]

RCR[12]

RES[10]

RCR[13]

RESD[9]

RES[11]

RCR[14]

RESD[10]

RES[12]

RCR[15]

RES[13]

RESD[11]

RES[14]

RESD[12]

RES[15]

RESD[13]

RESD[14]

RESD[15]

CHCTR[0]

RCR[0]

RES[0]

CHCTR[1]

RESD[0]

RCR[1]

ARBCFG

CHCTR[2]

ARBPR

CHASS

RES[1]

RCR[2]

CHCTR[3]

RESD[1]

ALIAS

BOUND

SYNCTR

RES[2]

CHCTR[4]

BFL

RCR[3]

RESD[2]

CHCTR[5]

RES[3]

RCR[4]


QCTRL0

Queue 0 Source Control Register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QCTRL0 QCTRL0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTSEL XTLVL XTMODE XTWC GTSEL GTLVL GTWC TMEN TMWC

XTSEL : External Trigger Input Selection
bits : 8 - 10 (3 bit)
access : read-write

XTLVL : External Trigger Level
bits : 12 - 11 (0 bit)
access : read-only

XTMODE : Trigger Operating Mode
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#00 : value1

No external trigger

#01 : value2

Trigger event upon a falling edge

#10 : value3

Trigger event upon a rising edge

#11 : value4

Trigger event upon any edge

End of enumeration elements list.

XTWC : Write Control for Trigger Configuration
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

No write access to trigger configuration

#1 : value2

Bitfields XTMODE and XTSEL can be written

End of enumeration elements list.

GTSEL : Gate Input Selection
bits : 16 - 18 (3 bit)
access : read-write

GTLVL : Gate Input Level
bits : 20 - 19 (0 bit)
access : read-only

GTWC : Write Control for Gate Configuration
bits : 23 - 22 (0 bit)
access : write-only

Enumeration:

#0 : value1

No write access to gate configuration

#1 : value2

Bitfield GTSEL can be written

End of enumeration elements list.

TMEN : Timer Mode Enable
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : value1

No timer mode: standard gating mechanism can be used

#1 : value2

Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled

End of enumeration elements list.

TMWC : Write Control for Timer Mode
bits : 31 - 30 (0 bit)
access : write-only

Enumeration:

#0 : value1

No write access to timer mode

#1 : value2

Bitfield TMEN can be written

End of enumeration elements list.


QMR0

Queue 0 Mode Register
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QMR0 QMR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENGT ENTR CLRV TREV FLUSH CEV RPTDIS

ENGT : Enable Gate
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

No conversion requests are issued

#01 : value2

Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register

#10 : value3

Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 1

#11 : value4

Conversion requests are issued if a valid conversion request is pending in the queue 0 register or in the backup register and REQGTx = 0

End of enumeration elements list.

ENTR : Enable External Trigger
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

External trigger disabled

#1 : value2

The selected edge at the selected trigger input signal REQTR generates the trigger event

End of enumeration elements list.

CLRV : Clear Valid Bit
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

The next pending valid queue entry in the sequence and the event flag EV are cleared. If there is a valid entry in the queue backup register (QBUR.V = 1), this entry is cleared, otherwise the entry in queue register 0 is cleared.

End of enumeration elements list.

TREV : Trigger Event
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Generate a trigger event by software

End of enumeration elements list.

FLUSH : Flush Queue
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear all queue entries (including backup stage) and the event flag EV. The queue contains no more valid entry.

End of enumeration elements list.

CEV : Clear Event Flag
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear bit EV

End of enumeration elements list.

RPTDIS : Repeat Disable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : value1

A cancelled conversion is repeated

#1 : value2

A cancelled conversion is discarded

End of enumeration elements list.


CHCTR[6]

Channel Ctrl. Reg.
address_offset : 0x1054 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTR[6] CHCTR[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICLSEL BNDSELL BNDSELU CHEVMODE SYNC REFSEL RESREG RESTBS RESPOS BWDCH BWDEN

ICLSEL : Input Class Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific class 0

#01 : value2

Use group-specific class 1

#10 : value3

Use global class 0

#11 : value4

Use global class 1

End of enumeration elements list.

BNDSELL : Lower Boundary Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

BNDSELU : Upper Boundary Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

CHEVMODE : Channel Event Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Never

#01 : value2

NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.)

#10 : value3

NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.)

#11 : value4

NCM: Always (ignore band) FCM: If result switches to either level

End of enumeration elements list.

SYNC : Synchronization Request
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

No synchroniz. request, standalone operation

#1 : value2

Request a synchronized conversion of this channel (only taken into account for a master)

End of enumeration elements list.

REFSEL : Reference Input Selection
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Standard reference input VAREF

#1 : value2

Alternate reference input from CH0

End of enumeration elements list.

RESREG : Result Register
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Store result in group result register GxRES0

#1111 : value2

Store result in group result register GxRES15

End of enumeration elements list.

RESTBS : Result Target for Background Source
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results in the selected group result register

#1 : value2

Store results in the global result register

End of enumeration elements list.

RESPOS : Result Position
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results left-aligned

#1 : value2

Store results right-aligned

End of enumeration elements list.

BWDCH : Broken Wire Detection Channel
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#00 : value1

Select VAGND

#01 : value2

Select VAREF

End of enumeration elements list.

BWDEN : Broken Wire Detection Enable
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal operation

#1 : value2

Additional preparation phase is enabled

End of enumeration elements list.


QSR0

Queue 0 Status Register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QSR0 QSR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FILL EMPTY REQGT EV

FILL : Filling Level for Queue 2
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

#0000 : value1

There is 1 ( if EMPTY = 0) or no (if EMPTY = 1) valid entry in the queue

#0001 : value2

There are 2 valid entries in the queue

#0010 : value3

There are 3 valid entries in the queue

#0111 : value4

There are 8 valid entries in the queue

End of enumeration elements list.

EMPTY : Queue Empty
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : value1

There are valid entries in the queue (see FILL)

#1 : value2

No valid entries (queue is empty)

End of enumeration elements list.

REQGT : Request Gate Level
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : value1

The gate input is low

#1 : value2

The gate input is high

End of enumeration elements list.

EV : Event Detected
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

No trigger event

#1 : value2

A trigger event has been detected

End of enumeration elements list.


Q0R0

Queue 0 Register 0
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

Q0R0 Q0R0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQCHNR RF ENSI EXTR V

REQCHNR : Request Channel Number
bits : 0 - 3 (4 bit)
access : read-only

RF : Refill
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : value1

The request is discarded after the conversion start.

#1 : value2

The request is automatically refilled into the queue after the conversion start.

End of enumeration elements list.

ENSI : Enable Source Interrupt
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : value1

No request source interrupt

#1 : value2

A request source event interrupt is generated upon a request source event (related conversion is finished)

End of enumeration elements list.

EXTR : External Trigger
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : value1

A valid queue entry immediately leads to a conversion request

#1 : value2

The request handler waits for a trigger event

End of enumeration elements list.

V : Request Channel Number Valid
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

No valid queue entry

#1 : value2

The queue entry is valid and leads to a conversion request

End of enumeration elements list.


QINR0

Queue 0 Input Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

QINR0 QINR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQCHNR RF ENSI EXTR

REQCHNR : Request Channel Number
bits : 0 - 3 (4 bit)
access : write-only

RF : Refill
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

No refill: this queue entry is converted once and then invalidated

#1 : value2

Automatic refill: this queue entry is automatically reloaded into QINRx when the related conversion is started

End of enumeration elements list.

ENSI : Enable Source Interrupt
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

No request source interrupt

#1 : value2

A request source event interrupt is generated upon a request source event (related conversion is finished)

End of enumeration elements list.

EXTR : External Trigger
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

A valid queue entry immediately leads to a conversion request.

#1 : value2

A valid queue entry waits for a trigger event to occur before issuing a conversion request.

End of enumeration elements list.


QBUR0

Queue 0 Backup Register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
alternate_register : QINR0
reset_Mask : 0x0

QBUR0 QBUR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REQCHNR RF ENSI EXTR V

REQCHNR : Request Channel Number
bits : 0 - 3 (4 bit)
access : read-only

RF : Refill
bits : 5 - 4 (0 bit)
access : read-only

ENSI : Enable Source Interrupt
bits : 6 - 5 (0 bit)
access : read-only

EXTR : External Trigger
bits : 7 - 6 (0 bit)
access : read-only

V : Request Channel Number Valid
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

Backup register not valid

#1 : value2

Backup register contains a valid entry. This will be requested before a valid entry in queue register 0 (stage 0) will be requested.

End of enumeration elements list.


RESD[3]

Result Register, Debug
address_offset : 0x1198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[3] RESD[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RCR[5]

Result Control Register
address_offset : 0x11BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[5] RCR[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


ASCTRL

Autoscan Source Control Register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASCTRL ASCTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 XTSEL XTLVL XTMODE XTWC GTSEL GTLVL GTWC TMEN TMWC

XTSEL : External Trigger Input Selection
bits : 8 - 10 (3 bit)
access : read-write

XTLVL : External Trigger Level
bits : 12 - 11 (0 bit)
access : read-only

XTMODE : Trigger Operating Mode
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#00 : value1

No external trigger

#01 : value2

Trigger event upon a falling edge

#10 : value3

Trigger event upon a rising edge

#11 : value4

Trigger event upon any edge

End of enumeration elements list.

XTWC : Write Control for Trigger Configuration
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

No write access to trigger configuration

#1 : value2

Bitfields XTMODE and XTSEL can be written

End of enumeration elements list.

GTSEL : Gate Input Selection
bits : 16 - 18 (3 bit)
access : read-write

GTLVL : Gate Input Level
bits : 20 - 19 (0 bit)
access : read-only

GTWC : Write Control for Gate Configuration
bits : 23 - 22 (0 bit)
access : write-only

Enumeration:

#0 : value1

No write access to gate configuration

#1 : value2

Bitfield GTSEL can be written

End of enumeration elements list.

TMEN : Timer Mode Enable
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : value1

No timer mode: standard gating mechanism can be used

#1 : value2

Timer mode for equidistant sampling enabled: standard gating mechanism must be disabled

End of enumeration elements list.

TMWC : Write Control for Timer Mode
bits : 31 - 30 (0 bit)
access : write-only

Enumeration:

#0 : value1

No write access to timer mode

#1 : value2

Bitfield TMEN can be written

End of enumeration elements list.


RES[4]

Result Register
address_offset : 0x1228 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[4] RES[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


ASMR

Autoscan Source Mode Register
address_offset : 0x124 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASMR ASMR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENGT ENTR ENSI SCAN LDM REQGT CLRPND LDEV RPTDIS

ENGT : Enable Gate
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

No conversion requests are issued

#01 : value2

Conversion requests are issued if at least one pending bit is set

#10 : value3

Conversion requests are issued if at least one pending bit is set and REQGTx = 1.

#11 : value4

Conversion requests are issued if at least one pending bit is set and REQGTx = 0.

End of enumeration elements list.

ENTR : Enable External Trigger
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

External trigger disabled

#1 : value2

The selected edge at the selected trigger input signal REQTR generates the load event

End of enumeration elements list.

ENSI : Enable Source Interrupt
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

No request source interrupt

#1 : value2

A request source interrupt is generated upon a request source event (last pending conversion is finished)

End of enumeration elements list.

SCAN : Autoscan Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

No autoscan

#1 : value2

Autoscan functionality enabled: a request source event automatically generates a load event

End of enumeration elements list.

LDM : Autoscan Source Load Event Mode
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode: Copy all bits from the select registers to the pending registers upon a load event

#1 : value2

Combine mode: Set all pending bits that are set in the select registers upon a load event (logic OR)

End of enumeration elements list.

REQGT : Request Gate Level
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : value1

The gate input is low

#1 : value2

The gate input is high

End of enumeration elements list.

CLRPND : Clear Pending Bits
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

The bits in register GxASPNDx are cleared

End of enumeration elements list.

LDEV : Generate Load Event
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

A load event is generated

End of enumeration elements list.

RPTDIS : Repeat Disable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : value1

A cancelled conversion is repeated

#1 : value2

A cancelled conversion is discarded

End of enumeration elements list.


CHCTR[7]

Channel Ctrl. Reg.
address_offset : 0x1270 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTR[7] CHCTR[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICLSEL BNDSELL BNDSELU CHEVMODE SYNC REFSEL RESREG RESTBS RESPOS BWDCH BWDEN

ICLSEL : Input Class Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific class 0

#01 : value2

Use group-specific class 1

#10 : value3

Use global class 0

#11 : value4

Use global class 1

End of enumeration elements list.

BNDSELL : Lower Boundary Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

BNDSELU : Upper Boundary Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

CHEVMODE : Channel Event Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Never

#01 : value2

NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.)

#10 : value3

NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.)

#11 : value4

NCM: Always (ignore band) FCM: If result switches to either level

End of enumeration elements list.

SYNC : Synchronization Request
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

No synchroniz. request, standalone operation

#1 : value2

Request a synchronized conversion of this channel (only taken into account for a master)

End of enumeration elements list.

REFSEL : Reference Input Selection
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Standard reference input VAREF

#1 : value2

Alternate reference input from CH0

End of enumeration elements list.

RESREG : Result Register
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Store result in group result register GxRES0

#1111 : value2

Store result in group result register GxRES15

End of enumeration elements list.

RESTBS : Result Target for Background Source
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results in the selected group result register

#1 : value2

Store results in the global result register

End of enumeration elements list.

RESPOS : Result Position
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results left-aligned

#1 : value2

Store results right-aligned

End of enumeration elements list.

BWDCH : Broken Wire Detection Channel
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#00 : value1

Select VAGND

#01 : value2

Select VAREF

End of enumeration elements list.

BWDEN : Broken Wire Detection Enable
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal operation

#1 : value2

Additional preparation phase is enabled

End of enumeration elements list.


ASSEL

Autoscan Source Channel Select Register
address_offset : 0x128 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASSEL ASSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSEL0 CHSEL1 CHSEL2 CHSEL3 CHSEL4 CHSEL5 CHSEL6 CHSEL7

CHSEL0 : Channel Selection
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

This channel is part of the scan sequence

End of enumeration elements list.

CHSEL1 : Channel Selection
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

This channel is part of the scan sequence

End of enumeration elements list.

CHSEL2 : Channel Selection
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

This channel is part of the scan sequence

End of enumeration elements list.

CHSEL3 : Channel Selection
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

This channel is part of the scan sequence

End of enumeration elements list.

CHSEL4 : Channel Selection
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

This channel is part of the scan sequence

End of enumeration elements list.

CHSEL5 : Channel Selection
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

This channel is part of the scan sequence

End of enumeration elements list.

CHSEL6 : Channel Selection
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

This channel is part of the scan sequence

End of enumeration elements list.

CHSEL7 : Channel Selection
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

This channel is part of the scan sequence

End of enumeration elements list.


ASPND

Autoscan Source Pending Register
address_offset : 0x12C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ASPND ASPND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHPND0 CHPND1 CHPND2 CHPND3 CHPND4 CHPND5 CHPND6 CHPND7

CHPND0 : Channels Pending
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

Request conversion of this channel

End of enumeration elements list.

CHPND1 : Channels Pending
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

Request conversion of this channel

End of enumeration elements list.

CHPND2 : Channels Pending
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

Request conversion of this channel

End of enumeration elements list.

CHPND3 : Channels Pending
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

Request conversion of this channel

End of enumeration elements list.

CHPND4 : Channels Pending
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

Request conversion of this channel

End of enumeration elements list.

CHPND5 : Channels Pending
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

Request conversion of this channel

End of enumeration elements list.

CHPND6 : Channels Pending
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

Request conversion of this channel

End of enumeration elements list.

CHPND7 : Channels Pending
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Ignore this channel

#1 : value2

Request conversion of this channel

End of enumeration elements list.


ICLASS[0]

Input Class Register
address_offset : 0x140 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICLASS[0] ICLASS[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STCS CMS STCE CME

STCS : Sample Time Control for Standard Conversions
bits : 0 - 3 (4 bit)
access : read-write

CMS : Conversion Mode for Standard Conversions
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : value1

12-bit conversion

#001 : value2

10-bit conversion

#010 : value3

8-bit conversion

#101 : value6

10-bit fast compare mode

End of enumeration elements list.

STCE : Sample Time Control for EMUX Conversions
bits : 16 - 19 (4 bit)
access : read-write

CME : Conversion Mode for EMUX Conversions
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#000 : value1

12-bit conversion

#001 : value2

10-bit conversion

#010 : value3

8-bit conversion

#101 : value6

10-bit fast compare mode

End of enumeration elements list.


RCR[6]

Result Control Register
address_offset : 0x1454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[6] RCR[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


RESD[4]

Result Register, Debug
address_offset : 0x1528 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[4] RESD[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RES[5]

Result Register
address_offset : 0x153C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[5] RES[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RCR[7]

Result Control Register
address_offset : 0x16F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[7] RCR[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


CEFLAG

Channel Event Flag Register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CEFLAG CEFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEV0 CEV1 CEV2 CEV3 CEV4 CEV5 CEV6 CEV7

CEV0 : Channel Event for Channel 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

No channel event

#1 : value2

A channel event has occurred

End of enumeration elements list.

CEV1 : Channel Event for Channel 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

No channel event

#1 : value2

A channel event has occurred

End of enumeration elements list.

CEV2 : Channel Event for Channel 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

No channel event

#1 : value2

A channel event has occurred

End of enumeration elements list.

CEV3 : Channel Event for Channel 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

No channel event

#1 : value2

A channel event has occurred

End of enumeration elements list.

CEV4 : Channel Event for Channel 4
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

No channel event

#1 : value2

A channel event has occurred

End of enumeration elements list.

CEV5 : Channel Event for Channel 5
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

No channel event

#1 : value2

A channel event has occurred

End of enumeration elements list.

CEV6 : Channel Event for Channel 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

No channel event

#1 : value2

A channel event has occurred

End of enumeration elements list.

CEV7 : Channel Event for Channel 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

No channel event

#1 : value2

A channel event has occurred

End of enumeration elements list.


REFLAG

Result Event Flag Register
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REFLAG REFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REV0 REV1 REV2 REV3 REV4 REV5 REV6 REV7 REV8 REV9 REV10 REV11 REV12 REV13 REV14 REV15

REV0 : Result Event for Result Register 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV1 : Result Event for Result Register 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV2 : Result Event for Result Register 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV3 : Result Event for Result Register 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV4 : Result Event for Result Register 4
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV5 : Result Event for Result Register 5
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV6 : Result Event for Result Register 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV7 : Result Event for Result Register 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV8 : Result Event for Result Register 8
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV9 : Result Event for Result Register 9
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV10 : Result Event for Result Register 10
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV11 : Result Event for Result Register 11
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV12 : Result Event for Result Register 12
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV13 : Result Event for Result Register 13
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV14 : Result Event for Result Register 14
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.

REV15 : Result Event for Result Register 15
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : value1

No result event

#1 : value2

New result was stored in register GxRESy

End of enumeration elements list.


RES[6]

Result Register
address_offset : 0x1854 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[6] RES[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


SEFLAG

Source Event Flag Register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEFLAG SEFLAG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEV0 SEV1

SEV0 : Source Event 0/1
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

No source event

#1 : value2

A source event has occurred

End of enumeration elements list.

SEV1 : Source Event 0/1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

No source event

#1 : value2

A source event has occurred

End of enumeration elements list.


RESD[5]

Result Register, Debug
address_offset : 0x18BC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[5] RESD[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


CEFCLR

Channel Event Flag Clear Register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CEFCLR CEFCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEV0 CEV1 CEV2 CEV3 CEV4 CEV5 CEV6 CEV7

CEV0 : Clear Channel Event for Channel 0
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the channel event flag in GxCEFLAG

End of enumeration elements list.

CEV1 : Clear Channel Event for Channel 1
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the channel event flag in GxCEFLAG

End of enumeration elements list.

CEV2 : Clear Channel Event for Channel 2
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the channel event flag in GxCEFLAG

End of enumeration elements list.

CEV3 : Clear Channel Event for Channel 3
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the channel event flag in GxCEFLAG

End of enumeration elements list.

CEV4 : Clear Channel Event for Channel 4
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the channel event flag in GxCEFLAG

End of enumeration elements list.

CEV5 : Clear Channel Event for Channel 5
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the channel event flag in GxCEFLAG

End of enumeration elements list.

CEV6 : Clear Channel Event for Channel 6
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the channel event flag in GxCEFLAG

End of enumeration elements list.

CEV7 : Clear Channel Event for Channel 7
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the channel event flag in GxCEFLAG

End of enumeration elements list.


REFCLR

Result Event Flag Clear Register
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REFCLR REFCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REV0 REV1 REV2 REV3 REV4 REV5 REV6 REV7 REV8 REV9 REV10 REV11 REV12 REV13 REV14 REV15

REV0 : Clear Result Event for Result Register 0
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV1 : Clear Result Event for Result Register 1
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV2 : Clear Result Event for Result Register 2
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV3 : Clear Result Event for Result Register 3
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV4 : Clear Result Event for Result Register 4
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV5 : Clear Result Event for Result Register 5
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV6 : Clear Result Event for Result Register 6
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV7 : Clear Result Event for Result Register 7
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV8 : Clear Result Event for Result Register 8
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV9 : Clear Result Event for Result Register 9
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV10 : Clear Result Event for Result Register 10
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV11 : Clear Result Event for Result Register 11
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV12 : Clear Result Event for Result Register 12
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV13 : Clear Result Event for Result Register 13
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV14 : Clear Result Event for Result Register 14
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.

REV15 : Clear Result Event for Result Register 15
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the result event flag in GxREFLAG

End of enumeration elements list.


SEFCLR

Source Event Flag Clear Register
address_offset : 0x198 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEFCLR SEFCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEV0 SEV1

SEV0 : Clear Source Event 0/1
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the source event flag in GxSEFLAG

End of enumeration elements list.

SEV1 : Clear Source Event 0/1
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Clear the source event flag in GxSEFLAG

End of enumeration elements list.


RCR[8]

Result Control Register
address_offset : 0x1990 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[8] RCR[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


CEVNP0

Channel Event Node Pointer Register 0
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CEVNP0 CEVNP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CEV0NP CEV1NP CEV2NP CEV3NP CEV4NP CEV5NP CEV6NP CEV7NP

CEV0NP : Service Request Node Pointer Channel Event i
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

CEV1NP : Service Request Node Pointer Channel Event i
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

CEV2NP : Service Request Node Pointer Channel Event i
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

CEV3NP : Service Request Node Pointer Channel Event i
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

CEV4NP : Service Request Node Pointer Channel Event i
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

CEV5NP : Service Request Node Pointer Channel Event i
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

CEV6NP : Service Request Node Pointer Channel Event i
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

CEV7NP : Service Request Node Pointer Channel Event i
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.


REVNP0

Result Event Node Pointer Register 0
address_offset : 0x1B0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REVNP0 REVNP0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REV0NP REV1NP REV2NP REV3NP REV4NP REV5NP REV6NP REV7NP

REV0NP : Service Request Node Pointer Result Event i
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV1NP : Service Request Node Pointer Result Event i
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV2NP : Service Request Node Pointer Result Event i
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV3NP : Service Request Node Pointer Result Event i
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV4NP : Service Request Node Pointer Result Event i
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV5NP : Service Request Node Pointer Result Event i
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV6NP : Service Request Node Pointer Result Event i
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV7NP : Service Request Node Pointer Result Event i
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.


REVNP1

Result Event Node Pointer Register 1
address_offset : 0x1B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

REVNP1 REVNP1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REV8NP REV9NP REV10NP REV11NP REV12NP REV13NP REV14NP REV15NP

REV8NP : Service Request Node Pointer Result Event i
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV9NP : Service Request Node Pointer Result Event i
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV10NP : Service Request Node Pointer Result Event i
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV11NP : Service Request Node Pointer Result Event i
bits : 12 - 14 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV12NP : Service Request Node Pointer Result Event i
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV13NP : Service Request Node Pointer Result Event i
bits : 20 - 22 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV14NP : Service Request Node Pointer Result Event i
bits : 24 - 26 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

REV15NP : Service Request Node Pointer Result Event i
bits : 28 - 30 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.


RES[7]

Result Register
address_offset : 0x1B70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[7] RES[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


SEVNP

Source Event Node Pointer Register
address_offset : 0x1C0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SEVNP SEVNP read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEV0NP SEV1NP

SEV0NP : Service Request Node Pointer Source Event i
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.

SEV1NP : Service Request Node Pointer Source Event i
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Select service request line 0 of group x

#0011 : value2

Select service request line 3 of group x

#0100 : value3

Select shared service request line 0

#0111 : value4

Select shared service request line 3

End of enumeration elements list.


RCR[9]

Result Control Register
address_offset : 0x1C34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[9] RCR[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


RESD[6]

Result Register, Debug
address_offset : 0x1C54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[6] RESD[6] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


SRACT

Service Request Software Activation Trigger
address_offset : 0x1C8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRACT SRACT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AGSR0 AGSR1 AGSR2 AGSR3 ASSR0 ASSR1 ASSR2 ASSR3

AGSR0 : Activate Group Service Request Node 0
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Activate the associated service request line

End of enumeration elements list.

AGSR1 : Activate Group Service Request Node 1
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Activate the associated service request line

End of enumeration elements list.

AGSR2 : Activate Group Service Request Node 2
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Activate the associated service request line

End of enumeration elements list.

AGSR3 : Activate Group Service Request Node 3
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Activate the associated service request line

End of enumeration elements list.

ASSR0 : Activate Shared Service Request Node 0
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Activate the associated service request line

End of enumeration elements list.

ASSR1 : Activate Shared Service Request Node 1
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Activate the associated service request line

End of enumeration elements list.

ASSR2 : Activate Shared Service Request Node 2
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Activate the associated service request line

End of enumeration elements list.

ASSR3 : Activate Shared Service Request Node 3
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

No action

#1 : value2

Activate the associated service request line

End of enumeration elements list.


ICLASS[1]

Input Class Register
address_offset : 0x1E4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICLASS[1] ICLASS[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STCS CMS STCE CME

STCS : Sample Time Control for Standard Conversions
bits : 0 - 3 (4 bit)
access : read-write

CMS : Conversion Mode for Standard Conversions
bits : 8 - 9 (2 bit)
access : read-write

Enumeration:

#000 : value1

12-bit conversion

#001 : value2

10-bit conversion

#010 : value3

8-bit conversion

#101 : value6

10-bit fast compare mode

End of enumeration elements list.

STCE : Sample Time Control for EMUX Conversions
bits : 16 - 19 (4 bit)
access : read-write

CME : Conversion Mode for EMUX Conversions
bits : 24 - 25 (2 bit)
access : read-write

Enumeration:

#000 : value1

12-bit conversion

#001 : value2

10-bit conversion

#010 : value3

8-bit conversion

#101 : value6

10-bit fast compare mode

End of enumeration elements list.


RES[8]

Result Register
address_offset : 0x1E90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[8] RES[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RCR[10]

Result Control Register
address_offset : 0x1EDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[10] RCR[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


EMUXCTR

External Multiplexer Control Register
address_offset : 0x1F0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

EMUXCTR EMUXCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EMUXSET EMUXACT EMUXCH EMUXMODE EMXCOD EMXST EMXWC

EMUXSET : External Multiplexer Start Selection
bits : 0 - 1 (2 bit)
access : read-write

EMUXACT : External Multiplexer Actual Selection
bits : 8 - 9 (2 bit)
access : read-only

EMUXCH : External Multiplexer Channel Select
bits : 16 - 19 (4 bit)
access : read-write

EMUXMODE : External Multiplexer Mode
bits : 26 - 26 (1 bit)
access : read-write

Enumeration:

#00 : value1

Software control (no hardware action)

#01 : value2

Steady mode (use EMUXSET value)

#10 : value3

Single-step mode

#11 : value4

Sequence mode

End of enumeration elements list.

EMXCOD : External Multiplexer Coding Scheme
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : value1

Output the channel number in binary code

#1 : value2

Output the channel number in Gray code

End of enumeration elements list.

EMXST : External Multiplexer Sample Time Control
bits : 29 - 28 (0 bit)
access : read-write

Enumeration:

#0 : value1

Use STCE whenever the setting changes

#1 : value2

Use STCE for each conversion of an external channel

End of enumeration elements list.

EMXWC : Write Control for EMUX Configuration
bits : 31 - 30 (0 bit)
access : write-only

Enumeration:

#0 : value1

No write access to EMUX cfg.

#1 : value2

Bitfields EMXMODE, EMXCOD, EMXST can be written

End of enumeration elements list.


VFR

Valid Flag Register
address_offset : 0x1F8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VFR VFR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VF0 VF1 VF2 VF3 VF4 VF5 VF6 VF7 VF8 VF9 VF10 VF11 VF12 VF13 VF14 VF15

VF0 : Valid Flag of Result Register x
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF1 : Valid Flag of Result Register x
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF2 : Valid Flag of Result Register x
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF3 : Valid Flag of Result Register x
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF4 : Valid Flag of Result Register x
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF5 : Valid Flag of Result Register x
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF6 : Valid Flag of Result Register x
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF7 : Valid Flag of Result Register x
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF8 : Valid Flag of Result Register x
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF9 : Valid Flag of Result Register x
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF10 : Valid Flag of Result Register x
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF11 : Valid Flag of Result Register x
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF12 : Valid Flag of Result Register x
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF13 : Valid Flag of Result Register x
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF14 : Valid Flag of Result Register x
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.

VF15 : Valid Flag of Result Register x
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : value1

Read access: No new valid data available Write access: No effect

#1 : value2

Read access: Result register x contains valid data and has not yet been read, or bit FCR has been updated Write access: Clear this valid flag and bitfield DRC in register GxRESy (overrides a hardware set action)

End of enumeration elements list.


RESD[7]

Result Register, Debug
address_offset : 0x1FF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[7] RESD[7] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RCR[11]

Result Control Register
address_offset : 0x2188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[11] RCR[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


RES[9]

Result Register
address_offset : 0x21B4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[9] RES[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RESD[8]

Result Register, Debug
address_offset : 0x2390 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[8] RESD[8] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RCR[12]

Result Control Register
address_offset : 0x2438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[12] RCR[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


RES[10]

Result Register
address_offset : 0x24DC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[10] RES[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RCR[13]

Result Control Register
address_offset : 0x26EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[13] RCR[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


RESD[9]

Result Register, Debug
address_offset : 0x2734 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[9] RESD[9] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RES[11]

Result Register
address_offset : 0x2808 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[11] RES[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RCR[14]

Result Control Register
address_offset : 0x29A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[14] RCR[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


RESD[10]

Result Register, Debug
address_offset : 0x2ADC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[10] RESD[10] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RES[12]

Result Register
address_offset : 0x2B38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[12] RES[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RCR[15]

Result Control Register
address_offset : 0x2C60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[15] RCR[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


RES[13]

Result Register
address_offset : 0x2E6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[13] RES[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RESD[11]

Result Register, Debug
address_offset : 0x2E88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[11] RESD[11] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RES[14]

Result Register
address_offset : 0x31A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[14] RES[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RESD[12]

Result Register, Debug
address_offset : 0x3238 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[12] RESD[12] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RES[15]

Result Register
address_offset : 0x34E0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[15] RES[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RESD[13]

Result Register, Debug
address_offset : 0x35EC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[13] RESD[13] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RESD[14]

Result Register, Debug
address_offset : 0x39A4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[14] RESD[14] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RESD[15]

Result Register, Debug
address_offset : 0x3D60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[15] RESD[15] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


CHCTR[0]

Channel Ctrl. Reg.
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTR[0] CHCTR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICLSEL BNDSELL BNDSELU CHEVMODE SYNC REFSEL RESREG RESTBS RESPOS BWDCH BWDEN

ICLSEL : Input Class Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific class 0

#01 : value2

Use group-specific class 1

#10 : value3

Use global class 0

#11 : value4

Use global class 1

End of enumeration elements list.

BNDSELL : Lower Boundary Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

BNDSELU : Upper Boundary Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

CHEVMODE : Channel Event Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Never

#01 : value2

NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.)

#10 : value3

NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.)

#11 : value4

NCM: Always (ignore band) FCM: If result switches to either level

End of enumeration elements list.

SYNC : Synchronization Request
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

No synchroniz. request, standalone operation

#1 : value2

Request a synchronized conversion of this channel (only taken into account for a master)

End of enumeration elements list.

REFSEL : Reference Input Selection
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Standard reference input VAREF

#1 : value2

Alternate reference input from CH0

End of enumeration elements list.

RESREG : Result Register
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Store result in group result register GxRES0

#1111 : value2

Store result in group result register GxRES15

End of enumeration elements list.

RESTBS : Result Target for Background Source
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results in the selected group result register

#1 : value2

Store results in the global result register

End of enumeration elements list.

RESPOS : Result Position
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results left-aligned

#1 : value2

Store results right-aligned

End of enumeration elements list.

BWDCH : Broken Wire Detection Channel
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#00 : value1

Select VAGND

#01 : value2

Select VAREF

End of enumeration elements list.

BWDEN : Broken Wire Detection Enable
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal operation

#1 : value2

Additional preparation phase is enabled

End of enumeration elements list.


RCR[0]

Result Control Register
address_offset : 0x500 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[0] RCR[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


RES[0]

Result Register
address_offset : 0x600 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[0] RES[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


CHCTR[1]

Channel Ctrl. Reg.
address_offset : 0x604 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTR[1] CHCTR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICLSEL BNDSELL BNDSELU CHEVMODE SYNC REFSEL RESREG RESTBS RESPOS BWDCH BWDEN

ICLSEL : Input Class Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific class 0

#01 : value2

Use group-specific class 1

#10 : value3

Use global class 0

#11 : value4

Use global class 1

End of enumeration elements list.

BNDSELL : Lower Boundary Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

BNDSELU : Upper Boundary Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

CHEVMODE : Channel Event Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Never

#01 : value2

NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.)

#10 : value3

NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.)

#11 : value4

NCM: Always (ignore band) FCM: If result switches to either level

End of enumeration elements list.

SYNC : Synchronization Request
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

No synchroniz. request, standalone operation

#1 : value2

Request a synchronized conversion of this channel (only taken into account for a master)

End of enumeration elements list.

REFSEL : Reference Input Selection
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Standard reference input VAREF

#1 : value2

Alternate reference input from CH0

End of enumeration elements list.

RESREG : Result Register
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Store result in group result register GxRES0

#1111 : value2

Store result in group result register GxRES15

End of enumeration elements list.

RESTBS : Result Target for Background Source
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results in the selected group result register

#1 : value2

Store results in the global result register

End of enumeration elements list.

RESPOS : Result Position
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results left-aligned

#1 : value2

Store results right-aligned

End of enumeration elements list.

BWDCH : Broken Wire Detection Channel
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#00 : value1

Select VAGND

#01 : value2

Select VAREF

End of enumeration elements list.

BWDEN : Broken Wire Detection Enable
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal operation

#1 : value2

Additional preparation phase is enabled

End of enumeration elements list.


RESD[0]

Result Register, Debug
address_offset : 0x700 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[0] RESD[0] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RCR[1]

Result Control Register
address_offset : 0x784 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[1] RCR[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


ARBCFG

Arbitration Configuration Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARBCFG ARBCFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ANONC ARBRND ARBM ANONS CAL BUSY SAMPLE

ANONC : Analog Converter Control
bits : 0 - 0 (1 bit)
access : read-write

ARBRND : Arbitration Round Length
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

4 arbitration slots per round (tARB = 4 / fADCD)

#01 : value2

8 arbitration slots per round (tARB = 8 / fADCD)

#10 : value3

16 arbitration slots per round (tARB = 16 / fADCD)

#11 : value4

20 arbitration slots per round (tARB = 20 / fADCD)

End of enumeration elements list.

ARBM : Arbitration Mode
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

The arbiter runs permanently. This setting is required for a synchronization slave (see ) and for equidistant sampling using the signal ARBCNT (see ).

#1 : value2

The arbiter only runs if at least one conversion request of an enabled request source is pending. This setting ensures a reproducible latency from an incoming request to the conversion start, if the converter is idle. Synchronized conversions are not supported.

End of enumeration elements list.

ANONS : Analog Converter Control Status
bits : 16 - 16 (1 bit)
access : read-only

Enumeration:

#00 : value1

Analog converter off

#11 : value4

Normal operation (permanently on)

End of enumeration elements list.

CAL : Start-Up Calibration Active Indication
bits : 28 - 27 (0 bit)
access : read-only

Enumeration:

#0 : value1

Completed or not yet started

#1 : value2

Start-up calibration phase is active

End of enumeration elements list.

BUSY : Converter Busy Flag
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Not busy

#1 : value2

Converter is busy with a conversion

End of enumeration elements list.

SAMPLE : Sample Phase Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

Converting or idle

#1 : value2

Input signal is currently sampled

End of enumeration elements list.


CHCTR[2]

Channel Ctrl. Reg.
address_offset : 0x80C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTR[2] CHCTR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICLSEL BNDSELL BNDSELU CHEVMODE SYNC REFSEL RESREG RESTBS RESPOS BWDCH BWDEN

ICLSEL : Input Class Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific class 0

#01 : value2

Use group-specific class 1

#10 : value3

Use global class 0

#11 : value4

Use global class 1

End of enumeration elements list.

BNDSELL : Lower Boundary Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

BNDSELU : Upper Boundary Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

CHEVMODE : Channel Event Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Never

#01 : value2

NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.)

#10 : value3

NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.)

#11 : value4

NCM: Always (ignore band) FCM: If result switches to either level

End of enumeration elements list.

SYNC : Synchronization Request
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

No synchroniz. request, standalone operation

#1 : value2

Request a synchronized conversion of this channel (only taken into account for a master)

End of enumeration elements list.

REFSEL : Reference Input Selection
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Standard reference input VAREF

#1 : value2

Alternate reference input from CH0

End of enumeration elements list.

RESREG : Result Register
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Store result in group result register GxRES0

#1111 : value2

Store result in group result register GxRES15

End of enumeration elements list.

RESTBS : Result Target for Background Source
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results in the selected group result register

#1 : value2

Store results in the global result register

End of enumeration elements list.

RESPOS : Result Position
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results left-aligned

#1 : value2

Store results right-aligned

End of enumeration elements list.

BWDCH : Broken Wire Detection Channel
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#00 : value1

Select VAGND

#01 : value2

Select VAREF

End of enumeration elements list.

BWDEN : Broken Wire Detection Enable
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal operation

#1 : value2

Additional preparation phase is enabled

End of enumeration elements list.


ARBPR

Arbitration Priority Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ARBPR ARBPR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRIO0 CSM0 PRIO1 CSM1 PRIO2 CSM2 ASEN0 ASEN1 ASEN2

PRIO0 : Priority of Request Source x
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Lowest priority is selected.

#11 : value2

Highest priority is selected.

End of enumeration elements list.

CSM0 : Conversion Start Mode of Request Source x
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Wait-for-start mode

#1 : value2

Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources.

End of enumeration elements list.

PRIO1 : Priority of Request Source x
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Lowest priority is selected.

#11 : value2

Highest priority is selected.

End of enumeration elements list.

CSM1 : Conversion Start Mode of Request Source x
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Wait-for-start mode

#1 : value2

Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources.

End of enumeration elements list.

PRIO2 : Priority of Request Source x
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Lowest priority is selected.

#11 : value2

Highest priority is selected.

End of enumeration elements list.

CSM2 : Conversion Start Mode of Request Source x
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Wait-for-start mode

#1 : value2

Cancel-inject-repeat mode, i.e. this source can cancel conversion of other sources.

End of enumeration elements list.

ASEN0 : Arbitration Slot 0 Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded.

#1 : value2

The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated.

End of enumeration elements list.

ASEN1 : Arbitration Slot 1 Enable
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

#0 : value1

The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded.

#1 : value2

The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated.

End of enumeration elements list.

ASEN2 : Arbitration Slot 2 Enable
bits : 26 - 25 (0 bit)
access : read-write

Enumeration:

#0 : value1

The corresponding arbitration slot is disabled and considered as empty. Pending conversion requests from the associated request source are disregarded.

#1 : value2

The corresponding arbitration slot is enabled. Pending conversion requests from the associated request source are arbitrated.

End of enumeration elements list.


CHASS

Channel Assignment Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHASS CHASS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASSCH0 ASSCH1 ASSCH2 ASSCH3 ASSCH4 ASSCH5 ASSCH6 ASSCH7

ASSCH0 : Assignment for Channel 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Channel y can be a background channel converted with lowest priority

#1 : value2

Channel y is a priority channel within group x

End of enumeration elements list.

ASSCH1 : Assignment for Channel 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Channel y can be a background channel converted with lowest priority

#1 : value2

Channel y is a priority channel within group x

End of enumeration elements list.

ASSCH2 : Assignment for Channel 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Channel y can be a background channel converted with lowest priority

#1 : value2

Channel y is a priority channel within group x

End of enumeration elements list.

ASSCH3 : Assignment for Channel 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Channel y can be a background channel converted with lowest priority

#1 : value2

Channel y is a priority channel within group x

End of enumeration elements list.

ASSCH4 : Assignment for Channel 4
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Channel y can be a background channel converted with lowest priority

#1 : value2

Channel y is a priority channel within group x

End of enumeration elements list.

ASSCH5 : Assignment for Channel 5
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Channel y can be a background channel converted with lowest priority

#1 : value2

Channel y is a priority channel within group x

End of enumeration elements list.

ASSCH6 : Assignment for Channel 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

Channel y can be a background channel converted with lowest priority

#1 : value2

Channel y is a priority channel within group x

End of enumeration elements list.

ASSCH7 : Assignment for Channel 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Channel y can be a background channel converted with lowest priority

#1 : value2

Channel y is a priority channel within group x

End of enumeration elements list.


RES[1]

Result Register
address_offset : 0x904 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[1] RES[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RCR[2]

Result Control Register
address_offset : 0xA0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[2] RCR[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


CHCTR[3]

Channel Ctrl. Reg.
address_offset : 0xA18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTR[3] CHCTR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICLSEL BNDSELL BNDSELU CHEVMODE SYNC REFSEL RESREG RESTBS RESPOS BWDCH BWDEN

ICLSEL : Input Class Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific class 0

#01 : value2

Use group-specific class 1

#10 : value3

Use global class 0

#11 : value4

Use global class 1

End of enumeration elements list.

BNDSELL : Lower Boundary Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

BNDSELU : Upper Boundary Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

CHEVMODE : Channel Event Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Never

#01 : value2

NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.)

#10 : value3

NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.)

#11 : value4

NCM: Always (ignore band) FCM: If result switches to either level

End of enumeration elements list.

SYNC : Synchronization Request
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

No synchroniz. request, standalone operation

#1 : value2

Request a synchronized conversion of this channel (only taken into account for a master)

End of enumeration elements list.

REFSEL : Reference Input Selection
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Standard reference input VAREF

#1 : value2

Alternate reference input from CH0

End of enumeration elements list.

RESREG : Result Register
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Store result in group result register GxRES0

#1111 : value2

Store result in group result register GxRES15

End of enumeration elements list.

RESTBS : Result Target for Background Source
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results in the selected group result register

#1 : value2

Store results in the global result register

End of enumeration elements list.

RESPOS : Result Position
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results left-aligned

#1 : value2

Store results right-aligned

End of enumeration elements list.

BWDCH : Broken Wire Detection Channel
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#00 : value1

Select VAGND

#01 : value2

Select VAREF

End of enumeration elements list.

BWDEN : Broken Wire Detection Enable
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal operation

#1 : value2

Additional preparation phase is enabled

End of enumeration elements list.


RESD[1]

Result Register, Debug
address_offset : 0xA84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[1] RESD[1] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


ALIAS

Alias Register
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ALIAS ALIAS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALIAS0 ALIAS1

ALIAS0 : Alias Value for CH0 Conversion Requests
bits : 0 - 3 (4 bit)
access : read-write

ALIAS1 : Alias Value for CH1 Conversion Requests
bits : 8 - 11 (4 bit)
access : read-write


BOUND

Boundary Select Register
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BOUND BOUND read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOUNDARY0 BOUNDARY1

BOUNDARY0 : Boundary Value 0 for Limit Checking
bits : 0 - 10 (11 bit)
access : read-write

BOUNDARY1 : Boundary Value 1 for Limit Checking
bits : 16 - 26 (11 bit)
access : read-write


SYNCTR

Synchronization Control Register
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYNCTR SYNCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STSEL EVALR1 EVALR2 EVALR3

STSEL : Start Selection
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Kernel is synchronization master: Use own bitfield GxARBCFG.ANONC

#01 : value2

Kernel is synchronization slave: Control information from input CI1

#10 : value3

Kernel is synchronization slave: Control information from input CI2

#11 : value4

Kernel is synchronization slave: Control information from input CI3

End of enumeration elements list.

EVALR1 : Evaluate Ready Input Rx
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

No ready input control

#1 : value2

Ready input Rx is considered for the start of a parallel conversion of this conversion group

End of enumeration elements list.

EVALR2 : Evaluate Ready Input Rx
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

No ready input control

#1 : value2

Ready input Rx is considered for the start of a parallel conversion of this conversion group

End of enumeration elements list.

EVALR3 : Evaluate Ready Input Rx
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

No ready input control

#1 : value2

Ready input Rx is considered for the start of a parallel conversion of this conversion group

End of enumeration elements list.


RES[2]

Result Register
address_offset : 0xC0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[2] RES[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


CHCTR[4]

Channel Ctrl. Reg.
address_offset : 0xC28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTR[4] CHCTR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICLSEL BNDSELL BNDSELU CHEVMODE SYNC REFSEL RESREG RESTBS RESPOS BWDCH BWDEN

ICLSEL : Input Class Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific class 0

#01 : value2

Use group-specific class 1

#10 : value3

Use global class 0

#11 : value4

Use global class 1

End of enumeration elements list.

BNDSELL : Lower Boundary Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

BNDSELU : Upper Boundary Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

CHEVMODE : Channel Event Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Never

#01 : value2

NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.)

#10 : value3

NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.)

#11 : value4

NCM: Always (ignore band) FCM: If result switches to either level

End of enumeration elements list.

SYNC : Synchronization Request
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

No synchroniz. request, standalone operation

#1 : value2

Request a synchronized conversion of this channel (only taken into account for a master)

End of enumeration elements list.

REFSEL : Reference Input Selection
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Standard reference input VAREF

#1 : value2

Alternate reference input from CH0

End of enumeration elements list.

RESREG : Result Register
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Store result in group result register GxRES0

#1111 : value2

Store result in group result register GxRES15

End of enumeration elements list.

RESTBS : Result Target for Background Source
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results in the selected group result register

#1 : value2

Store results in the global result register

End of enumeration elements list.

RESPOS : Result Position
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results left-aligned

#1 : value2

Store results right-aligned

End of enumeration elements list.

BWDCH : Broken Wire Detection Channel
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#00 : value1

Select VAGND

#01 : value2

Select VAREF

End of enumeration elements list.

BWDEN : Broken Wire Detection Enable
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal operation

#1 : value2

Additional preparation phase is enabled

End of enumeration elements list.


BFL

Boundary Flag Register
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BFL BFL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BFL0 BFL1 BFL2 BFL3 BFE0 BFE1 BFE2 BFE3

BFL0 : Boundar0 Flag y
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled

#1 : value2

Active state: result has crossed the activation boundary

End of enumeration elements list.

BFL1 : Boundar1 Flag y
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : value1

Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled

#1 : value2

Active state: result has crossed the activation boundary

End of enumeration elements list.

BFL2 : Boundar2 Flag y
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled

#1 : value2

Active state: result has crossed the activation boundary

End of enumeration elements list.

BFL3 : Boundar3 Flag y
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : value1

Passive state: result has not yet crossed the activation boundary, or selected gate signal is inactive, or this boundary flag is disabled

#1 : value2

Active state: result has crossed the activation boundary

End of enumeration elements list.

BFE0 : Enable Bit for Boundar0 Flag y
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : value1

Output 0 on this channel

#1 : value2

Output BFLy on this channel

End of enumeration elements list.

BFE1 : Enable Bit for Boundar1 Flag y
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : value1

Output 0 on this channel

#1 : value2

Output BFLy on this channel

End of enumeration elements list.

BFE2 : Enable Bit for Boundar2 Flag y
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

#0 : value1

Output 0 on this channel

#1 : value2

Output BFLy on this channel

End of enumeration elements list.

BFE3 : Enable Bit for Boundar3 Flag y
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

#0 : value1

Output 0 on this channel

#1 : value2

Output BFLy on this channel

End of enumeration elements list.


RCR[3]

Result Control Register
address_offset : 0xC98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[3] RCR[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.


RESD[2]

Result Register, Debug
address_offset : 0xE0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESD[2] RESD[2] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-only

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


CHCTR[5]

Channel Ctrl. Reg.
address_offset : 0xE3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHCTR[5] CHCTR[5] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ICLSEL BNDSELL BNDSELU CHEVMODE SYNC REFSEL RESREG RESTBS RESPOS BWDCH BWDEN

ICLSEL : Input Class Select
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific class 0

#01 : value2

Use group-specific class 1

#10 : value3

Use global class 0

#11 : value4

Use global class 1

End of enumeration elements list.

BNDSELL : Lower Boundary Select
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

BNDSELU : Upper Boundary Select
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

Use group-specific boundary 0

#01 : value2

Use group-specific boundary 1

#10 : value3

Use global boundary 0

#11 : value4

Use global boundary 1

End of enumeration elements list.

CHEVMODE : Channel Event Mode
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Never

#01 : value2

NCM: If result is inside the boundary band FCM: If result becomes high (above cmp. val.)

#10 : value3

NCM: If result is outside the boundary band FCM: If result becomes low (below cmp. val.)

#11 : value4

NCM: Always (ignore band) FCM: If result switches to either level

End of enumeration elements list.

SYNC : Synchronization Request
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

No synchroniz. request, standalone operation

#1 : value2

Request a synchronized conversion of this channel (only taken into account for a master)

End of enumeration elements list.

REFSEL : Reference Input Selection
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Standard reference input VAREF

#1 : value2

Alternate reference input from CH0

End of enumeration elements list.

RESREG : Result Register
bits : 16 - 18 (3 bit)
access : read-write

Enumeration:

#0000 : value1

Store result in group result register GxRES0

#1111 : value2

Store result in group result register GxRES15

End of enumeration elements list.

RESTBS : Result Target for Background Source
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results in the selected group result register

#1 : value2

Store results in the global result register

End of enumeration elements list.

RESPOS : Result Position
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : value1

Store results left-aligned

#1 : value2

Store results right-aligned

End of enumeration elements list.

BWDCH : Broken Wire Detection Channel
bits : 28 - 28 (1 bit)
access : read-write

Enumeration:

#00 : value1

Select VAGND

#01 : value2

Select VAREF

End of enumeration elements list.

BWDEN : Broken Wire Detection Enable
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal operation

#1 : value2

Additional preparation phase is enabled

End of enumeration elements list.


RES[3]

Result Register
address_offset : 0xF18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES[3] RES[3] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RESULT DRC CHNR EMUX CRS FCR VF

RESULT : Result of Most Recent Conversion
bits : 0 - 14 (15 bit)
access : read-write

DRC : Data Reduction Counter
bits : 16 - 18 (3 bit)
access : read-only

CHNR : Channel Number
bits : 20 - 23 (4 bit)
access : read-only

EMUX : External Multiplexer Setting
bits : 25 - 26 (2 bit)
access : read-only

CRS : Converted Request Source
bits : 28 - 28 (1 bit)
access : read-only

Enumeration:

#00 : value1

Request source 0

#01 : value2

Request source 1

#10 : value3

Request source 2

End of enumeration elements list.

FCR : Fast Compare Result
bits : 30 - 29 (0 bit)
access : read-only

Enumeration:

#0 : value1

Signal level was below compare value

#1 : value2

Signal level was above compare value

End of enumeration elements list.

VF : Valid Flag
bits : 31 - 30 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new result available

#1 : value2

Bitfield RESULT has been updated with new result value and has not yet been read, or bit FCR has been updated

End of enumeration elements list.


RCR[4]

Result Control Register
address_offset : 0xF28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RCR[4] RCR[4] read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DRCTR DMM WFR FEN SRGEN

DRCTR : Data Reduction Control
bits : 16 - 18 (3 bit)
access : read-write

DMM : Data Modification Mode
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Standard data reduction (accumulation)

#01 : value2

Result filtering mode

#10 : value3

Difference mode

End of enumeration elements list.

WFR : Wait-for-Read Mode Enable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Overwrite mode

#1 : value2

Wait-for-read mode enabled for this register

End of enumeration elements list.

FEN : FIFO Mode Enable
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

Separate result register

#01 : value2

Part of a FIFO structure: copy each new valid result

End of enumeration elements list.

SRGEN : Service Request Generation Enable
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

No service request

#1 : value2

Service request after a result event

End of enumeration elements list.



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