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CCU8

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

INS

TCCLR

TC

PSL

DIT

DITS

PSC

FPC

FPCS

PR

PRS

CR1

CR1S

CMC

CR2

CR2S

CHC

DTC

DC1R

DC2R

TIMER

C0V

C1V

C2V

TCST

C3V

INTS

INTE

SRS

SWS

SWR

TCSET


INS

Input Selector Configuration
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INS INS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EV0IS EV1IS EV2IS EV0EM EV1EM EV2EM EV0LM EV1LM EV2LM LPF0M LPF1M LPF2M

EV0IS : Event 0 signal selection
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

#0000 : value1

CCU8x.INyA

#0001 : value2

CCU8x.INyB

#0010 : value3

CCU8x.INyC

#0011 : value4

CCU8x.INyD

#0100 : value5

CCU8x.INyE

#0101 : value6

CCU8x.INyF

#0110 : value7

CCU8x.INyG

#0111 : value8

CCU8x.INyH

#1000 : value9

CCU8x.INyI

#1001 : value10

CCU8x.INyJ

#1010 : value11

CCU8x.INyK

#1011 : value12

CCU8x.INyL

#1100 : value13

CCU8x.INyM

#1101 : value14

CCU8x.INyN

#1110 : value15

CCU8x.INyO

#1111 : value16

CCU8x.INyP

End of enumeration elements list.

EV1IS : Event 1 signal selection
bits : 4 - 6 (3 bit)
access : read-write

Enumeration:

#0000 : value1

CCU8x.INyA

#0001 : value2

CCU8x.INyB

#0010 : value3

CCU8x.INyC

#0011 : value4

CCU8x.INyD

#0100 : value5

CCU8x.INyE

#0101 : value6

CCU8x.INyF

#0110 : value7

CCU8x.INyG

#0111 : value8

CCU8x.INyH

#1000 : value9

CCU8x.INyI

#1001 : value10

CCU8x.INyJ

#1010 : value11

CCU8x.INyK

#1011 : value12

CCU8x.INyL

#1100 : value13

CCU8x.INyM

#1101 : value14

CCU8x.INyN

#1110 : value15

CCU8x.INyO

#1111 : value16

CCU8x.INyP

End of enumeration elements list.

EV2IS : Event 2 signal selection
bits : 8 - 10 (3 bit)
access : read-write

Enumeration:

#0000 : value1

CCU8x.INyA

#0001 : value2

CCU8x.INyB

#0010 : value3

CCU8x.INyC

#0011 : value4

CCU8x.INyD

#0100 : value5

CCU8x.INyE

#0101 : value6

CCU8x.INyF

#0110 : value7

CCU8x.INyG

#0111 : value8

CCU8x.INyH

#1000 : value9

CCU8x.INyI

#1001 : value10

CCU8x.INyJ

#1010 : value11

CCU8x.INyK

#1011 : value12

CCU8x.INyL

#1100 : value13

CCU8x.INyM

#1101 : value14

CCU8x.INyN

#1110 : value15

CCU8x.INyO

#1111 : value16

CCU8x.INyP

End of enumeration elements list.

EV0EM : Event 0 Edge Selection
bits : 16 - 16 (1 bit)
access : read-write

Enumeration:

#00 : value1

No action

#01 : value2

Signal active on rising edge

#10 : value3

Signal active on falling edge

#11 : value4

Signal active on both edges

End of enumeration elements list.

EV1EM : Event 1 Edge Selection
bits : 18 - 18 (1 bit)
access : read-write

Enumeration:

#00 : value1

No action

#01 : value2

Signal active on rising edge

#10 : value3

Signal active on falling edge

#11 : value4

Signal active on both edges

End of enumeration elements list.

EV2EM : Event 2 Edge Selection
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

No action

#01 : value2

Signal active on rising edge

#10 : value3

Signal active on falling edge

#11 : value4

Signal active on both edges

End of enumeration elements list.

EV0LM : Event 0 Level Selection
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

#0 : value1

Active on HIGH level

#1 : value2

Active on LOW level

End of enumeration elements list.

EV1LM : Event 1 Level Selection
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

#0 : value1

Active on HIGH level

#1 : value2

Active on LOW level

End of enumeration elements list.

EV2LM : Event 2 Level Selection
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

Active on HIGH level

#1 : value2

Active on LOW level

End of enumeration elements list.

LPF0M : Event 0 Low Pass Filter Configuration
bits : 25 - 25 (1 bit)
access : read-write

Enumeration:

#00 : value1

LPF is disabled

#01 : value2

3 clock cycles of fCCU8

#10 : value3

5 clock cycles of fCCU8

#11 : value4

7 clock cycles of fCCU8

End of enumeration elements list.

LPF1M : Event 1 Low Pass Filter Configuration
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#00 : value1

LPF is disabled

#01 : value2

3 clock cycles of fCCU8

#10 : value3

5 clock cycles of fCCU8

#11 : value4

7 clock cycles of fCCU8

End of enumeration elements list.

LPF2M : Event 2 Low Pass Filter Configuration
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#00 : value1

LPF is disabled

#01 : value2

3 clock cycles of fCCU8

#10 : value3

5 clock cycles of fCCU8

#11 : value4

7 clock cycles of fCCU8

End of enumeration elements list.


TCCLR

Slice Timer Clear
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCCLR TCCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRBC TCC DITC DTC1C DTC2C

TRBC : Timer Run Bit Clear
bits : 0 - -1 (0 bit)
access : write-only

TCC : Timer Clear
bits : 1 - 0 (0 bit)
access : write-only

DITC : Dither Counter Clear
bits : 2 - 1 (0 bit)
access : write-only

DTC1C : Dead Time Counter 1 Clear
bits : 3 - 2 (0 bit)
access : write-only

DTC2C : Dead Time Counter 2 Clear
bits : 4 - 3 (0 bit)
access : write-only


TC

Slice Timer Control
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TC TC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TCM TSSM CLST CMOD ECM CAPC TLS ENDM STRM SCE CCS DITHE DIM FPE TRAPE0 TRAPE1 TRAPE2 TRAPE3 TRPSE TRPSW EMS EMT MCME1 MCME2 EME STOS

TCM : Timer Counting Mode
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Edge aligned mode

#1 : value2

Center aligned mode

End of enumeration elements list.

TSSM : Timer Single Shot Mode
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Single shot mode is disabled

#1 : value2

Single shot mode is enabled

End of enumeration elements list.

CLST : Shadow Transfer on Clear
bits : 2 - 1 (0 bit)
access : read-write

CMOD : Capture Compare Mode
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : value1

Compare Mode

#1 : value2

Capture Mode

End of enumeration elements list.

ECM : Extended Capture Mode
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Normal Capture Mode. Clear of the Full Flag of each capture register is done by accessing the registers individually only.

#1 : value2

Extended Capture Mode. Clear of the Full Flag of each capture register is done not only by accessing the individual registers but also by accessing the ECRD register. When reading the ECRD register, only the capture register register full flag pointed by the VPTR is cleared

End of enumeration elements list.

CAPC : Clear on Capture Control
bits : 5 - 5 (1 bit)
access : read-write

Enumeration:

#00 : value1

Timer is never cleared on a capture event

#01 : value2

Timer is cleared on a capture event into capture registers 2 and 3. (When SCE = 1#, Timer is always cleared in a capture event)

#10 : value3

Timer is cleared on a capture event into capture registers 0 and 1. (When SCE = 1#, Timer is always cleared in a capture event)

#11 : value4

Timer is always cleared in a capture event.

End of enumeration elements list.

TLS : Timer Load selector
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

Timer is loaded with the value of CR1

#1 : value2

Timer is loaded with the value of CR2

End of enumeration elements list.

ENDM : Extended Stop Function Control
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Clears the timer run bit only (default stop)

#01 : value2

Clears the timer only (flush)

#10 : value3

Clears the timer and run bit (flush/stop)

End of enumeration elements list.

STRM : Extended Start Function Control
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

Sets run bit only (default start)

#1 : value2

Clears the timer and sets run bit, if not set (flush/start)

End of enumeration elements list.

SCE : Equal Capture Event enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. registers control by CCycapt0 and capture into CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1

#1 : value2

Capture into CC8yC0VThis register contains the values associated with the Capture 0 field./CC8yC1VThis register contains the values associated with the Capture 1 field. and CC8yC3VThis register contains the values associated with the Capture 3 field./CC8yC2VThis register contains the values associated with the Capture 2 field. control by CCycapt1

End of enumeration elements list.

CCS : Continuous Capture Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : value1

The capture into a specific capture register is done with the rules linked with the full flags, described at .

#1 : value2

The capture into the capture registers is always done regardless of the full flag status (even if the register has not been read back).

End of enumeration elements list.

DITHE : Dither Enable
bits : 13 - 13 (1 bit)
access : read-write

Enumeration:

#00 : value1

Dither is disabled

#01 : value2

Dither is applied to the Period

#10 : value3

Dither is applied to the Compare

#11 : value4

Dither is applied to the Period and Compare

End of enumeration elements list.

DIM : Dither input selector
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : value1

Slice is using it own dither unit

#1 : value2

Slice is connected to the dither unit of slice 0.

End of enumeration elements list.

FPE : Floating Prescaler enable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : value1

Floating prescaler mode is disabled

#1 : value2

Floating prescaler mode is enabled

End of enumeration elements list.

TRAPE0 : TRAP enable for CCU8x.OUTy0
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : value1

TRAP functionality has no effect on the CCU8x.OUTy0 output

#1 : value2

TRAP functionality affects the CCU8x.OUTy0 output

End of enumeration elements list.

TRAPE1 : TRAP enable for CCU8x.OUTy1
bits : 18 - 17 (0 bit)
access : read-write

TRAPE2 : TRAP enable for CCU8x.OUTy2
bits : 19 - 18 (0 bit)
access : read-write

TRAPE3 : TRAP enable for CCU8x.OUTy3
bits : 20 - 19 (0 bit)
access : read-write

TRPSE : TRAP Synchronization Enable
bits : 21 - 20 (0 bit)
access : read-write

Enumeration:

#0 : value1

Exiting from TRAP state isn't synchronized with the PWM signal

#1 : value2

Exiting from TRAP state is synchronized with the PWM signal

End of enumeration elements list.

TRPSW : TRAP State Clear Control
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

#0 : value1

The slice exits the TRAP state automatically when the TRAP condition is not present (Trap state cleared by HW and SW)

#1 : value2

The TRAP state can only be exited by a SW request.

End of enumeration elements list.

EMS : External Modulation Synchronization
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

#0 : value1

External Modulation functionality is not synchronized with the PWM signal

#1 : value2

External Modulation functionality is synchronized with the PWM signal

End of enumeration elements list.

EMT : External Modulation Type
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

External Modulation functionality is clearing the CC8ySTx bits.

#1 : value2

External Modulation functionality is gating the outputs.

End of enumeration elements list.

MCME1 : Multi Channel Mode Enable for Channel 1
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

#0 : value1

Multi Channel Mode in Channel 1 is disabled

#1 : value2

Multi Channel Mode in Channel 1 is enabled

End of enumeration elements list.

MCME2 : Multi Channel Mode Enable for Channel 2
bits : 26 - 25 (0 bit)
access : read-write

Enumeration:

#0 : value1

Multi Channel Mode in Channel 2 is disabled

#1 : value2

Multi Channel Mode in Channel 2 is enabled

End of enumeration elements list.

EME : External Modulation Channel enable
bits : 27 - 27 (1 bit)
access : read-write

Enumeration:

#00 : value1

External Modulation functionality doesn't affect any channel

#01 : value2

External Modulation only applied on channel 1

#10 : value3

External Modulation only applied on channel 2

#11 : value4

External Modulation applied on both channels

End of enumeration elements list.

STOS : Status bit output selector
bits : 29 - 29 (1 bit)
access : read-write

Enumeration:

#00 : value1

CC8yST1 forward to CCU8x.STy

#01 : value2

CC8yST2 forward to CCU8x.STy

#10 : value3

CC8yST1 AND CC8yST2 forward to CCU8x.STy

End of enumeration elements list.


PSL

Passive Level Config
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSL PSL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSL11 PSL12 PSL21 PSL22

PSL11 : Output Passive Level for CCU8x.OUTy0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Passive Level is LOW

#1 : value2

Passive Level is HIGH

End of enumeration elements list.

PSL12 : Output Passive Level for CCU8x.OUTy1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Passive Level is LOW

#1 : value2

Passive Level is HIGH

End of enumeration elements list.

PSL21 : Output Passive Level for CCU8x.OUTy2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Passive Level is LOW

#1 : value2

Passive Level is HIGH

End of enumeration elements list.

PSL22 : Output Passive Level for CCU8x.OUTy3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Passive Level is LOW

#1 : value2

Passive Level is HIGH

End of enumeration elements list.


DIT

Dither Config
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DIT DIT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCV DCNT

DCV : Dither compare Value
bits : 0 - 2 (3 bit)
access : read-only

DCNT : Dither counter actual value
bits : 8 - 10 (3 bit)
access : read-only


DITS

Dither Shadow Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DITS DITS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DCVS

DCVS : Dither Shadow Compare Value
bits : 0 - 2 (3 bit)
access : read-write


PSC

Prescaler Control
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PSC PSC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSIV

PSIV : Prescaler Initial Value
bits : 0 - 2 (3 bit)
access : read-write


FPC

Floating Prescaler Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPC FPC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCMP PVAL

PCMP : Floating Prescaler Compare Value
bits : 0 - 2 (3 bit)
access : read-only

PVAL : Actual Prescaler Value
bits : 8 - 10 (3 bit)
access : read-write


FPCS

Floating Prescaler Shadow
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPCS FPCS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PCMP

PCMP : Floating Prescaler Shadow Compare Value
bits : 0 - 2 (3 bit)
access : read-write


PR

Timer Period Value
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PR PR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PR

PR : Period Register
bits : 0 - 14 (15 bit)
access : read-only


PRS

Timer Shadow Period Value
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRS PRS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRS

PRS : Period Register
bits : 0 - 14 (15 bit)
access : read-write


CR1

Channel 1 Compare Value
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1 CR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR1

CR1 : Compare Register for Channel 1
bits : 0 - 14 (15 bit)
access : read-only


CR1S

Channel 1 Compare Shadow Value
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR1S CR1S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR1S

CR1S : Shadow Compare Register for Channel 1
bits : 0 - 14 (15 bit)
access : read-write


CMC

Connection Matrix Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CMC CMC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STRTS ENDS CAP0S CAP1S GATES UDS LDS CNTS OFS TS MOS TCE

STRTS : External Start Functionality Selector
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

External Start Function deactivated

#01 : value2

External Start Function triggered by Event 0

#10 : value3

External Start Function triggered by Event 1

#11 : value4

External Start Function triggered by Event 2

End of enumeration elements list.

ENDS : External Stop Functionality Selector
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : value1

External Stop Function deactivated

#01 : value2

External Stop Function triggered by Event 0

#10 : value3

External Stop Function triggered by Event 1

#11 : value4

External Stop Function triggered by Event 2

End of enumeration elements list.

CAP0S : External Capture 0 Functionality Selector
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

External Capture 0 Function deactivated

#01 : value2

External Capture 0 Function triggered by Event 0

#10 : value3

External Capture 0 Function triggered by Event 1

#11 : value4

External Capture 0 Function triggered by Event 2

End of enumeration elements list.

CAP1S : External Capture 1 Functionality Selector
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

External Capture 1 Function deactivated

#01 : value2

External Capture 1 Function triggered by Event 0

#10 : value3

External Capture 1 Function triggered by Event 1

#11 : value4

External Capture 1 Function triggered by Event 2

End of enumeration elements list.

GATES : External Gate Functionality Selector
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

External Gating Function deactivated

#01 : value2

External Gating Function triggered by Event 0

#10 : value3

External Gating Function triggered by Event 1

#11 : value4

External Gating Function triggered by Event 2

End of enumeration elements list.

UDS : External Up/Down Functionality Selector
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#00 : value1

External Up/Down Function deactivated

#01 : value2

External Up/Down Function triggered by Event 0

#10 : value3

External Up/Down Function triggered by Event 1

#11 : value4

External Up/Down Function triggered by Event 2

End of enumeration elements list.

LDS : External Timer Load Functionality Selector
bits : 12 - 12 (1 bit)
access : read-write

CNTS : External Count Selector
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#00 : value1

External Count Function deactivated

#01 : value2

External Count Function triggered by Event 0

#10 : value3

External Count Function triggered by Event 1

#11 : value4

External Count Function triggered by Event 2

End of enumeration elements list.

OFS : Override Function Selector
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : value1

Override functionality disabled

#1 : value2

Status bit trigger override connected to Event 1; Status bit value override connected to Event 2

End of enumeration elements list.

TS : Trap Function Selector
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : value1

Trap function disabled

#1 : value2

TRAP function connected to Event 2

End of enumeration elements list.

MOS : External Modulation Functionality Selector
bits : 18 - 18 (1 bit)
access : read-write

TCE : Timer Concatenation Enable
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

#0 : value1

Timer concatenation is disabled

#1 : value2

Timer concatenation is enabled

End of enumeration elements list.


CR2

Channel 2 Compare Value
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2 CR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR2

CR2 : Compare Register for Channel 2
bits : 0 - 14 (15 bit)
access : read-only


CR2S

Channel 2 Compare Shadow Value
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CR2S CR2S read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CR2S

CR2S : Shadow Compare Register for Channel 2
bits : 0 - 14 (15 bit)
access : read-write


CHC

Channel Control
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHC CHC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASE OCS1 OCS2 OCS3 OCS4

ASE : Asymmetric PWM mode Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Asymmetric PWM is disabled

#1 : value2

Asymmetric PWM is enabled

End of enumeration elements list.

OCS1 : Output selector for CCU8x.OUTy0
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

CC8yST1 signal path is connected to the CCU8x.OUTy0

#1 : value2

Inverted CC8yST1 signal path is connected to the CCU8x.OUTy0

End of enumeration elements list.

OCS2 : Output selector for CCU8x.OUTy1
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Inverted CC8yST1 signal path is connected to the CCU8x.OUTy1

#1 : value2

CC8yST1 signal path is connected to the CCU8x.OUTy1

End of enumeration elements list.

OCS3 : Output selector for CCU8x.OUTy2
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

CC8yST2 signal path is connected to the CCU8x.OUTy2

#1 : value2

Inverted CCST2 signal path is connected to the CCU8x.OUTy2

End of enumeration elements list.

OCS4 : Output selector for CCU8x.OUTy3
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Inverted CC8yST2 signal path is connected to the CCU8x.OUTy3

#1 : value2

CC8yST2 signal path is connected to the CCU8x.OUTy3

End of enumeration elements list.


DTC

Dead Time Control
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DTC DTC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DTE1 DTE2 DCEN1 DCEN2 DCEN3 DCEN4 DTCC

DTE1 : Dead Time Enable for Channel 1
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Dead Time for channel 1 is disabled

#1 : value2

Dead Time for channel 1 is enabled

End of enumeration elements list.

DTE2 : Dead Time Enable for Channel 2
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Dead Time for channel 2 is disabled

#1 : value2

Dead Time for channel 2 is enabled

End of enumeration elements list.

DCEN1 : Dead Time Enable for CC8yST1
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Dead Time for CC8yST1 path is disabled

#1 : value2

Dead Time for CC8yST1 path is enabled

End of enumeration elements list.

DCEN2 : Dead Time Enable for inverted CC8yST1
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Dead Time for inverted CC8yST1 path is disabled

#1 : value2

Dead Time for inverted CC8yST1 path is enabled

End of enumeration elements list.

DCEN3 : Dead Time Enable for CC8yST2
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Dead Time for CC8yST2 path is disabled

#1 : value2

Dead Time for CC8yST2 path is enabled

End of enumeration elements list.

DCEN4 : Dead Time Enable for inverted CC8yST2
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Dead Time for inverted CC8yST2 path is disabled

#1 : value2

Dead Time for inverted CC8yST2 path is enabled

End of enumeration elements list.

DTCC : Dead Time clock control
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

#00 : value1

ftclk

#01 : value2

ftclk/2

#10 : value3

ftclk/4

#11 : value4

ftclk/8

End of enumeration elements list.


DC1R

Channel 1 Dead Time Values
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DC1R DC1R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT1R DT1F

DT1R : Rise Value for Dead Time of Channel 1
bits : 0 - 6 (7 bit)
access : read-write

DT1F : Fall Value for Dead Time of Channel 1
bits : 8 - 14 (7 bit)
access : read-write


DC2R

Channel 2 Dead Time Values
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DC2R DC2R read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DT2R DT2F

DT2R : Rise Value for Dead Time of Channel 2
bits : 0 - 6 (7 bit)
access : read-write

DT2F : Fall Value for Dead Time of Channel 2
bits : 8 - 14 (7 bit)
access : read-write


TIMER

Timer Value
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TIMER TIMER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TVAL

TVAL : Timer Value
bits : 0 - 14 (15 bit)
access : read-write


C0V

Capture Register 0
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C0V C0V read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPTV FPCV FFL

CAPTV : Capture Value
bits : 0 - 14 (15 bit)
access : read-only

FPCV : Prescaler Value
bits : 16 - 18 (3 bit)
access : read-only

FFL : Full Flag
bits : 20 - 19 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new value was captured into the specific capture register

#1 : value2

A new value was captured into the specific register

End of enumeration elements list.


C1V

Capture Register 1
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C1V C1V read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPTV FPCV FFL

CAPTV : Capture Value
bits : 0 - 14 (15 bit)
access : read-only

FPCV : Prescaler Value
bits : 16 - 18 (3 bit)
access : read-only

FFL : Full Flag
bits : 20 - 19 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new value was captured into the specific capture register

#1 : value2

A new value was captured into the specific register

End of enumeration elements list.


C2V

Capture Register 2
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C2V C2V read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPTV FPCV FFL

CAPTV : Capture Value
bits : 0 - 14 (15 bit)
access : read-only

FPCV : Prescaler Value
bits : 16 - 18 (3 bit)
access : read-only

FFL : Full Flag
bits : 20 - 19 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new value was captured into the specific capture register

#1 : value2

A new value was captured into the specific register

End of enumeration elements list.


TCST

Slice Timer Status
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCST TCST read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRB CDIR DTR1 DTR2

TRB : Timer Run Bit
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Timer is stopped

#1 : value2

Timer is running

End of enumeration elements list.

CDIR : Timer Counting Direction
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : value1

Timer is counting up

#1 : value2

Timer is counting down

End of enumeration elements list.

DTR1 : Dead Time Counter 1 Run bit
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : value1

Dead Time counter is idle

#1 : value2

Dead Time counter is running

End of enumeration elements list.

DTR2 : Dead Time Counter 2 Run bit
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : value1

Dead Time counter is idle

#1 : value2

Dead Time counter is running

End of enumeration elements list.


C3V

Capture Register 3
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

C3V C3V read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CAPTV FPCV FFL

CAPTV : Capture Value
bits : 0 - 14 (15 bit)
access : read-only

FPCV : Prescaler Value
bits : 16 - 18 (3 bit)
access : read-only

FFL : Full Flag
bits : 20 - 19 (0 bit)
access : read-only

Enumeration:

#0 : value1

No new value was captured into the specific capture register

#1 : value2

A new value was captured into the specific register

End of enumeration elements list.


INTS

Interrupt Status
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTS INTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMUS OMDS CMU1S CMD1S CMU2S CMD2S E0AS E1AS E2AS TRPF

PMUS : Period Match while Counting Up
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Period match while counting up not detected

#1 : value2

Period match while counting up detected

End of enumeration elements list.

OMDS : One Match while Counting Down
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : value1

One match while counting down not detected

#1 : value2

One match while counting down detected

End of enumeration elements list.

CMU1S : Channel 1 Compare Match while Counting Up
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Compare match while counting up not detected

#1 : value2

Compare match while counting up detected

End of enumeration elements list.

CMD1S : Channel 1 Compare Match while Counting Down
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : value1

Compare match while counting down not detected

#1 : value2

Compare match while counting down detected

End of enumeration elements list.

CMU2S : Channel 2 Compare Match while Counting Up
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : value1

Compare match while counting up not detected

#1 : value2

Compare match while counting up detected

End of enumeration elements list.

CMD2S : Channel 2 Compare Match while Counting Down
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : value1

Compare match while counting down not detected

#1 : value2

Compare match while counting down detected

End of enumeration elements list.

E0AS : Event 0 Detection Status
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

Event 0 not detected

#1 : value2

Event 0 detected

End of enumeration elements list.

E1AS : Event 1 Detection Status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : value1

Event 1 not detected

#1 : value2

Event 1 detected

End of enumeration elements list.

E2AS : Event 2 Detection Status
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

#0 : value1

Event 2 not detected

#1 : value2

Event 2 detected

End of enumeration elements list.

TRPF : Trap Flag Status
bits : 11 - 10 (0 bit)
access : read-only


INTE

Interrupt Enable Control
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

INTE INTE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PME OME CMU1E CMD1E CMU2E CMD2E E0AE E1AE E2AE

PME : Period match while counting up enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Period Match interrupt is disabled

#1 : value2

Period Match interrupt is enabled

End of enumeration elements list.

OME : One match while counting down enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

One Match interrupt is disabled

#1 : value2

One Match interrupt is enabled

End of enumeration elements list.

CMU1E : Channel 1 Compare match while counting up enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Compare Match while counting up interrupt is disabled

#1 : value2

Compare Match while counting up interrupt is enabled

End of enumeration elements list.

CMD1E : Channel 1 Compare match while counting down enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Compare Match while counting down interrupt is disabled

#1 : value2

Compare Match while counting down interrupt is enabled

End of enumeration elements list.

CMU2E : Channel 2 Compare match while counting up enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Compare Match while counting up interrupt is disabled

#1 : value2

Compare Match while counting up interrupt is enabled

End of enumeration elements list.

CMD2E : Channel 2 Compare match while counting down enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Compare Match while counting down interrupt is disabled

#1 : value2

Compare Match while counting down interrupt is enabled

End of enumeration elements list.

E0AE : Event 0 interrupt enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

Event 0 detection interrupt is disabled

#1 : value2

Event 0 detection interrupt is enabled

End of enumeration elements list.

E1AE : Event 1 interrupt enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : value1

Event 1 detection interrupt is disabled

#1 : value2

Event 1 detection interrupt is enabled

End of enumeration elements list.

E2AE : Event 2 interrupt enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

Event 2 detection interrupt is disabled

#1 : value2

Event 2 detection interrupt is enabled

End of enumeration elements list.


SRS

Service Request Selector
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SRS SRS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 POSR CM1SR CM2SR E0SR E1SR E2SR

POSR : Period/One match Service request selector
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

#00 : value1

Forward to CC8ySR0

#01 : value2

Forward to CC8ySR1

#10 : value3

Forward to CC8ySR2

#11 : value4

Forward to CC8ySR3

End of enumeration elements list.

CM1SR : Channel 1 Compare match Service request selector
bits : 2 - 2 (1 bit)
access : read-write

Enumeration:

#00 : value1

Forward to CC8ySR0

#01 : value2

Forward to CC8ySR1

#10 : value3

Forward to CC8ySR2

#11 : value4

Forward to CC8ySR3

End of enumeration elements list.

CM2SR : Channel 2 Compare match Service request selector
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

#00 : value1

Forward to CC8ySR0

#01 : value2

Forward to CC8ySR1

#10 : value3

Forward to CC8ySR2

#11 : value4

Forward to CC8ySR3

End of enumeration elements list.

E0SR : Event 0 Service request selector
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

#00 : value1

Forward to CCvySR0

#01 : value2

Forward to CC8ySR1

#10 : value3

Forward to CC8ySR2

#11 : value4

Forward to CC8ySR3

End of enumeration elements list.

E1SR : Event 1 Service request selector
bits : 10 - 10 (1 bit)
access : read-write

Enumeration:

#00 : value1

Forward to CC8ySR0

#01 : value2

Forward to CC8ySR1

#10 : value3

Forward to CC8ySR2

#11 : value4

Forward to CC8ySR3

End of enumeration elements list.

E2SR : Event 2 Service request selector
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#00 : value1

Forward to CC8ySR0

#01 : value2

Forward to CCvySR1

#10 : value3

Forward to CC8ySR2

#11 : value4

Forward to CC8ySR3

End of enumeration elements list.


SWS

Interrupt Status Set
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWS SWS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SPM SOM SCM1U SCM1D SCM2U SCM2D SE0A SE1A SE2A STRPF

SPM : Period match while counting up set
bits : 0 - -1 (0 bit)
access : write-only

SOM : One match while counting down set
bits : 1 - 0 (0 bit)
access : write-only

SCM1U : Channel 1 Compare match while counting up set
bits : 2 - 1 (0 bit)
access : write-only

SCM1D : Channel 1 Compare match while counting down set
bits : 3 - 2 (0 bit)
access : write-only

SCM2U : Compare match while counting up set
bits : 4 - 3 (0 bit)
access : write-only

SCM2D : Compare match while counting down set
bits : 5 - 4 (0 bit)
access : write-only

SE0A : Event 0 detection set
bits : 8 - 7 (0 bit)
access : write-only

SE1A : Event 1 detection set
bits : 9 - 8 (0 bit)
access : write-only

SE2A : Event 2 detection set
bits : 10 - 9 (0 bit)
access : write-only

STRPF : Trap Flag status set
bits : 11 - 10 (0 bit)
access : write-only


SWR

Interrupt Status Clear
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SWR SWR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RPM ROM RCM1U RCM1D RCM2U RCM2D RE0A RE1A RE2A RTRPF

RPM : Period match while counting up clear
bits : 0 - -1 (0 bit)
access : write-only

ROM : One match while counting down clear
bits : 1 - 0 (0 bit)
access : write-only

RCM1U : Channel 1 Compare match while counting up clear
bits : 2 - 1 (0 bit)
access : write-only

RCM1D : Channel 1 Compare match while counting down clear
bits : 3 - 2 (0 bit)
access : write-only

RCM2U : Channel 2 Compare match while counting up clear
bits : 4 - 3 (0 bit)
access : write-only

RCM2D : Channel 2 Compare match while counting down clear
bits : 5 - 4 (0 bit)
access : write-only

RE0A : Event 0 detection clear
bits : 8 - 7 (0 bit)
access : write-only

RE1A : Event 1 detection clear
bits : 9 - 8 (0 bit)
access : write-only

RE2A : Event 2 detection clear
bits : 10 - 9 (0 bit)
access : write-only

RTRPF : Trap Flag status clear
bits : 11 - 10 (0 bit)
access : write-only


TCSET

Slice Timer Run Set
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TCSET TCSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRBS

TRBS : Timer Run Bit set
bits : 0 - -1 (0 bit)
access : write-only



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