\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
control register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EN : Enable
bits : 0 - 0 (1 bit)
ABORT : Abort request
bits : 1 - 1 (1 bit)
DMAEN : DMA enable
bits : 2 - 2 (1 bit)
TCEN : Timeout counter enable
bits : 3 - 3 (1 bit)
DQM : Dual-quad mode
bits : 6 - 6 (1 bit)
FSEL : FLASH memory selection
bits : 7 - 7 (1 bit)
FTHRES : IFO threshold level
bits : 8 - 12 (5 bit)
TEIE : Transfer error interrupt enable
bits : 16 - 16 (1 bit)
TCIE : Transfer complete interrupt enable
bits : 17 - 17 (1 bit)
FTIE : FIFO threshold interrupt enable
bits : 18 - 18 (1 bit)
SMIE : Status match interrupt enable
bits : 19 - 19 (1 bit)
TOIE : TimeOut interrupt enable
bits : 20 - 20 (1 bit)
APMS : Automatic poll mode stop
bits : 22 - 22 (1 bit)
PMM : Polling match mode
bits : 23 - 23 (1 bit)
FMODE : Functional mode
bits : 28 - 29 (2 bit)
device configuration register 3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CSBOUND : CS boundary
bits : 16 - 20 (5 bit)
communication configuration register
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMODE : Instruction mode
bits : 0 - 2 (3 bit)
IDTR : Instruction double transfer rate
bits : 3 - 3 (1 bit)
ISIZE : Instruction size
bits : 4 - 5 (2 bit)
ADMODE : Address mode
bits : 8 - 10 (3 bit)
ADDTR : Address double transfer rate
bits : 11 - 11 (1 bit)
ADSIZE : Address size
bits : 12 - 13 (2 bit)
ABMODE : Alternate byte mode
bits : 16 - 18 (3 bit)
ABDTR : Alternate bytes double transfer rate
bits : 19 - 19 (1 bit)
ABSIZE : Alternate bytes size
bits : 20 - 21 (2 bit)
DMODE : Data mode
bits : 24 - 26 (3 bit)
DDTR : Alternate bytes double transfer rate
bits : 27 - 27 (1 bit)
DQSE : DQS enable
bits : 29 - 29 (1 bit)
SIOO : Send instruction only once mode
bits : 31 - 31 (1 bit)
timing configuration register
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYC : Number of dummy cycles
bits : 0 - 4 (5 bit)
DHQC : Delay hold quarter cycle
bits : 28 - 28 (1 bit)
SSHIFT : Sample shift
bits : 30 - 30 (1 bit)
instruction register
address_offset : 0x110 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INSTRUCTION : INSTRUCTION
bits : 0 - 31 (32 bit)
alternate bytes register
address_offset : 0x120 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALTERNATE : Alternate bytes
bits : 0 - 31 (32 bit)
low-power timeout register
address_offset : 0x130 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TIMEOUT : Timeout period
bits : 0 - 15 (16 bit)
write communication configuration register
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IMODE : Instruction mode
bits : 0 - 2 (3 bit)
IDTR : Instruction double transfer rate
bits : 3 - 3 (1 bit)
ISIZE : Instruction size
bits : 4 - 5 (2 bit)
ADMODE : Address mode
bits : 8 - 10 (3 bit)
ADDTR : Address double transfer rate
bits : 11 - 11 (1 bit)
ADSIZE : Address size
bits : 12 - 13 (2 bit)
ABMODE : Alternate byte mode
bits : 16 - 18 (3 bit)
ABDTR : Alternate bytes double transfer rate
bits : 19 - 19 (1 bit)
ABSIZE : Alternate bytes size
bits : 20 - 21 (2 bit)
DMODE : Data mode
bits : 24 - 26 (3 bit)
DDTR : alternate bytes double transfer rate
bits : 27 - 27 (1 bit)
DQSE : DQS enable
bits : 29 - 29 (1 bit)
SIOO : Send instruction only once mode
bits : 31 - 31 (1 bit)
write timing configuration register
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DCYC : Number of dummy cycles
bits : 0 - 4 (5 bit)
write instruction register
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INSTRUCTION : INSTRUCTION
bits : 0 - 31 (32 bit)
write alternate bytes register
address_offset : 0x1A0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALTERNATE : Alternate bytes
bits : 0 - 31 (32 bit)
status register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TEF : Transfer error flag
bits : 0 - 0 (1 bit)
TCF : Transfer complete flag
bits : 1 - 1 (1 bit)
FTF : FIFO threshold flag
bits : 2 - 2 (1 bit)
SMF : Status match flag
bits : 3 - 3 (1 bit)
TOF : Timeout flag
bits : 4 - 4 (1 bit)
BUSY : BUSY
bits : 5 - 5 (1 bit)
FLEVEL : FIFO level
bits : 8 - 13 (6 bit)
HyperBusTM latency configuration register
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LM : Latency mode
bits : 0 - 0 (1 bit)
WZL : Write zero latency
bits : 1 - 1 (1 bit)
TACC : Access time
bits : 8 - 15 (8 bit)
TRWR : Read write recovery time
bits : 16 - 23 (8 bit)
flag clear register
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : write-only
reset_value : 0x0
reset_Mask : 0x0
CTEF : Clear transfer error flag
bits : 0 - 0 (1 bit)
CTCF : Clear transfer complete flag
bits : 1 - 1 (1 bit)
CSMF : Clear status match flag
bits : 3 - 3 (1 bit)
CTOF : Clear timeout flag
bits : 4 - 4 (1 bit)
HW configuration register
address_offset : 0x3F0 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
AXI : AXI interface
bits : 0 - 3 (4 bit)
FIFO : FIFO depth
bits : 4 - 11 (8 bit)
PRES : Prescaler
bits : 12 - 19 (8 bit)
IDL : ID Length
bits : 20 - 23 (4 bit)
MMW : Memory map write
bits : 24 - 27 (4 bit)
MST : Master
bits : 28 - 31 (4 bit)
version register
address_offset : 0x3F4 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
VER : Version
bits : 0 - 7 (8 bit)
identification
address_offset : 0x3F8 Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
ID : Identification
bits : 0 - 31 (32 bit)
magic ID
address_offset : 0x3FC Bytes (0x0)
size : 32 bit
access : read-only
reset_value : 0x0
reset_Mask : 0x0
MID : Magic ID
bits : 0 - 31 (32 bit)
data length register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DL : Data length
bits : 0 - 31 (32 bit)
address register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : ADDRESS
bits : 0 - 31 (32 bit)
data register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DATA : Data
bits : 0 - 31 (32 bit)
device configuration register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CKMODE : Mode 0 / mode 3
bits : 0 - 0 (1 bit)
FRCK : Free running clock
bits : 1 - 1 (1 bit)
CSHT : Chip-select high time
bits : 8 - 10 (3 bit)
DEVSIZE : Device size
bits : 16 - 20 (5 bit)
MTYP : Memory type
bits : 24 - 25 (2 bit)
polling status mask register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASK : Status mask
bits : 0 - 31 (32 bit)
polling status match register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MATCH : Status match
bits : 0 - 31 (32 bit)
polling interval register
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTERVAL : Polling interval
bits : 0 - 15 (16 bit)
device configuration register 2
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRESCALER : Clock prescaler
bits : 0 - 7 (8 bit)
WRAPSIZE : Wrap size
bits : 16 - 18 (3 bit)
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.