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PPB

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SYST_CSR

NVIC_ISER0

NVIC_ISER1

NVIC_ISER2

NVIC_ISER3

SYST_RVR

SYST_CVR

NVIC_ICER0

NVIC_ICER1

NVIC_ICER2

NVIC_ICER3

SYST_CALIB

NVIC_ISPR0

NVIC_ISPR1

NVIC_ISPR2

NVIC_ISPR3

NVIC_ICPR0

NVIC_ICPR1

NVIC_ICPR2

NVIC_ICPR3

NVIC_IABR0

NVIC_IABR1

NVIC_IABR2

NVIC_IABR3

NVIC_IPR0

NVIC_IPR1

NVIC_IPR2

NVIC_IPR3

NVIC_IPR4

NVIC_IPR5

NVIC_IPR6

NVIC_IPR7

NVIC_IPR8

NVIC_IPR9

NVIC_IPR10

NVIC_IPR11

NVIC_IPR12

NVIC_IPR13

NVIC_IPR14

NVIC_IPR15

NVIC_IPR16

NVIC_IPR17

NVIC_IPR18

NVIC_IPR19

NVIC_IPR20

NVIC_IPR21

NVIC_IPR22

NVIC_IPR23

NVIC_IPR24

NVIC_IPR25

NVIC_IPR26

NVIC_IPR27

ACTLR

CPUID

ICSR

VTOR

AIRCR

SCR

CCR

SHPR1

SHPR2

SHPR3

SHCSR

CFSR

HFSR

MMFAR

BFAR

AFSR

CPACR

MPU_TYPE

MPU_CTRL

MPU_RNR

MPU_RBAR

MPU_RASR

MPU_RBAR_A1

MPU_RASR_A1

MPU_RBAR_A2

MPU_RASR_A2

MPU_RBAR_A3

MPU_RASR_A3

STIR

FPCCR

FPCAR

FPDSCR


SYST_CSR

SysTick Control and Status Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYST_CSR SYST_CSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE TICKINT CLKSOURCE COUNTFLAG

ENABLE : Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

counter disabled

#1 : value2

counter enabled.

End of enumeration elements list.

TICKINT : Tick Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

counting down to zero does not assert the SysTick exception request

#1 : value2

counting down to zero to asserts the SysTick exception request.

End of enumeration elements list.

CLKSOURCE : Indicates the clock source:
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

external clock

#1 : value2

processor clock.

End of enumeration elements list.

COUNTFLAG : Counter Flag
bits : 16 - 15 (0 bit)
access : read-write


NVIC_ISER0

Interrupt Set-enable Register 0
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER0 NVIC_ISER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set-enable bits
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt disabled

#1 : value4

interrupt enabled.

End of enumeration elements list.


NVIC_ISER1

Interrupt Set-enable Register 1
address_offset : 0x104 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER1 NVIC_ISER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set-enable bits
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt disabled

#1 : value4

interrupt enabled.

End of enumeration elements list.


NVIC_ISER2

Interrupt Set-enable Register 2
address_offset : 0x108 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER2 NVIC_ISER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set-enable bits
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt disabled

#1 : value4

interrupt enabled.

End of enumeration elements list.


NVIC_ISER3

Interrupt Set-enable Register 3
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISER3 NVIC_ISER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETENA

SETENA : Interrupt set-enable bits
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt disabled

#1 : value4

interrupt enabled.

End of enumeration elements list.


SYST_RVR

SysTick Reload Value Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYST_RVR SYST_RVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RELOAD

RELOAD : Reload Value
bits : 0 - 22 (23 bit)
access : read-write


SYST_CVR

SysTick Current Value Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYST_CVR SYST_CVR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CURRENT

CURRENT : Current Value
bits : 0 - 22 (23 bit)
access : read-write


NVIC_ICER0

Interrupt Clear-enable Register 0
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER0 NVIC_ICER0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits.
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt disabled

#1 : value4

interrupt enabled.

End of enumeration elements list.


NVIC_ICER1

Interrupt Clear-enable Register 1
address_offset : 0x184 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER1 NVIC_ICER1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits.
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt disabled

#1 : value4

interrupt enabled.

End of enumeration elements list.


NVIC_ICER2

Interrupt Clear-enable Register 2
address_offset : 0x188 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER2 NVIC_ICER2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits.
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt disabled

#1 : value4

interrupt enabled.

End of enumeration elements list.


NVIC_ICER3

Interrupt Clear-enable Register 3
address_offset : 0x18C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICER3 NVIC_ICER3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRENA

CLRENA : Interrupt clear-enable bits.
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt disabled

#1 : value4

interrupt enabled.

End of enumeration elements list.


SYST_CALIB

SysTick Calibration Value Register r
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYST_CALIB SYST_CALIB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TENMS SKEW NOREF

TENMS : Ten Milliseconds Reload Value
bits : 0 - 22 (23 bit)
access : read-write

SKEW : Ten Milliseconds Skewed
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : value1

TENMS value is exact

#1 : value2

TENMS value is inexact, or not given.

End of enumeration elements list.

NOREF : No Reference Clock
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

reference clock provided

#1 : value2

no reference clock provided.

End of enumeration elements list.


NVIC_ISPR0

Interrupt Set-pending Register 0
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR0 NVIC_ISPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits.
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt is not pending

#1 : value4

interrupt is pending.

End of enumeration elements list.


NVIC_ISPR1

Interrupt Set-pending Register 1
address_offset : 0x204 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR1 NVIC_ISPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits.
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt is not pending

#1 : value4

interrupt is pending.

End of enumeration elements list.


NVIC_ISPR2

Interrupt Set-pending Register 2
address_offset : 0x208 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR2 NVIC_ISPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits.
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt is not pending

#1 : value4

interrupt is pending.

End of enumeration elements list.


NVIC_ISPR3

Interrupt Set-pending Register 3
address_offset : 0x20C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ISPR3 NVIC_ISPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SETPEND

SETPEND : Interrupt set-pending bits.
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt is not pending

#1 : value4

interrupt is pending.

End of enumeration elements list.


NVIC_ICPR0

Interrupt Clear-pending Register 0
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR0 NVIC_ICPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt set-pending bits.
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt is not pending

#1 : value4

interrupt is pending.

End of enumeration elements list.


NVIC_ICPR1

Interrupt Clear-pending Register 1
address_offset : 0x284 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR1 NVIC_ICPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt set-pending bits.
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt is not pending

#1 : value4

interrupt is pending.

End of enumeration elements list.


NVIC_ICPR2

Interrupt Clear-pending Register 2
address_offset : 0x288 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR2 NVIC_ICPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt set-pending bits.
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt is not pending

#1 : value4

interrupt is pending.

End of enumeration elements list.


NVIC_ICPR3

Interrupt Clear-pending Register 3
address_offset : 0x28C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_ICPR3 NVIC_ICPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLRPEND

CLRPEND : Interrupt set-pending bits.
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value3

interrupt is not pending

#1 : value4

interrupt is pending.

End of enumeration elements list.


NVIC_IABR0

Interrupt Active Bit Register 0
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IABR0 NVIC_IABR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active flags:
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value1

interrupt not active

#1 : value2

interrupt active

End of enumeration elements list.


NVIC_IABR1

Interrupt Active Bit Register 1
address_offset : 0x304 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IABR1 NVIC_IABR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active flags:
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value1

interrupt not active

#1 : value2

interrupt active

End of enumeration elements list.


NVIC_IABR2

Interrupt Active Bit Register 2
address_offset : 0x308 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IABR2 NVIC_IABR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active flags:
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value1

interrupt not active

#1 : value2

interrupt active

End of enumeration elements list.


NVIC_IABR3

Interrupt Active Bit Register 3
address_offset : 0x30C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IABR3 NVIC_IABR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ACTIVE

ACTIVE : Interrupt active flags:
bits : 0 - 30 (31 bit)
access : read-write

Enumeration:

#0 : value1

interrupt not active

#1 : value2

interrupt active

End of enumeration elements list.


NVIC_IPR0

Interrupt Priority Register 0
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR0 NVIC_IPR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR1

Interrupt Priority Register 1
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR1 NVIC_IPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR2

Interrupt Priority Register 2
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR2 NVIC_IPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR3

Interrupt Priority Register 3
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR3 NVIC_IPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR4

Interrupt Priority Register 4
address_offset : 0x410 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR4 NVIC_IPR4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR5

Interrupt Priority Register 5
address_offset : 0x414 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR5 NVIC_IPR5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR6

Interrupt Priority Register 6
address_offset : 0x418 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR6 NVIC_IPR6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR7

Interrupt Priority Register 7
address_offset : 0x41C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR7 NVIC_IPR7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR8

Interrupt Priority Register 8
address_offset : 0x420 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR8 NVIC_IPR8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR9

Interrupt Priority Register 9
address_offset : 0x424 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR9 NVIC_IPR9 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR10

Interrupt Priority Register 10
address_offset : 0x428 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR10 NVIC_IPR10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR11

Interrupt Priority Register 11
address_offset : 0x42C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR11 NVIC_IPR11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR12

Interrupt Priority Register 12
address_offset : 0x430 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR12 NVIC_IPR12 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR13

Interrupt Priority Register 13
address_offset : 0x434 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR13 NVIC_IPR13 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR14

Interrupt Priority Register 14
address_offset : 0x438 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR14 NVIC_IPR14 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR15

Interrupt Priority Register 15
address_offset : 0x43C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR15 NVIC_IPR15 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR16

Interrupt Priority Register 16
address_offset : 0x440 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR16 NVIC_IPR16 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR17

Interrupt Priority Register 17
address_offset : 0x444 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR17 NVIC_IPR17 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR18

Interrupt Priority Register 18
address_offset : 0x448 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR18 NVIC_IPR18 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR19

Interrupt Priority Register 19
address_offset : 0x44C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR19 NVIC_IPR19 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR20

Interrupt Priority Register 20
address_offset : 0x450 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR20 NVIC_IPR20 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR21

Interrupt Priority Register 21
address_offset : 0x454 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR21 NVIC_IPR21 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR22

Interrupt Priority Register 22
address_offset : 0x458 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR22 NVIC_IPR22 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR23

Interrupt Priority Register 23
address_offset : 0x45C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR23 NVIC_IPR23 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR24

Interrupt Priority Register 24
address_offset : 0x460 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR24 NVIC_IPR24 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR25

Interrupt Priority Register 25
address_offset : 0x464 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR25 NVIC_IPR25 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR26

Interrupt Priority Register 26
address_offset : 0x468 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR26 NVIC_IPR26 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


NVIC_IPR27

Interrupt Priority Register 27
address_offset : 0x46C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

NVIC_IPR27 NVIC_IPR27 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_0 PRI_1 PRI_2 PRI_3

PRI_0 : Priority value 0
bits : 0 - 6 (7 bit)
access : read-write

PRI_1 : Priority value 1
bits : 8 - 14 (7 bit)
access : read-write

PRI_2 : Priority value 2
bits : 16 - 22 (7 bit)
access : read-write

PRI_3 : Priority value 3
bits : 24 - 30 (7 bit)
access : read-write


ACTLR

Auxiliary Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ACTLR ACTLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DISMCYCINT DISDEFWBUF DISFOLD DISFPCA DISOOFP

DISMCYCINT : Disable load/store multiple
bits : 0 - -1 (0 bit)
access : read-write

DISDEFWBUF : Disable write buffer
bits : 1 - 0 (0 bit)
access : read-write

DISFOLD : Disable IT folding
bits : 2 - 1 (0 bit)
access : read-write

DISFPCA : Disable FPCA update
bits : 8 - 7 (0 bit)
access : read-write

DISOOFP : Disable out of order FP execution
bits : 9 - 8 (0 bit)
access : read-write


CPUID

CPUID Base Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPUID CPUID read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Revision PartNo Constant Variant Implementer

Revision : Revision number
bits : 0 - 2 (3 bit)
access : read-only

Enumeration:

0x1 : value1

Patch 1

End of enumeration elements list.

PartNo : Part number of the processor
bits : 4 - 14 (11 bit)
access : read-only

Enumeration:

0xC24 : value1

Cortex-M4

End of enumeration elements list.

Constant : Reads as 0xF
bits : 16 - 18 (3 bit)
access : read-only

Variant : Variant number
bits : 20 - 22 (3 bit)
access : read-only

Enumeration:

0x0 : value1

Revision 0

End of enumeration elements list.

Implementer : Implementer code
bits : 24 - 30 (7 bit)
access : read-only

Enumeration:

0x41 : value1

ARM

End of enumeration elements list.


ICSR

Interrupt Control and State Register
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICSR ICSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTACTIVE RETTOBASE VECTPENDING ISRPENDING PENDSTCLR PENDSTSET PENDSVCLR PENDSVSET NMIPENDSET

VECTACTIVE : Active exception number
bits : 0 - 7 (8 bit)
access : read-only

Enumeration:

0x00 : value1

Thread mode

End of enumeration elements list.

RETTOBASE : Return to Base
bits : 11 - 10 (0 bit)
access : read-only

Enumeration:

#0 : value1

there are preempted active exceptions to execute

#1 : value2

there are no active exceptions, or the currently-executing exception is the only active exception.

End of enumeration elements list.

VECTPENDING : Vector Pending
bits : 12 - 16 (5 bit)
access : read-only

Enumeration:

0x0 : value1

no pending exceptions

End of enumeration elements list.

ISRPENDING : Interrupt pending flag
bits : 22 - 21 (0 bit)
access : read-only

Enumeration:

#0 : value1

interrupt not pending

#1 : value2

interrupt pending.

End of enumeration elements list.

PENDSTCLR : SysTick exception clear-pending bit
bits : 25 - 24 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

removes the pending state from the SysTick exception.

End of enumeration elements list.

PENDSTSET : SysTick exception set-pending bit
bits : 26 - 25 (0 bit)
access : read-write

Enumeration:

#0 : value1

no effect

#1 : value2

changes SysTick exception state to pending.

End of enumeration elements list.

PENDSVCLR : PendSV clear-pending bit
bits : 27 - 26 (0 bit)
access : write-only

Enumeration:

#0 : value1

no effect

#1 : value2

removes the pending state from the PendSV exception.

End of enumeration elements list.

PENDSVSET : PendSV set-pending bit: 0b0=no effect, 0b1=changes PendSV exception state to pending., 0b0=PendSV exception is not pending, 0b1=PendSV exception is pending.,
bits : 28 - 27 (0 bit)
access : read-write

NMIPENDSET : NMI set-pending bit: 0b0=no effect, 0b1=changes NMI exception state to pending., 0b0=NMI exception is not pending, 0b1=NMI exception is pending.,
bits : 31 - 30 (0 bit)
access : read-write


VTOR

Vector Table Offset Register
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VTOR VTOR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TBLOFF

TBLOFF : Vector table base offset field
bits : 10 - 30 (21 bit)
access : read-write


AIRCR

Application Interrupt and Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AIRCR AIRCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTRESET VECTCLRACTIVE SYSRESETREQ PRIGROUP ENDIANNESS VECTKEY

VECTRESET : Reserved for Debug use.
bits : 0 - -1 (0 bit)
access : write-only

VECTCLRACTIVE : Reserved for Debug use.
bits : 1 - 0 (0 bit)
access : write-only

SYSRESETREQ : System reset request
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

no system reset request

#1 : value2

asserts a signal to the outer system that requests a reset.

End of enumeration elements list.

PRIGROUP : Interrupt priority grouping field
bits : 8 - 9 (2 bit)
access : read-write

ENDIANNESS : Data endianness bit
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

#0 : value1

Little-endian

#1 : value2

Big-endian.

End of enumeration elements list.

VECTKEY : Register key
bits : 16 - 30 (15 bit)
access : read-write


SCR

System Control Register
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCR SCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLEEPONEXIT SLEEPDEEP SEVONPEND

SLEEPONEXIT : Sleep on Exit
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

do not sleep when returning to Thread mode.

#1 : value2

enter sleep, or deep sleep, on return from an ISR.

End of enumeration elements list.

SLEEPDEEP : Sleep or Deep Sleep
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

sleep

#1 : value2

deep sleep

End of enumeration elements list.

SEVONPEND : Send Event on Pending bit:
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded

#1 : value2

enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

End of enumeration elements list.


CCR

Configuration and Control Register
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CCR CCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NONBASETHRDENA USERSETMPEND UNALIGN_TRP DIV_0_TRP BFHFNMIGN STKALIGN

NONBASETHRDENA : Non Base Thread Mode Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

processor can enter Thread mode only when no exception is active.

#1 : value2

processor can enter Thread mode from any level under the control of an EXC_RETURN value, see Exception returnException return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC:an LDM or POP instruction that loads the PCan LDR instruction with PC as the destinationa BX instruction using any register.EXC_RETURN is the value loaded into the LR on exception entry. The exception mechanism relies on this value to detect when the processor has completed an exception handler. The lowest five bits of this value provide information on the return stack and processor mode. shows the EXC_RETURN values with a description of the exception return behavior. All EXC_RETURN values have bits[31:5] set to one. When this value is loaded into the PC it indicates to the processor that the exception is complete, and the processor initiates the appropriate exception return sequence.Exception return behaviorEXC_RETURN[31:0]Description 0xFFFFFFF1 Return to Handler mode, exception return uses non-floating-point state from the MSP and execution uses MSP after return. 0xFFFFFFF9 Return to Thread mode, exception return uses non-floating-point state from MSP and execution uses MSP after return. 0xFFFFFFFD Return to Thread mode, exception return uses non-floating-point state from the PSP and execution uses PSP after return. 0xFFFFFFE1 Return to Handler mode, exception return uses floating-point-state from MSP and execution uses MSP after return. 0xFFFFFFE9 Return to Thread mode, exception return uses floating-point state from MSP and execution uses MSP after return. 0xFFFFFFED Return to Thread mode, exception return uses floating-point state from PSP and execution uses PSP after return. .

End of enumeration elements list.

USERSETMPEND : User Set Pending Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

disable

#1 : value2

enable

End of enumeration elements list.

UNALIGN_TRP : Unaligned Access Trap Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

do not trap unaligned halfword and word accesses

#1 : value2

trap unaligned halfword and word accesses.

End of enumeration elements list.

DIV_0_TRP : Divide by Zero Trap Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

do not trap divide by 0

#1 : value2

trap divide by 0.

End of enumeration elements list.

BFHFNMIGN : Bus Fault Hard Fault and NMI Ignore
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

data bus faults caused by load and store instructions cause a lock-up

#1 : value2

handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions.

End of enumeration elements list.

STKALIGN : Stack Alignment
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : value1

4-byte aligned

#1 : value2

8-byte aligned.

End of enumeration elements list.


SHPR1

System Handler Priority Register 1
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR1 SHPR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_4 PRI_5 PRI_6

PRI_4 : Priority of system handler 4, MemManage
bits : 0 - 6 (7 bit)
access : read-write

PRI_5 : Priority of system handler 5, BusFault
bits : 8 - 14 (7 bit)
access : read-write

PRI_6 : Priority of system handler 6, UsageFault
bits : 16 - 22 (7 bit)
access : read-write


SHPR2

System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR2 SHPR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_11

PRI_11 : Priority of system handler 11, SVCall
bits : 24 - 30 (7 bit)
access : read-write


SHPR3

System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHPR3 SHPR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRI_14 PRI_15

PRI_14 : Priority of system handler 14
bits : 16 - 22 (7 bit)
access : read-write

PRI_15 : Priority of system handler 15
bits : 24 - 30 (7 bit)
access : read-write


SHCSR

System Handler Control and State Register
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SHCSR SHCSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEMFAULTACT BUSFAULTACT USGFAULTACT SVCALLACT MONITORACT PENDSVACT SYSTICKACT USGFAULTPENDED MEMFAULTPENDED BUSFAULTPENDED SVCALLPENDED MEMFAULTENA BUSFAULTENA USGFAULTENA

MEMFAULTACT : MemManage exception active bit
bits : 0 - -1 (0 bit)
access : read-write

BUSFAULTACT : BusFault exception active bit
bits : 1 - 0 (0 bit)
access : read-write

USGFAULTACT : UsageFault exception active bit
bits : 3 - 2 (0 bit)
access : read-write

SVCALLACT : SVCall active bit
bits : 7 - 6 (0 bit)
access : read-write

MONITORACT : Debug monitor active bit
bits : 8 - 7 (0 bit)
access : read-write

PENDSVACT : PendSV exception active bit
bits : 10 - 9 (0 bit)
access : read-write

SYSTICKACT : SysTick exception active bit
bits : 11 - 10 (0 bit)
access : read-write

USGFAULTPENDED : UsageFault exception pending bit
bits : 12 - 11 (0 bit)
access : read-write

MEMFAULTPENDED : MemManage exception pending bit
bits : 13 - 12 (0 bit)
access : read-write

BUSFAULTPENDED : BusFault exception pending bit
bits : 14 - 13 (0 bit)
access : read-write

SVCALLPENDED : SVCall pending bit
bits : 15 - 14 (0 bit)
access : read-write

MEMFAULTENA : MemManage enable bit
bits : 16 - 15 (0 bit)
access : read-write

BUSFAULTENA : BusFault enable bit
bits : 17 - 16 (0 bit)
access : read-write

USGFAULTENA : UsageFault enable bit
bits : 18 - 17 (0 bit)
access : read-write


CFSR

Configurable Fault Status Register
address_offset : 0xD28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFSR CFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IACCVIOL DACCVIOL MUNSTKERR MSTKERR MLSPERR MMARVALID IBUSERR PRECISERR IMPRECISERR UNSTKERR STKERR LSPERR BFARVALID UNDEFINSTR INVSTATE INVPC NOCP UNALIGNED DIVBYZERO

IACCVIOL : Instruction access violation flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

no instruction access violation fault

#1 : value2

the processor attempted an instruction fetch from a location that does not permit execution.

End of enumeration elements list.

DACCVIOL : Data access violation flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

no data access violation fault

#1 : value2

the processor attempted a load or store at a location that does not permit the operation.

End of enumeration elements list.

MUNSTKERR : MemManage fault on unstacking for a return from exception
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

no unstacking fault

#1 : value2

unstack for an exception return has caused one or more access violations.

End of enumeration elements list.

MSTKERR : MemManage fault on stacking for exception entry
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

no stacking fault

#1 : value2

stacking for an exception entry has caused one or more access violations.

End of enumeration elements list.

MLSPERR : MemManage fault during floating point lazy state preservation
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

No MemManage fault occurred during floating-point lazy state preservation

#1 : value2

A MemManage fault occurred during floating-point lazy state preservation

End of enumeration elements list.

MMARVALID : MemManage Fault Address Register (MMFAR) valid flag
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

#0 : value1

value in MMAR is not a valid fault address

#1 : value2

MMAR holds a valid fault address.

End of enumeration elements list.

IBUSERR : Instruction bus error
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

no instruction bus error

#1 : value2

instruction bus error.

End of enumeration elements list.

PRECISERR : Precise data bus error
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : value1

no precise data bus error

#1 : value2

a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault.

End of enumeration elements list.

IMPRECISERR : Imprecise data bus error
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

no imprecise data bus error

#1 : value2

a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error.

End of enumeration elements list.

UNSTKERR : BusFault on unstacking for a return from exception
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

no unstacking fault

#1 : value2

stacking for an exception entry has caused one or more BusFaults.

End of enumeration elements list.

STKERR : BusFault on stacking for exception entry
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

#0 : value1

no stacking fault

#1 : value2

stacking for an exception entry has caused one or more BusFaults.

End of enumeration elements list.

LSPERR : BusFault during floating point lazy state preservation
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

#0 : value1

No bus fault occurred during floating-point lazy state preservation.

#1 : value2

A bus fault occurred during floating-point lazy state preservation

End of enumeration elements list.

BFARVALID : BusFault Address Register (BFAR) valid flag
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

#0 : value1

value in BFAR is not a valid fault address

#1 : value2

BFAR holds a valid fault address.

End of enumeration elements list.

UNDEFINSTR : Undefined instruction UsageFault
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

#0 : value1

no undefined instruction UsageFault

#1 : value2

the processor has attempted to execute an undefined instruction.

End of enumeration elements list.

INVSTATE : Invalid state UsageFault
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

#0 : value1

no invalid state UsageFault

#1 : value2

the processor has attempted to execute an instruction that makes illegal use of the EPSR.

End of enumeration elements list.

INVPC : Invalid PC load UsageFault
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

#0 : value1

no invalid PC load UsageFault

#1 : value2

the processor has attempted an illegal load of EXC_RETURN to the PC, as a result of an invalid context, or an invalid EXC_RETURN value.

End of enumeration elements list.

NOCP : No coprocessor UsageFault
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

#0 : value1

no UsageFault caused by attempting to access a coprocessor

#1 : value2

the processor has attempted to access a coprocessor.

End of enumeration elements list.

UNALIGNED : Unaligned access UsageFault
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

#0 : value1

no unaligned access fault, or unaligned access trapping not enabled

#1 : value2

the processor has made an unaligned memory access.

End of enumeration elements list.

DIVBYZERO : Divide by zero UsageFault
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

#0 : value1

no divide by zero fault, or divide by zero trapping not enabled

#1 : value2

the processor has executed an SDIV or UDIV instruction with a divisor of 0

End of enumeration elements list.


HFSR

HardFault Status Register
address_offset : 0xD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

HFSR HFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VECTTBL FORCED DEBUGEVT

VECTTBL : BusFault on vector table read
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

no BusFault on vector table read

#1 : value2

BusFault on vector table read

End of enumeration elements list.

FORCED : Forced HardFault
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : value1

no forced HardFault

#1 : value2

forced HardFault.

End of enumeration elements list.

DEBUGEVT : Reserved for Debug use
bits : 31 - 30 (0 bit)
access : read-write


MMFAR

MemManage Fault Address Register
address_offset : 0xD34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MMFAR MMFAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : Address causing the fault
bits : 0 - 30 (31 bit)
access : read-write


BFAR

BusFault Address Register
address_offset : 0xD38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BFAR BFAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : Address causing the fault
bits : 0 - 30 (31 bit)
access : read-write


AFSR

Auxiliary Fault Status Register
address_offset : 0xD3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AFSR AFSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VALUE

VALUE : Reserved
bits : 0 - 30 (31 bit)
access : read-write


CPACR

Coprocessor Access Control Register
address_offset : 0xD88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CPACR CPACR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CP10 CP11

CP10 : Access privileges for coprocessor 10
bits : 20 - 20 (1 bit)
access : read-write

Enumeration:

#00 : value1

Access denied. Any attempted access generates a NOCP UsageFault.

#01 : value2

Privileged access only. An unprivileged access generates a NOCP fault.

#11 : value4

Full access.

End of enumeration elements list.

CP11 : Access privileges for coprocessor 11
bits : 22 - 22 (1 bit)
access : read-write

Enumeration:

#00 : value1

Access denied. Any attempted access generates a NOCP UsageFault.

#01 : value2

Privileged access only. An unprivileged access generates a NOCP fault.

#11 : value4

Full access.

End of enumeration elements list.


MPU_TYPE

MPU Type Register
address_offset : 0xD90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_TYPE MPU_TYPE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEPARATE DREGION IREGION

SEPARATE : Support for unified or separate instruction and date memory maps
bits : 0 - -1 (0 bit)
access : read-only

DREGION : Number of supported MPU data regions
bits : 8 - 14 (7 bit)
access : read-only

IREGION : Number of supported MPU instruction regions
bits : 16 - 22 (7 bit)
access : read-only


MPU_CTRL

MPU Control Register
address_offset : 0xD94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_CTRL MPU_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE HFNMIENA PRIVDEFENA

ENABLE : Enable MPU
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

MPU disabled

#1 : value2

MPU enabled.

End of enumeration elements list.

HFNMIENA : Enable the operation of MPU during hard fault, NMI, and FAULTMASK handlers
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

MPU is disabled during hard fault, NMI, and FAULTMASK handlers, regardless of the value of the ENABLE bit

#1 : value2

the MPU is enabled during hard fault, NMI, and FAULTMASK handlers.

End of enumeration elements list.

PRIVDEFENA : Enables privileged software access to the default memory map
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault.

#1 : value2

If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.

End of enumeration elements list.


MPU_RNR

MPU Region Number Register
address_offset : 0xD98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_RNR MPU_RNR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION

REGION : Region
bits : 0 - 6 (7 bit)
access : read-write


MPU_RBAR

MPU Region Base Address Register
address_offset : 0xD9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_RBAR MPU_RBAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION VALID ADDR

REGION : MPU region field
bits : 0 - 2 (3 bit)
access : read-write

VALID : MPU Region Number valid bit
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field

#1 : value2

the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field.

End of enumeration elements list.

ADDR : Region base address field
bits : 9 - 30 (22 bit)
access : read-write


MPU_RASR

MPU Region Attribute and Size Register
address_offset : 0xDA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_RASR MPU_RASR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SIZE SRD B C S TEX AP XN

ENABLE : Region enable bit.
bits : 0 - -1 (0 bit)
access : read-write

SIZE : MPU protection region size
bits : 1 - 4 (4 bit)
access : read-write

SRD : Subregion disable bits
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

#0 : value1

corresponding sub-region is enabled

#1 : value2

corresponding sub-region is disabled

End of enumeration elements list.

B : Memory access attribute
bits : 16 - 15 (0 bit)
access : read-write

C : Memory access attribute
bits : 17 - 16 (0 bit)
access : read-write

S : Shareable bit
bits : 18 - 17 (0 bit)
access : read-write

TEX : Memory access attribute
bits : 19 - 20 (2 bit)
access : read-write

AP : Access permission field
bits : 24 - 25 (2 bit)
access : read-write

XN : Instruction access disable bit
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : value1

instruction fetches enabled

#1 : value2

instruction fetches disabled.

End of enumeration elements list.


MPU_RBAR_A1

MPU Region Base Address Register A1
address_offset : 0xDA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_RBAR_A1 MPU_RBAR_A1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION VALID ADDR

REGION : MPU region field
bits : 0 - 2 (3 bit)
access : read-write

VALID : MPU Region Number valid bit
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field

#1 : value2

the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field.

End of enumeration elements list.

ADDR : Region base address field
bits : 9 - 30 (22 bit)
access : read-write


MPU_RASR_A1

MPU Region Attribute and Size Register A1
address_offset : 0xDA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_RASR_A1 MPU_RASR_A1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SIZE SRD B C S TEX AP XN

ENABLE : Region enable bit.
bits : 0 - -1 (0 bit)
access : read-write

SIZE : MPU protection region size
bits : 1 - 4 (4 bit)
access : read-write

SRD : Subregion disable bits
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

#0 : value1

corresponding sub-region is enabled

#1 : value2

corresponding sub-region is disabled

End of enumeration elements list.

B : Memory access attribute
bits : 16 - 15 (0 bit)
access : read-write

C : Memory access attribute
bits : 17 - 16 (0 bit)
access : read-write

S : Shareable bit
bits : 18 - 17 (0 bit)
access : read-write

TEX : Memory access attribute
bits : 19 - 20 (2 bit)
access : read-write

AP : Access permission field
bits : 24 - 25 (2 bit)
access : read-write

XN : Instruction access disable bit
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : value1

instruction fetches enabled

#1 : value2

instruction fetches disabled.

End of enumeration elements list.


MPU_RBAR_A2

MPU Region Base Address Register A2
address_offset : 0xDAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_RBAR_A2 MPU_RBAR_A2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION VALID ADDR

REGION : MPU region field
bits : 0 - 2 (3 bit)
access : read-write

VALID : MPU Region Number valid bit
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field

#1 : value2

the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field.

End of enumeration elements list.

ADDR : Region base address field
bits : 9 - 30 (22 bit)
access : read-write


MPU_RASR_A2

MPU Region Attribute and Size Register A2
address_offset : 0xDB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_RASR_A2 MPU_RASR_A2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SIZE SRD B C S TEX AP XN

ENABLE : Region enable bit.
bits : 0 - -1 (0 bit)
access : read-write

SIZE : MPU protection region size
bits : 1 - 4 (4 bit)
access : read-write

SRD : Subregion disable bits
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

#0 : value1

corresponding sub-region is enabled

#1 : value2

corresponding sub-region is disabled

End of enumeration elements list.

B : Memory access attribute
bits : 16 - 15 (0 bit)
access : read-write

C : Memory access attribute
bits : 17 - 16 (0 bit)
access : read-write

S : Shareable bit
bits : 18 - 17 (0 bit)
access : read-write

TEX : Memory access attribute
bits : 19 - 20 (2 bit)
access : read-write

AP : Access permission field
bits : 24 - 25 (2 bit)
access : read-write

XN : Instruction access disable bit
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : value1

instruction fetches enabled

#1 : value2

instruction fetches disabled.

End of enumeration elements list.


MPU_RBAR_A3

MPU Region Base Address Register A3
address_offset : 0xDB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_RBAR_A3 MPU_RBAR_A3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 REGION VALID ADDR

REGION : MPU region field
bits : 0 - 2 (3 bit)
access : read-write

VALID : MPU Region Number valid bit
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

MPU_RNR not changed, and the processor: - updates the base address for the region specified in the MPU_RNR - ignores the value of the REGION field

#1 : value2

the processor: - updates the value of the MPU_RNR to the value of the REGION field - updates the base address for the region specified in the REGION field.

End of enumeration elements list.

ADDR : Region base address field
bits : 9 - 30 (22 bit)
access : read-write


MPU_RASR_A3

MPU Region Attribute and Size Register A3
address_offset : 0xDB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MPU_RASR_A3 MPU_RASR_A3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE SIZE SRD B C S TEX AP XN

ENABLE : Region enable bit.
bits : 0 - -1 (0 bit)
access : read-write

SIZE : MPU protection region size
bits : 1 - 4 (4 bit)
access : read-write

SRD : Subregion disable bits
bits : 8 - 14 (7 bit)
access : read-write

Enumeration:

#0 : value1

corresponding sub-region is enabled

#1 : value2

corresponding sub-region is disabled

End of enumeration elements list.

B : Memory access attribute
bits : 16 - 15 (0 bit)
access : read-write

C : Memory access attribute
bits : 17 - 16 (0 bit)
access : read-write

S : Shareable bit
bits : 18 - 17 (0 bit)
access : read-write

TEX : Memory access attribute
bits : 19 - 20 (2 bit)
access : read-write

AP : Access permission field
bits : 24 - 25 (2 bit)
access : read-write

XN : Instruction access disable bit
bits : 28 - 27 (0 bit)
access : read-write

Enumeration:

#0 : value1

instruction fetches enabled

#1 : value2

instruction fetches disabled.

End of enumeration elements list.


STIR

Software Trigger Interrupt Register
address_offset : 0xF00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STIR STIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INTID

INTID : Interrupt ID of the interrupt to trigger
bits : 0 - 7 (8 bit)
access : write-only


FPCCR

Floating-point Context Control Register
address_offset : 0xF34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPCCR FPCCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LSPACT USER THREAD HFRDY MMRDY BFRDY MONRDY LSPEN ASPEN

LSPACT : Lazy State Preservation Active
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Lazy state preservation is not active.

#1 : value2

Lazy state preservation is active. floating-point stack frame has been allocated but saving state to it has been deferred.

End of enumeration elements list.

USER : User allocated Stack Frame
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Privilege level was not user when the floating-point stack frame was allocated.

#1 : value2

Privilege level was user when the floating-point stack frame was allocated.

End of enumeration elements list.

THREAD : Thread Mode allocated Stack Frame
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Mode was not Thread Mode when the floating-point stack frame was allocated.

#1 : value2

Mode was Thread Mode when the floating-point stack frame was allocated.

End of enumeration elements list.

HFRDY : HardFault Ready
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

Priority did not permit setting the HardFault handler to the pending state when the floating-point stack frame was allocated.

#1 : value2

Priority permitted setting the HardFault handler to the pending state when the floating-point stack frame was allocated.

End of enumeration elements list.

MMRDY : MemManage Ready
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

MemManage is disabled or priority did not permit setting the MemManage handler to the pending state when the floating-point stack frame was allocated.

#1 : value2

MemManage is enabled and priority permitted setting the MemManage handler to the pending state when the floating-point stack frame was allocated.

End of enumeration elements list.

BFRDY : BusFault Ready
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

#0 : value1

BusFault is disabled or priority did not permit setting the BusFault handler to the pending state when the floating-point stack frame was allocated.

#1 : value2

BusFault is enabled and priority permitted setting the BusFault handler to the pending state when the floating-point stack frame was allocated.

End of enumeration elements list.

MONRDY : Monitor Ready
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

Debug Monitor is disabled or priority did not permit setting MON_PEND when the floating-point stack frame was allocated.

#1 : value2

Debug Monitor is enabled and priority permits setting MON_PEND when the floating-point stack frame was allocated.

End of enumeration elements list.

LSPEN : Lazy State Preservation Enabled
bits : 30 - 29 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disable automatic lazy state preservation for floating-point context.

#1 : value2

Enable automatic lazy state preservation for floating-point context.

End of enumeration elements list.

ASPEN : Automatic State Preservation
bits : 31 - 30 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disable CONTROL setting on execution of a floating-point instruction.

#1 : value2

Enable CONTROL setting on execution of a floating-point instruction.

End of enumeration elements list.


FPCAR

Floating-point Context Address Register
address_offset : 0xF38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPCAR FPCAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ADDRESS

ADDRESS : Address
bits : 3 - 30 (28 bit)
access : read-write


FPDSCR

Floating-point Default Status Control Register
address_offset : 0xF3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

FPDSCR FPDSCR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RMode FZ DN AHP

RMode : Default value for FPSCR.RMode
bits : 22 - 22 (1 bit)
access : read-write

FZ : Default value for FPSCR.FZ
bits : 24 - 23 (0 bit)
access : read-write

DN : Default value for FPSCR.DN
bits : 25 - 24 (0 bit)
access : read-write

AHP : Default value for FPSCR.AHP
bits : 26 - 25 (0 bit)
access : read-write



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