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GPDMA

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x55 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SAR

CTLL

CTLH

CFGL

CFGH

DAR


SAR

Source Address Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SAR SAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SAR

SAR : Current Source Address of DMA transfer
bits : 0 - 30 (31 bit)
access : read-write


CTLL

Control Register Low
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLL CTLL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 INT_EN DST_TR_WIDTH SRC_TR_WIDTH DINC SINC DEST_MSIZE SRC_MSIZE TT_FC

INT_EN : Interrupt Enable Bit
bits : 0 - -1 (0 bit)
access : read-write

DST_TR_WIDTH : Destination Transfer Width
bits : 1 - 2 (2 bit)
access : read-write

SRC_TR_WIDTH : Source Transfer Width
bits : 4 - 5 (2 bit)
access : read-write

DINC : Destination Address Increment
bits : 7 - 7 (1 bit)
access : read-write

Enumeration:

#00 : value1

Increment

#01 : value2

Decrement

#10 : value3

No change

End of enumeration elements list.

SINC : Source Address Increment
bits : 9 - 9 (1 bit)
access : read-write

Enumeration:

#00 : value1

Increment

#01 : value2

Decrement

#10 : value3

No change

End of enumeration elements list.

DEST_MSIZE : Destination Burst Transaction Length
bits : 11 - 12 (2 bit)
access : read-write

SRC_MSIZE : Source Burst Transaction Length
bits : 14 - 15 (2 bit)
access : read-write

TT_FC : Transfer Type and Flow Control
bits : 20 - 21 (2 bit)
access : read-write


CTLH

Control Register High
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTLH CTLH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BLOCK_TS DONE

BLOCK_TS : Block Transfer Size
bits : 0 - 10 (11 bit)
access : read-write

DONE : Done bit
bits : 12 - 11 (0 bit)
access : read-write


CFGL

Configuration Register Low
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGL CFGL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH_PRIOR CH_SUSP FIFO_EMPTY HS_SEL_DST HS_SEL_SRC LOCK_CH_L LOCK_B_L LOCK_CH LOCK_B DST_HS_POL SRC_HS_POL MAX_ABRST

CH_PRIOR : Channel priority
bits : 5 - 6 (2 bit)
access : read-write

CH_SUSP : Channel Suspend
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

Not suspended.

#1 : value2

Suspend DMA transfer from the source.

End of enumeration elements list.

FIFO_EMPTY : Indicates if there is data left in the channel FIFO
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#1 : value1

Channel FIFO empty

#0 : value2

Channel FIFO not empty

End of enumeration elements list.

HS_SEL_DST : Destination Software or Hardware Handshaking Select
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

Hardware handshaking interface. Software-initiated transaction requests are ignored.

#1 : value2

Software handshaking interface. Hardware- initiated transaction requests are ignored.

End of enumeration elements list.

HS_SEL_SRC : Source Software or Hardware Handshaking Select
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

#0 : value1

Hardware handshaking interface. Software-initiated transaction requests are ignored.

#1 : value2

Software handshaking interface. Hardware-initiated transaction requests are ignored.

End of enumeration elements list.

LOCK_CH_L : Channel Lock Level
bits : 12 - 12 (1 bit)
access : read-write

Enumeration:

#00 : value1

Over complete DMA transfer

#01 : value2

Over complete DMA block transfer

#10 : value3

Over complete DMA transaction

End of enumeration elements list.

LOCK_B_L : Bus Lock Level
bits : 14 - 14 (1 bit)
access : read-write

Enumeration:

#00 : value1

Over complete DMA transfer

#01 : value2

Over complete DMA block transfer

#10 : value3

Over complete DMA transaction

End of enumeration elements list.

LOCK_CH : Channel Lock Bit
bits : 16 - 15 (0 bit)
access : read-write

LOCK_B : Bus Lock Bit
bits : 17 - 16 (0 bit)
access : read-write

DST_HS_POL : Destination Handshaking Interface Polarity
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

#0 : value1

Active high

#1 : value2

Active low

End of enumeration elements list.

SRC_HS_POL : Source Handshaking Interface Polarity
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

#0 : value1

Active high

#1 : value2

Active low

End of enumeration elements list.

MAX_ABRST : Maximum AMBA Burst Length
bits : 20 - 28 (9 bit)
access : read-write


CFGH

Configuration Register High
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFGH CFGH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCMODE FIFO_MODE PROTCTL SRC_PER DEST_PER

FCMODE : Flow Control Mode
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Source transaction requests are serviced when they occur. Data pre-fetching is enabled.

#1 : value2

Source transaction requests are not serviced until a destination transaction request occurs. In this mode, the amount of data transferred from the source is limited so that it is guaranteed to be transferred to the destination prior to block termination by the destination. Data pre-fetching is disabled.

End of enumeration elements list.

FIFO_MODE : FIFO Mode Select
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Space/data available for single AHB transfer of the specified transfer width.

#1 : value2

Data available is greater than or equal to half the FIFO depth for destination transfers and space available is greater than half the fifo depth for source transfers. The exceptions are at the end of a burst transaction request or at the end of a block transfer.

End of enumeration elements list.

PROTCTL : Protection Control
bits : 2 - 3 (2 bit)
access : read-write

SRC_PER : Source Peripheral
bits : 7 - 9 (3 bit)
access : read-write

DEST_PER : Destination Peripheral
bits : 11 - 13 (3 bit)
access : read-write


DAR

Destination Address Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DAR DAR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DAR

DAR : Current Destination address of DMA transfer
bits : 0 - 30 (31 bit)
access : read-write



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