\n

FCE

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x20 byte (0x0)
mem_usage : registers
protection : not protected

Registers

IR

LENGTH

CHECK

CRC

CTR

RES

CFG

STS


IR

Input Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IR IR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IR

IR : Input Register
bits : 0 - 30 (31 bit)
access : read-write


LENGTH

CRC Length Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LENGTH LENGTH read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LENGTH

LENGTH : Message Length Register
bits : 0 - 14 (15 bit)
access : read-write


CHECK

CRC Check Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHECK CHECK read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHECK

CHECK : CHECK Register
bits : 0 - 30 (31 bit)
access : read-write


CRC

CRC Register
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CRC CRC read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRC

CRC : CRC Register
bits : 0 - 30 (31 bit)
access : read-write


CTR

CRC Test Register
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTR CTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FCM FRM_CFG FRM_CHECK

FCM : Force CRC Mismatch
bits : 0 - -1 (0 bit)
access : read-write

FRM_CFG : Force CFG Register Mismatch
bits : 1 - 0 (0 bit)
access : read-write

FRM_CHECK : Force Check Register Mismatch
bits : 2 - 1 (0 bit)
access : read-write


RES

CRC Result Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES RES read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RES

RES : Result Register
bits : 0 - 30 (31 bit)
access : read-only


CFG

CRC Configuration Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CFG CFG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMI CEI LEI BEI CCE ALR REFIN REFOUT XSEL

CMI : CRC Mismatch Interrupt
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

#0 : value1

CRC Mismatch Interrupt is disabled

#1 : value2

CRC Mismatch Interrupt is enabled

End of enumeration elements list.

CEI : Configuration Error Interrupt
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

#0 : value1

Configuration Error Interrupt is disabled

#1 : value2

Configuration Error Interrupt is enabled

End of enumeration elements list.

LEI : Length Error Interrupt
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

#0 : value1

Length Error Interrupt is disabled

#1 : value2

Length Error Interrupt is enabled

End of enumeration elements list.

BEI : Bus Error Interrupt
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

#0 : value1

Bus Error Interrupt is disabled

#1 : value2

Bus Error Interrupt is enabled

End of enumeration elements list.

CCE : CRC Check Comparison
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

#0 : value1

CRC check comparison at the end of a message is disabled

#1 : value2

CRC check comparison at the end of a message is enabled

End of enumeration elements list.

ALR : Automatic Length Reload
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

#0 : value1

Disables automatic reload of the LENGTH field.

#1 : value2

Enables automatic reload of the LENGTH field at the end of a message.

End of enumeration elements list.

REFIN : IR Byte Wise Reflection
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

#0 : value1

IR Byte Wise Reflection is disabled

#1 : value2

IR Byte Wise Reflection is enabled

End of enumeration elements list.

REFOUT : CRC 32-Bit Wise Reflection
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

#0 : value1

CRC 32-bit wise is disabled

#1 : value2

CRC 32-bit wise is enabled

End of enumeration elements list.

XSEL : Selects the value to be xored with the final CRC
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

#0 : value1

0x00000000

#1 : value2

0xFFFFFFFF

End of enumeration elements list.


STS

CRC Status Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STS STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CMF CEF LEF BEF

CMF : CRC Mismatch Flag
bits : 0 - -1 (0 bit)
access : read-write

CEF : Configuration Error Flag
bits : 1 - 0 (0 bit)
access : read-write

LEF : Length Error Flag
bits : 2 - 1 (0 bit)
access : read-write

BEF : Bus Error Flag
bits : 3 - 2 (0 bit)
access : read-write



Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !

This website is sponsored by EmbeetleEmbeetle, an IDE designed from scratch for embedded software developers.