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SCU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected

Registers

RSTSTAT

PRSET0

PRCLR0

PRSTAT1

PRSET1

PRCLR1

PRSTAT2

PRSET2

PRCLR2

PRSTAT3

PRSET3

PRCLR3

RSTSET

RSTCLR

PRSTAT0


RSTSTAT

RCU Reset Status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTSTAT RSTSTAT read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSTSTAT HIBWK HIBRS LCKEN

RSTSTAT : Reset Status Information
bits : 0 - 6 (7 bit)
access : read-only

Enumeration:

#00000001 : value1

PORST reset

#00000010 : value2

SWD reset

#00000100 : value3

PV reset

#00001000 : value4

CPU system reset

#00010000 : value5

CPU lockup reset

#00100000 : value6

WDT reset

#10000000 : value8

Parity Error reset

End of enumeration elements list.

HIBWK : Hibernate Wake-up Status
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

No Wake-up

#1 : value2

Wake-up event

End of enumeration elements list.

HIBRS : Hibernate Reset Status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

LCKEN : Enable Lockup Status
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset by Lockup disabled

#1 : value2

Reset by Lockup enabled

End of enumeration elements list.


PRSET0

RCU Peripheral 0 Reset Set
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRSET0 PRSET0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VADCRS DSDRS CCU40RS CCU41RS CCU42RS CCU80RS CCU81RS POSIF0RS POSIF1RS USIC0RS ERU1RS

VADCRS : VADC Reset Assert
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

DSDRS : DSD Reset Assert
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

CCU40RS : CCU40 Reset Assert
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

CCU41RS : CCU41 Reset Assert
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

CCU42RS : CCU42 Reset Assert
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

CCU80RS : CCU80 Reset Assert
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

CCU81RS : CCU81 Reset Assert
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

POSIF0RS : POSIF0 Reset Assert
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

POSIF1RS : POSIF1 Reset Assert
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

USIC0RS : USIC0 Reset Assert
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

ERU1RS : ERU1 Reset Assert
bits : 16 - 15 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.


PRCLR0

RCU Peripheral 0 Reset Clear
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRCLR0 PRCLR0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VADCRS DSDRS CCU40RS CCU41RS CCU42RS CCU80RS CCU81RS POSIF0RS POSIF1RS USIC0RS ERU1RS

VADCRS : VADC Reset Clear
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

DSDRS : DSD Reset Clear
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

CCU40RS : CCU40 Reset Clear
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

CCU41RS : CCU41 Reset Clear
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

CCU42RS : CCU42 Reset Clear
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

CCU80RS : CCU80 Reset Clear
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

CCU81RS : CCU81 Reset Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

POSIF0RS : POSIF0 Reset Clear
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

POSIF1RS : POSIF1 Reset Clear
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

USIC0RS : USIC0 Reset Clear
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

ERU1RS : ERU1 Reset Clear
bits : 16 - 15 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.


PRSTAT1

RCU Peripheral 1 Reset Status
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRSTAT1 PRSTAT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCU43RS LEDTSCU0RS MCAN0RS DACRS MMCIRS USIC1RS USIC2RS PPORTSRS

CCU43RS : CCU43 Reset Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

LEDTSCU0RS : LEDTS Reset Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

MCAN0RS : MultiCAN Reset Status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

DACRS : DAC Reset Status
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

MMCIRS : MMC Interface Reset Status
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

USIC1RS : USIC1 Reset Status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

USIC2RS : USIC2 Reset Status
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

PPORTSRS : PORTS Reset Status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.


PRSET1

RCU Peripheral 1 Reset Set
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRSET1 PRSET1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCU43RS LEDTSCU0RS MCAN0RS DACRS MMCIRS USIC1RS USIC2RS PPORTSRS

CCU43RS : CCU43 Reset Assert
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

LEDTSCU0RS : LEDTS Reset Assert
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

MCAN0RS : MultiCAN Reset Assert
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

DACRS : DAC Reset Assert
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

MMCIRS : MMC Interface Reset Assert
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

USIC1RS : USIC1 Reset Assert
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

USIC2RS : USIC2 Reset Assert
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

PPORTSRS : PORTS Reset Assert
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.


PRCLR1

RCU Peripheral 1 Reset Clear
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRCLR1 PRCLR1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCU43RS LEDTSCU0RS MCAN0RS DACRS MMCIRS USIC1RS USIC2RS PPORTSRS

CCU43RS : CCU43 Reset Clear
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

LEDTSCU0RS : LEDTS Reset Clear
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

MCAN0RS : MultiCAN Reset Clear
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

DACRS : DAC Reset Clear
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

MMCIRS : MMC Interface Reset Clear
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

USIC1RS : USIC1 Reset Clear
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

USIC2RS : USIC2 Reset Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

PPORTSRS : PORTS Reset Clear
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.


PRSTAT2

RCU Peripheral 2 Reset Status
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRSTAT2 PRSTAT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTRS ETH0RS DMA0RS DMA1RS FCERS USBRS

WDTRS : WDT Reset Status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

ETH0RS : ETH0 Reset Status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

DMA0RS : DMA0 Reset Status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

DMA1RS : DMA1 Reset Status
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

FCERS : FCE Reset Status
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

USBRS : USB Reset Status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.


PRSET2

RCU Peripheral 2 Reset Set
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRSET2 PRSET2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTRS ETH0RS DMA0RS DMA1RS FCERS USBRS

WDTRS : WDT Reset Assert
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

ETH0RS : ETH0 Reset Assert
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

DMA0RS : DMA0 Reset Assert
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

DMA1RS : DMA1 Reset Assert
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

FCERS : FCE Reset Assert
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

USBRS : USB Reset Assert
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.


PRCLR2

RCU Peripheral 2 Reset Clear
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRCLR2 PRCLR2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTRS ETH0RS DMA0RS DMA1RS FCERS USBRS

WDTRS : WDT Reset Clear
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

ETH0RS : ETH0 Reset Clear
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

DMA0RS : DMA0 Reset Clear
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

DMA1RS : DMA1 Reset Clear
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

FCERS : FCE Reset Clear
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

USBRS : USB Reset Clear
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.


PRSTAT3

RCU Peripheral 3 Reset Status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRSTAT3 PRSTAT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EBURS

EBURS : EBU Reset Status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.


PRSET3

RCU Peripheral 3 Reset Set
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRSET3 PRSET3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EBURS

EBURS : EBU Reset Assert
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.


PRCLR3

RCU Peripheral 3 Reset Clear
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRCLR3 PRCLR3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EBURS

EBURS : EBU Reset Assert
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.


RSTSET

RCU Reset Set Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTSET RSTSET read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 HIBWK HIBRS LCKEN

HIBWK : Set Hibernate Wake-up Reset Status
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset status bit

End of enumeration elements list.

HIBRS : Set Hibernate Reset
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Assert reset

End of enumeration elements list.

LCKEN : Enable Lockup Reset
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Enable reset when Lockup gets asserted

End of enumeration elements list.


RSTCLR

RCU Reset Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RSTCLR RSTCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RSCLR HIBWK HIBRS LCKEN

RSCLR : Clear Reset Status
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Clears field RSTSTAT.RSTSTAT

End of enumeration elements list.

HIBWK : Clear Hibernate Wake-up Reset Status
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset status bit

End of enumeration elements list.

HIBRS : Clear Hibernate Reset
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

De-assert reset

End of enumeration elements list.

LCKEN : Enable Lockup Reset
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

#0 : value1

No effect

#1 : value2

Disable reset when Lockup gets asserted

End of enumeration elements list.


PRSTAT0

RCU Peripheral 0 Reset Status
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PRSTAT0 PRSTAT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VADCRS DSDRS CCU40RS CCU41RS CCU42RS CCU80RS CCU81RS POSIF0RS POSIF1RS USIC0RS ERU1RS

VADCRS : VADC Reset Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

DSDRS : DSD Reset Status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

CCU40RS : CCU40 Reset Status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

CCU41RS : CCU41 Reset Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

CCU42RS : CCU42 Reset Status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

CCU80RS : CCU80 Reset Status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

CCU81RS : CCU81 Reset Status
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

POSIF0RS : POSIF0 Reset Status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

POSIF1RS : POSIF1 Reset Status
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

USIC0RS : USIC0 Reset Status
bits : 11 - 10 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.

ERU1RS : ERU1 Reset Status
bits : 16 - 15 (0 bit)
access : read-only

Enumeration:

#0 : value1

Reset de-asserted

#1 : value2

Reset asserted

End of enumeration elements list.



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