Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
EBU Clock Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DISR : EBU Disable Request Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
EBU disable is not requested
#1 : value2
EBU disable is requested
End of enumeration elements list.
DISS : EBU Disable Status Bit
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
EBU is enabled (default after reset)
#1 : value2
EBU is disabled
End of enumeration elements list.
SYNC : EBU Clocking Mode
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
request EBU to run asynchronously to AHB bus clock and use separate clock source
#1 : value2
request EBU to run synchronously to ARM processor (default after reset)
End of enumeration elements list.
DIV2 : DIV2 Clocking Mode
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
standard clocking mode. clock input selected by SYNC bitfield (default after reset).
#1 : value2
request EBU to run off AHB bus clock divided by 2.
End of enumeration elements list.
EBUDIV : EBU Clock Divide Ratio
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#00 : value1
request EBU to run off input clock (default after reset)
#01 : value2
request EBU to run off input clock divided by 2
#10 : value3
request EBU to run off input clock divided by 3
#11 : value4
request EBU to run off input clock divided by 4
End of enumeration elements list.
SYNCACK : EBU Clocking Mode Status
bits : 20 - 19 (0 bit)
access : read-only
Enumeration:
#0 : value1
the EBU is asynchronous to the AHB bus clock and is using a separate clock source
#1 : value2
EBU is synchronous to the AHB bus clock (default after reset)
End of enumeration elements list.
DIV2ACK : DIV2 Clocking Mode Status
bits : 21 - 20 (0 bit)
access : read-only
Enumeration:
#0 : value1
EBU is using standard clocking mode. clock input selected by SYNC bitfield (default after reset).
#1 : value2
EBU is running off AHB bus clock divided by 2.
End of enumeration elements list.
EBUDIVACK : EBU Clock Divide Ratio Status
bits : 22 - 22 (1 bit)
access : read-only
Enumeration:
#00 : value1
EBU is running off input clock (default after reset)
#01 : value2
EBU is running off input clock divided by 2
#10 : value3
EBU is running off input clock divided by 3
#11 : value4
EBU is running off input clock divided by 4
End of enumeration elements list.
EBU Address Select Register 0
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGENAB : Memory Region Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Memory region is disabled (default after reset).
#1 : value2
Memory region is enabled.
End of enumeration elements list.
ALTENAB : Alternate Region Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Memory region is disabled (default after reset).
#1 : value2
Memory region is enabled.
End of enumeration elements list.
WPROT : Memory Region Write Protect
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Region is enabled for write accesses
#1 : value2
Region is write protected.
End of enumeration elements list.
EBU Address Select Register 1
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGENAB : Memory Region Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Memory region is disabled (default after reset).
#1 : value2
Memory region is enabled.
End of enumeration elements list.
ALTENAB : Alternate Region Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Memory region is disabled (default after reset).
#1 : value2
Memory region is enabled.
End of enumeration elements list.
WPROT : Memory Region Write Protect
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Region is enabled for write accesses
#1 : value2
Region is write protected.
End of enumeration elements list.
EBU Address Select Register 2
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGENAB : Memory Region Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Memory region is disabled (default after reset).
#1 : value2
Memory region is enabled.
End of enumeration elements list.
ALTENAB : Alternate Region Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Memory region is disabled (default after reset).
#1 : value2
Memory region is enabled.
End of enumeration elements list.
WPROT : Memory Region Write Protect
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Region is enabled for write accesses
#1 : value2
Region is write protected.
End of enumeration elements list.
EBU Address Select Register 3
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REGENAB : Memory Region Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Memory region is disabled (default after reset).
#1 : value2
Memory region is enabled.
End of enumeration elements list.
ALTENAB : Alternate Region Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
Memory region is disabled (default after reset).
#1 : value2
Memory region is enabled.
End of enumeration elements list.
WPROT : Memory Region Write Protect
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Region is enabled for write accesses
#1 : value2
Region is write protected.
End of enumeration elements list.
EBU Bus Configuration Register
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FETBLEN : Burst Length for Synchronous Burst
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
1 data access (default after reset).
#001 : value2
2 data accesses.
#010 : value3
4 data accesses.
#011 : value4
8 data accesses.
End of enumeration elements list.
FBBMSEL : Synchronous burst buffer mode select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Burst buffer length defined by value in FETBLEN (default after reset).
#1 : value2
Continuous mode. All data required for transaction is transferred in a single burst.
End of enumeration elements list.
BFSSS : Read Single Stage Synchronization:
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Two stages of synchronization used. (maximum margin)
#1 : value2
One stage of synchronization used. (minimum latency)
End of enumeration elements list.
FDBKEN : Burst FLASH Clock Feedback Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
BFCLK feedback not used.
#1 : value2
Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input.
End of enumeration elements list.
BFCMSEL : Burst Flash Clock Mode Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Burst Flash Clock runs continuously with values selected by this register
#1 : value2
Burst Flash Clock is disabled between accesses
End of enumeration elements list.
NAA : Enable flash non-array access workaround
bits : 7 - 6 (0 bit)
access : read-write
ECSE : Early Chip Select for Synchronous Burst
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
CS is delayed.
#1 : value2
CS is not delayed.
End of enumeration elements list.
EBSE : Early Burst Signal Enable for Synchronous Burst
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
ADV is delayed.
#1 : value2
ADV is not delayed.
End of enumeration elements list.
DBA : Disable Burst Address Wrapping
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction.
#1 : value2
Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device.
End of enumeration elements list.
WAITINV : Reversed polarity at WAIT
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
input at WAIT pin is active low (default after reset).
#1 : value2
input at WAIT pin is active high.
End of enumeration elements list.
BCGEN : Byte Control Signal Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#00 : value1
Byte control signals follow chip select timing.
#01 : value2
Byte control signals follow control signal timing (RD, RD/WR) (default after reset).
#10 : value3
Byte control signals follow write enable signal timing (RD/WR only).
End of enumeration elements list.
PORTW : Device Addressing Mode
bits : 22 - 22 (1 bit)
access : read-write
WAIT : External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,
bits : 24 - 24 (1 bit)
access : read-write
AAP : Asynchronous Address phase:
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : value1
Clock is enabled at beginning of access.
#1 : value2
Clock is enabled at after address phase.
End of enumeration elements list.
AGEN : Device Type for Region
bits : 28 - 30 (3 bit)
access : read-write
EBU Bus Read Access Parameter Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDDTACS : Recovery Cycles between Different Regions
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : value1
No Recovery Phase clock cycles available.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
RDRECOVC : Recovery Cycles after Read Accesses
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
No Recovery Phase clock cycles available.
#001 : value2
1 clock cycle selected.
#110 : value3
6 clock cycles selected.
#111 : value4
7 clock cycles selected.
End of enumeration elements list.
WAITRDC : Programmed Wait States for read accesses
bits : 7 - 10 (4 bit)
access : read-write
Enumeration:
#00000 : value1
1 wait state.
#00001 : value2
1 wait states.
#00010 : value3
2 wait state.
#11110 : value4
30 wait states.
#11111 : value5
31 wait states.
End of enumeration elements list.
DATAC : Data Hold Cycles for Read Accesses
bits : 12 - 14 (3 bit)
access : read-write
EXTCLOCK : Frequency of external clock at pin BFCLKO
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : value1
Equal to INT_CLK frequency.
#01 : value2
1/2 of INT_CLK frequency.
#10 : value3
1/3 of INT_CLK frequency.
#11 : value4
1/4 of INT_CLK frequency (default after reset).
End of enumeration elements list.
EXTDATA : Extended data
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#00 : value1
external memory outputs data every BFCLK cycle
#01 : value2
external memory outputs data every two BFCLK cycles
#10 : value3
external memory outputs data every four BFCLK cycles
#11 : value4
external memory outputs data every eight BFCLK cycles
End of enumeration elements list.
CMDDELAY : Command Delay Cycles
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
AHOLDC : Address Hold Cycles
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
ADDRC : Address Cycles
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#0000 : value1
1 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
EBU Bus Write Configuration Register
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FETBLEN : Burst Length for Synchronous Burst
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
1 data access (default after reset).
#001 : value2
2 data accesses.
#010 : value3
4 data accesses.
#011 : value4
8 data accesses.
End of enumeration elements list.
FBBMSEL : Synchronous burst buffer mode select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Burst buffer length defined by value in FETBLEN (default after reset).
#1 : value2
Continuous mode. All data required for transaction transferred in single burst
End of enumeration elements list.
NAA : Enable flash non-array access workaround
bits : 7 - 6 (0 bit)
access : read-only
ECSE : Early Chip Select for Synchronous Burst
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
CS is delayed.
#1 : value2
CS is not delayed.
End of enumeration elements list.
EBSE : Early Burst Signal Enable for Synchronous Burst
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
ADV is delayed.
#1 : value2
ADV is not delayed.
End of enumeration elements list.
WAITINV : Reversed polarity at WAIT
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
input at WAIT pin is active low (default after reset).
#1 : value2
input at WAIT pin is active high.
End of enumeration elements list.
BCGEN : Byte Control Signal Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#00 : value1
Byte control signals follow chip select timing.
#01 : value2
Byte control signals follow control signal timing (RD, RD/WR) (default after reset).
#10 : value3
Byte control signals follow write enable signal timing (RD/WR only).
End of enumeration elements list.
PORTW : Device Addressing Mode
bits : 22 - 22 (1 bit)
access : read-only
WAIT : External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,
bits : 24 - 24 (1 bit)
access : read-write
AAP : Asynchronous Address phase:
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : value1
Clock is enabled at beginning of access.
#1 : value2
Clock is enabled at after address phase.
End of enumeration elements list.
LOCKCS : Lock Chip Select
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : value1
Chip Select cannot be locked (default after reset).
#1 : value2
Chip Select will be automatically locked when written to from the processor data port.
End of enumeration elements list.
AGEN : Device Type for Region
bits : 28 - 30 (3 bit)
access : read-write
EBU Bus Write Access Parameter Register
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRDTACS : Recovery Cycles between Different Regions
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : value1
No Recovery Phase clock cycles available.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
WRRECOVC : Recovery Cycles after Write Accesses
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
No Recovery Phase clock cycles available.
#001 : value2
1 clock cycle selected.
#110 : value3
6 clock cycles selected.
#111 : value4
7 clock cycles selected.
End of enumeration elements list.
WAITWRC : Programmed Wait States for write accesses
bits : 7 - 10 (4 bit)
access : read-write
Enumeration:
#00000 : value1
1 wait state.
#00001 : value2
1 wait states.
#00010 : value3
2 wait state.
#11110 : value4
30 wait states.
#11111 : value5
31 wait states.
End of enumeration elements list.
DATAC : Data Hold Cycles for Write Accesses
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#0000 : value1
No Recovery Phase clock cycles available.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
EXTCLOCK : Frequency of external clock at pin BFCLKO
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : value1
Equal to INT_CLK frequency.
#01 : value2
1/2 of INT_CLK frequency.
#10 : value3
1/3 of INT_CLK frequency.
#11 : value4
1/4 of INT_CLK frequency (default after reset).
End of enumeration elements list.
EXTDATA : Extended data
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#00 : value1
external memory outputs data every BFCLK cycle
#01 : value2
external memory outputs data every two BFCLK cycles
#10 : value3
external memory outputs data every four BFCLK cycles
#11 : value4
external memory outputs data every eight BFCLK cycles
End of enumeration elements list.
CMDDELAY : Command Delay Cycles
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
AHOLDC : Address Hold Cycles
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
ADDRC : Address Cycles
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#0000 : value1
1 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
EBU Bus Configuration Register
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FETBLEN : Burst Length for Synchronous Burst
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
1 data access (default after reset).
#001 : value2
2 data accesses.
#010 : value3
4 data accesses.
#011 : value4
8 data accesses.
End of enumeration elements list.
FBBMSEL : Synchronous burst buffer mode select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Burst buffer length defined by value in FETBLEN (default after reset).
#1 : value2
Continuous mode. All data required for transaction is transferred in a single burst.
End of enumeration elements list.
BFSSS : Read Single Stage Synchronization:
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Two stages of synchronization used. (maximum margin)
#1 : value2
One stage of synchronization used. (minimum latency)
End of enumeration elements list.
FDBKEN : Burst FLASH Clock Feedback Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
BFCLK feedback not used.
#1 : value2
Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input.
End of enumeration elements list.
BFCMSEL : Burst Flash Clock Mode Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Burst Flash Clock runs continuously with values selected by this register
#1 : value2
Burst Flash Clock is disabled between accesses
End of enumeration elements list.
NAA : Enable flash non-array access workaround
bits : 7 - 6 (0 bit)
access : read-write
ECSE : Early Chip Select for Synchronous Burst
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
CS is delayed.
#1 : value2
CS is not delayed.
End of enumeration elements list.
EBSE : Early Burst Signal Enable for Synchronous Burst
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
ADV is delayed.
#1 : value2
ADV is not delayed.
End of enumeration elements list.
DBA : Disable Burst Address Wrapping
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction.
#1 : value2
Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device.
End of enumeration elements list.
WAITINV : Reversed polarity at WAIT
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
input at WAIT pin is active low (default after reset).
#1 : value2
input at WAIT pin is active high.
End of enumeration elements list.
BCGEN : Byte Control Signal Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#00 : value1
Byte control signals follow chip select timing.
#01 : value2
Byte control signals follow control signal timing (RD, RD/WR) (default after reset).
#10 : value3
Byte control signals follow write enable signal timing (RD/WR only).
End of enumeration elements list.
PORTW : Device Addressing Mode
bits : 22 - 22 (1 bit)
access : read-write
WAIT : External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,
bits : 24 - 24 (1 bit)
access : read-write
AAP : Asynchronous Address phase:
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : value1
Clock is enabled at beginning of access.
#1 : value2
Clock is enabled at after address phase.
End of enumeration elements list.
AGEN : Device Type for Region
bits : 28 - 30 (3 bit)
access : read-write
EBU Bus Read Access Parameter Register
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDDTACS : Recovery Cycles between Different Regions
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : value1
No Recovery Phase clock cycles available.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
RDRECOVC : Recovery Cycles after Read Accesses
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
No Recovery Phase clock cycles available.
#001 : value2
1 clock cycle selected.
#110 : value3
6 clock cycles selected.
#111 : value4
7 clock cycles selected.
End of enumeration elements list.
WAITRDC : Programmed Wait States for read accesses
bits : 7 - 10 (4 bit)
access : read-write
Enumeration:
#00000 : value1
1 wait state.
#00001 : value2
1 wait states.
#00010 : value3
2 wait state.
#11110 : value4
30 wait states.
#11111 : value5
31 wait states.
End of enumeration elements list.
DATAC : Data Hold Cycles for Read Accesses
bits : 12 - 14 (3 bit)
access : read-write
EXTCLOCK : Frequency of external clock at pin BFCLKO
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : value1
Equal to INT_CLK frequency.
#01 : value2
1/2 of INT_CLK frequency.
#10 : value3
1/3 of INT_CLK frequency.
#11 : value4
1/4 of INT_CLK frequency (default after reset).
End of enumeration elements list.
EXTDATA : Extended data
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#00 : value1
external memory outputs data every BFCLK cycle
#01 : value2
external memory outputs data every two BFCLK cycles
#10 : value3
external memory outputs data every four BFCLK cycles
#11 : value4
external memory outputs data every eight BFCLK cycles
End of enumeration elements list.
CMDDELAY : Command Delay Cycles
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
AHOLDC : Address Hold Cycles
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
ADDRC : Address Cycles
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#0000 : value1
1 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
EBU Configuration Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
STS : Memory Status Bit
bits : 0 - -1 (0 bit)
access : read-only
LCKABRT : Lock Abort
bits : 1 - 0 (0 bit)
access : read-only
SDTRI : SDRAM Tristate
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
SDRAM control signals are driven by the EBU when the EBU does not own the external bus. SDRAM cannot be shared.
#1 : value2
SDRAM control signals are tri-stated by the EBU when the EBU does not own the external bus. The SDRAM can be shared.
End of enumeration elements list.
EXTLOCK : External Bus Lock Control
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
External bus is not locked after the EBU gains ownership
#1 : value2
External bus is locked after the EBU gains ownership
End of enumeration elements list.
ARBSYNC : Arbitration Signal Synchronization Control
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
Arbitration inputs are synchronous
#1 : value2
Arbitration inputs are asynchronous
End of enumeration elements list.
ARBMODE : Arbitration Mode Selection
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : value1
No Bus arbitration mode selected
#01 : value2
Arbiter Mode arbitration mode selected
#10 : value3
Participant arbitration mode selected
#11 : value4
Sole Master arbitration mode selected
End of enumeration elements list.
TIMEOUTC : Bus Time-out Control
bits : 8 - 14 (7 bit)
access : read-write
Enumeration:
0x00 : value1
Time-out is disabled.
0x01 : value2
Time-out is generated after 1 8 clock cycles.
0xFF : value3
Time-out is generated after 255 8 clock cycles.
End of enumeration elements list.
LOCKTIMEOUT : Lock Timeout Counter Preload
bits : 16 - 22 (7 bit)
access : read-write
GLOBALCS : Global Chip Select Enable
bits : 24 - 26 (3 bit)
access : read-write
ACCSINH : Access Inhibit request
bits : 28 - 27 (0 bit)
access : read-write
ACCSINHACK : Access inhibit acknowledge
bits : 29 - 28 (0 bit)
access : read-only
ALE : ALE Mode
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#0 : value1
Output is ADV
#1 : value2
Output is ALE
End of enumeration elements list.
EBU Bus Write Configuration Register
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FETBLEN : Burst Length for Synchronous Burst
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
1 data access (default after reset).
#001 : value2
2 data accesses.
#010 : value3
4 data accesses.
#011 : value4
8 data accesses.
End of enumeration elements list.
FBBMSEL : Synchronous burst buffer mode select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Burst buffer length defined by value in FETBLEN (default after reset).
#1 : value2
Continuous mode. All data required for transaction transferred in single burst
End of enumeration elements list.
NAA : Enable flash non-array access workaround
bits : 7 - 6 (0 bit)
access : read-only
ECSE : Early Chip Select for Synchronous Burst
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
CS is delayed.
#1 : value2
CS is not delayed.
End of enumeration elements list.
EBSE : Early Burst Signal Enable for Synchronous Burst
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
ADV is delayed.
#1 : value2
ADV is not delayed.
End of enumeration elements list.
WAITINV : Reversed polarity at WAIT
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
input at WAIT pin is active low (default after reset).
#1 : value2
input at WAIT pin is active high.
End of enumeration elements list.
BCGEN : Byte Control Signal Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#00 : value1
Byte control signals follow chip select timing.
#01 : value2
Byte control signals follow control signal timing (RD, RD/WR) (default after reset).
#10 : value3
Byte control signals follow write enable signal timing (RD/WR only).
End of enumeration elements list.
PORTW : Device Addressing Mode
bits : 22 - 22 (1 bit)
access : read-only
WAIT : External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,
bits : 24 - 24 (1 bit)
access : read-write
AAP : Asynchronous Address phase:
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : value1
Clock is enabled at beginning of access.
#1 : value2
Clock is enabled at after address phase.
End of enumeration elements list.
LOCKCS : Lock Chip Select
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : value1
Chip Select cannot be locked (default after reset).
#1 : value2
Chip Select will be automatically locked when written to from the processor data port.
End of enumeration elements list.
AGEN : Device Type for Region
bits : 28 - 30 (3 bit)
access : read-write
EBU Bus Write Access Parameter Register
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRDTACS : Recovery Cycles between Different Regions
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : value1
No Recovery Phase clock cycles available.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
WRRECOVC : Recovery Cycles after Write Accesses
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
No Recovery Phase clock cycles available.
#001 : value2
1 clock cycle selected.
#110 : value3
6 clock cycles selected.
#111 : value4
7 clock cycles selected.
End of enumeration elements list.
WAITWRC : Programmed Wait States for write accesses
bits : 7 - 10 (4 bit)
access : read-write
Enumeration:
#00000 : value1
1 wait state.
#00001 : value2
1 wait states.
#00010 : value3
2 wait state.
#11110 : value4
30 wait states.
#11111 : value5
31 wait states.
End of enumeration elements list.
DATAC : Data Hold Cycles for Write Accesses
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#0000 : value1
No Recovery Phase clock cycles available.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
EXTCLOCK : Frequency of external clock at pin BFCLKO
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : value1
Equal to INT_CLK frequency.
#01 : value2
1/2 of INT_CLK frequency.
#10 : value3
1/3 of INT_CLK frequency.
#11 : value4
1/4 of INT_CLK frequency (default after reset).
End of enumeration elements list.
EXTDATA : Extended data
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#00 : value1
external memory outputs data every BFCLK cycle
#01 : value2
external memory outputs data every two BFCLK cycles
#10 : value3
external memory outputs data every four BFCLK cycles
#11 : value4
external memory outputs data every eight BFCLK cycles
End of enumeration elements list.
CMDDELAY : Command Delay Cycles
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
AHOLDC : Address Hold Cycles
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
ADDRC : Address Cycles
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#0000 : value1
1 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
EBU Bus Configuration Register
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FETBLEN : Burst Length for Synchronous Burst
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
1 data access (default after reset).
#001 : value2
2 data accesses.
#010 : value3
4 data accesses.
#011 : value4
8 data accesses.
End of enumeration elements list.
FBBMSEL : Synchronous burst buffer mode select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Burst buffer length defined by value in FETBLEN (default after reset).
#1 : value2
Continuous mode. All data required for transaction is transferred in a single burst.
End of enumeration elements list.
BFSSS : Read Single Stage Synchronization:
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Two stages of synchronization used. (maximum margin)
#1 : value2
One stage of synchronization used. (minimum latency)
End of enumeration elements list.
FDBKEN : Burst FLASH Clock Feedback Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
BFCLK feedback not used.
#1 : value2
Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input.
End of enumeration elements list.
BFCMSEL : Burst Flash Clock Mode Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Burst Flash Clock runs continuously with values selected by this register
#1 : value2
Burst Flash Clock is disabled between accesses
End of enumeration elements list.
NAA : Enable flash non-array access workaround
bits : 7 - 6 (0 bit)
access : read-write
ECSE : Early Chip Select for Synchronous Burst
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
CS is delayed.
#1 : value2
CS is not delayed.
End of enumeration elements list.
EBSE : Early Burst Signal Enable for Synchronous Burst
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
ADV is delayed.
#1 : value2
ADV is not delayed.
End of enumeration elements list.
DBA : Disable Burst Address Wrapping
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction.
#1 : value2
Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device.
End of enumeration elements list.
WAITINV : Reversed polarity at WAIT
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
input at WAIT pin is active low (default after reset).
#1 : value2
input at WAIT pin is active high.
End of enumeration elements list.
BCGEN : Byte Control Signal Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#00 : value1
Byte control signals follow chip select timing.
#01 : value2
Byte control signals follow control signal timing (RD, RD/WR) (default after reset).
#10 : value3
Byte control signals follow write enable signal timing (RD/WR only).
End of enumeration elements list.
PORTW : Device Addressing Mode
bits : 22 - 22 (1 bit)
access : read-write
WAIT : External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,
bits : 24 - 24 (1 bit)
access : read-write
AAP : Asynchronous Address phase:
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : value1
Clock is enabled at beginning of access.
#1 : value2
Clock is enabled at after address phase.
End of enumeration elements list.
AGEN : Device Type for Region
bits : 28 - 30 (3 bit)
access : read-write
EBU Bus Read Access Parameter Register
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDDTACS : Recovery Cycles between Different Regions
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : value1
No Recovery Phase clock cycles available.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
RDRECOVC : Recovery Cycles after Read Accesses
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
No Recovery Phase clock cycles available.
#001 : value2
1 clock cycle selected.
#110 : value3
6 clock cycles selected.
#111 : value4
7 clock cycles selected.
End of enumeration elements list.
WAITRDC : Programmed Wait States for read accesses
bits : 7 - 10 (4 bit)
access : read-write
Enumeration:
#00000 : value1
1 wait state.
#00001 : value2
1 wait states.
#00010 : value3
2 wait state.
#11110 : value4
30 wait states.
#11111 : value5
31 wait states.
End of enumeration elements list.
DATAC : Data Hold Cycles for Read Accesses
bits : 12 - 14 (3 bit)
access : read-write
EXTCLOCK : Frequency of external clock at pin BFCLKO
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : value1
Equal to INT_CLK frequency.
#01 : value2
1/2 of INT_CLK frequency.
#10 : value3
1/3 of INT_CLK frequency.
#11 : value4
1/4 of INT_CLK frequency (default after reset).
End of enumeration elements list.
EXTDATA : Extended data
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#00 : value1
external memory outputs data every BFCLK cycle
#01 : value2
external memory outputs data every two BFCLK cycles
#10 : value3
external memory outputs data every four BFCLK cycles
#11 : value4
external memory outputs data every eight BFCLK cycles
End of enumeration elements list.
CMDDELAY : Command Delay Cycles
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
AHOLDC : Address Hold Cycles
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
ADDRC : Address Cycles
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#0000 : value1
1 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
EBU Bus Write Configuration Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FETBLEN : Burst Length for Synchronous Burst
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
1 data access (default after reset).
#001 : value2
2 data accesses.
#010 : value3
4 data accesses.
#011 : value4
8 data accesses.
End of enumeration elements list.
FBBMSEL : Synchronous burst buffer mode select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Burst buffer length defined by value in FETBLEN (default after reset).
#1 : value2
Continuous mode. All data required for transaction transferred in single burst
End of enumeration elements list.
NAA : Enable flash non-array access workaround
bits : 7 - 6 (0 bit)
access : read-only
ECSE : Early Chip Select for Synchronous Burst
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
CS is delayed.
#1 : value2
CS is not delayed.
End of enumeration elements list.
EBSE : Early Burst Signal Enable for Synchronous Burst
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
ADV is delayed.
#1 : value2
ADV is not delayed.
End of enumeration elements list.
WAITINV : Reversed polarity at WAIT
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
input at WAIT pin is active low (default after reset).
#1 : value2
input at WAIT pin is active high.
End of enumeration elements list.
BCGEN : Byte Control Signal Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#00 : value1
Byte control signals follow chip select timing.
#01 : value2
Byte control signals follow control signal timing (RD, RD/WR) (default after reset).
#10 : value3
Byte control signals follow write enable signal timing (RD/WR only).
End of enumeration elements list.
PORTW : Device Addressing Mode
bits : 22 - 22 (1 bit)
access : read-only
WAIT : External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,
bits : 24 - 24 (1 bit)
access : read-write
AAP : Asynchronous Address phase:
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : value1
Clock is enabled at beginning of access.
#1 : value2
Clock is enabled at after address phase.
End of enumeration elements list.
LOCKCS : Lock Chip Select
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : value1
Chip Select cannot be locked (default after reset).
#1 : value2
Chip Select will be automatically locked when written to from the processor data port.
End of enumeration elements list.
AGEN : Device Type for Region
bits : 28 - 30 (3 bit)
access : read-write
EBU Bus Write Access Parameter Register
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRDTACS : Recovery Cycles between Different Regions
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : value1
No Recovery Phase clock cycles available.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
WRRECOVC : Recovery Cycles after Write Accesses
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
No Recovery Phase clock cycles available.
#001 : value2
1 clock cycle selected.
#110 : value3
6 clock cycles selected.
#111 : value4
7 clock cycles selected.
End of enumeration elements list.
WAITWRC : Programmed Wait States for write accesses
bits : 7 - 10 (4 bit)
access : read-write
Enumeration:
#00000 : value1
1 wait state.
#00001 : value2
1 wait states.
#00010 : value3
2 wait state.
#11110 : value4
30 wait states.
#11111 : value5
31 wait states.
End of enumeration elements list.
DATAC : Data Hold Cycles for Write Accesses
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#0000 : value1
No Recovery Phase clock cycles available.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
EXTCLOCK : Frequency of external clock at pin BFCLKO
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : value1
Equal to INT_CLK frequency.
#01 : value2
1/2 of INT_CLK frequency.
#10 : value3
1/3 of INT_CLK frequency.
#11 : value4
1/4 of INT_CLK frequency (default after reset).
End of enumeration elements list.
EXTDATA : Extended data
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#00 : value1
external memory outputs data every BFCLK cycle
#01 : value2
external memory outputs data every two BFCLK cycles
#10 : value3
external memory outputs data every four BFCLK cycles
#11 : value4
external memory outputs data every eight BFCLK cycles
End of enumeration elements list.
CMDDELAY : Command Delay Cycles
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
AHOLDC : Address Hold Cycles
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
ADDRC : Address Cycles
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#0000 : value1
1 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
EBU Bus Configuration Register
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FETBLEN : Burst Length for Synchronous Burst
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
1 data access (default after reset).
#001 : value2
2 data accesses.
#010 : value3
4 data accesses.
#011 : value4
8 data accesses.
End of enumeration elements list.
FBBMSEL : Synchronous burst buffer mode select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Burst buffer length defined by value in FETBLEN (default after reset).
#1 : value2
Continuous mode. All data required for transaction is transferred in a single burst.
End of enumeration elements list.
BFSSS : Read Single Stage Synchronization:
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
#0 : value1
Two stages of synchronization used. (maximum margin)
#1 : value2
One stage of synchronization used. (minimum latency)
End of enumeration elements list.
FDBKEN : Burst FLASH Clock Feedback Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
#0 : value1
BFCLK feedback not used.
#1 : value2
Incoming data and control signals (from the Burst FLASH device) are re-synchronized to the BFCLKI input.
End of enumeration elements list.
BFCMSEL : Burst Flash Clock Mode Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
#0 : value1
Burst Flash Clock runs continuously with values selected by this register
#1 : value2
Burst Flash Clock is disabled between accesses
End of enumeration elements list.
NAA : Enable flash non-array access workaround
bits : 7 - 6 (0 bit)
access : read-write
ECSE : Early Chip Select for Synchronous Burst
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
CS is delayed.
#1 : value2
CS is not delayed.
End of enumeration elements list.
EBSE : Early Burst Signal Enable for Synchronous Burst
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
ADV is delayed.
#1 : value2
ADV is not delayed.
End of enumeration elements list.
DBA : Disable Burst Address Wrapping
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
#0 : value1
Memory Controller automatically re-aligns any non-aligned synchronous burst access so that data can be fetched from the device in a single burst transaction.
#1 : value2
Memory Controller always starts any burst access to a synchronous burst device at the address specified by the AHB request. Any required address wrapping must be automatically provided by the Burst FLASH device.
End of enumeration elements list.
WAITINV : Reversed polarity at WAIT
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
input at WAIT pin is active low (default after reset).
#1 : value2
input at WAIT pin is active high.
End of enumeration elements list.
BCGEN : Byte Control Signal Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#00 : value1
Byte control signals follow chip select timing.
#01 : value2
Byte control signals follow control signal timing (RD, RD/WR) (default after reset).
#10 : value3
Byte control signals follow write enable signal timing (RD/WR only).
End of enumeration elements list.
PORTW : Device Addressing Mode
bits : 22 - 22 (1 bit)
access : read-write
WAIT : External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,
bits : 24 - 24 (1 bit)
access : read-write
AAP : Asynchronous Address phase:
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : value1
Clock is enabled at beginning of access.
#1 : value2
Clock is enabled at after address phase.
End of enumeration elements list.
AGEN : Device Type for Region
bits : 28 - 30 (3 bit)
access : read-write
EBU Bus Read Access Parameter Register
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDDTACS : Recovery Cycles between Different Regions
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : value1
No Recovery Phase clock cycles available.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
RDRECOVC : Recovery Cycles after Read Accesses
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
No Recovery Phase clock cycles available.
#001 : value2
1 clock cycle selected.
#110 : value3
6 clock cycles selected.
#111 : value4
7 clock cycles selected.
End of enumeration elements list.
WAITRDC : Programmed Wait States for read accesses
bits : 7 - 10 (4 bit)
access : read-write
Enumeration:
#00000 : value1
1 wait state.
#00001 : value2
1 wait states.
#00010 : value3
2 wait state.
#11110 : value4
30 wait states.
#11111 : value5
31 wait states.
End of enumeration elements list.
DATAC : Data Hold Cycles for Read Accesses
bits : 12 - 14 (3 bit)
access : read-write
EXTCLOCK : Frequency of external clock at pin BFCLKO
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : value1
Equal to INT_CLK frequency.
#01 : value2
1/2 of INT_CLK frequency.
#10 : value3
1/3 of INT_CLK frequency.
#11 : value4
1/4 of INT_CLK frequency (default after reset).
End of enumeration elements list.
EXTDATA : Extended data
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#00 : value1
external memory outputs data every BFCLK cycle
#01 : value2
external memory outputs data every two BFCLK cycles
#10 : value3
external memory outputs data every four BFCLK cycles
#11 : value4
external memory outputs data every eight BFCLK cycles
End of enumeration elements list.
CMDDELAY : Command Delay Cycles
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
AHOLDC : Address Hold Cycles
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
ADDRC : Address Cycles
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#0000 : value1
1 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
EBU Bus Write Configuration Register
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FETBLEN : Burst Length for Synchronous Burst
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
#000 : value1
1 data access (default after reset).
#001 : value2
2 data accesses.
#010 : value3
4 data accesses.
#011 : value4
8 data accesses.
End of enumeration elements list.
FBBMSEL : Synchronous burst buffer mode select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Burst buffer length defined by value in FETBLEN (default after reset).
#1 : value2
Continuous mode. All data required for transaction transferred in single burst
End of enumeration elements list.
NAA : Enable flash non-array access workaround
bits : 7 - 6 (0 bit)
access : read-only
ECSE : Early Chip Select for Synchronous Burst
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
#0 : value1
CS is delayed.
#1 : value2
CS is not delayed.
End of enumeration elements list.
EBSE : Early Burst Signal Enable for Synchronous Burst
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
#0 : value1
ADV is delayed.
#1 : value2
ADV is not delayed.
End of enumeration elements list.
WAITINV : Reversed polarity at WAIT
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
#0 : value1
input at WAIT pin is active low (default after reset).
#1 : value2
input at WAIT pin is active high.
End of enumeration elements list.
BCGEN : Byte Control Signal Control
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
#00 : value1
Byte control signals follow chip select timing.
#01 : value2
Byte control signals follow control signal timing (RD, RD/WR) (default after reset).
#10 : value3
Byte control signals follow write enable signal timing (RD/WR only).
End of enumeration elements list.
PORTW : Device Addressing Mode
bits : 22 - 22 (1 bit)
access : read-only
WAIT : External Wait Control: 0=OFF (default after reset)., 1=Asynchronous input at WAIT., 2=Synchronous input at WAIT., 3=reserved., 0=OFF (default after reset)., 1=Wait for page load (Early WAIT)., 2=Wait for page load (WAIT with data)., 3=Abort and retry access.,
bits : 24 - 24 (1 bit)
access : read-write
AAP : Asynchronous Address phase:
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
#0 : value1
Clock is enabled at beginning of access.
#1 : value2
Clock is enabled at after address phase.
End of enumeration elements list.
LOCKCS : Lock Chip Select
bits : 27 - 26 (0 bit)
access : read-write
Enumeration:
#0 : value1
Chip Select cannot be locked (default after reset).
#1 : value2
Chip Select will be automatically locked when written to from the processor data port.
End of enumeration elements list.
AGEN : Device Type for Region
bits : 28 - 30 (3 bit)
access : read-write
EBU Bus Write Access Parameter Register
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WRDTACS : Recovery Cycles between Different Regions
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
#0000 : value1
No Recovery Phase clock cycles available.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
WRRECOVC : Recovery Cycles after Write Accesses
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
No Recovery Phase clock cycles available.
#001 : value2
1 clock cycle selected.
#110 : value3
6 clock cycles selected.
#111 : value4
7 clock cycles selected.
End of enumeration elements list.
WAITWRC : Programmed Wait States for write accesses
bits : 7 - 10 (4 bit)
access : read-write
Enumeration:
#00000 : value1
1 wait state.
#00001 : value2
1 wait states.
#00010 : value3
2 wait state.
#11110 : value4
30 wait states.
#11111 : value5
31 wait states.
End of enumeration elements list.
DATAC : Data Hold Cycles for Write Accesses
bits : 12 - 14 (3 bit)
access : read-write
Enumeration:
#0000 : value1
No Recovery Phase clock cycles available.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
EXTCLOCK : Frequency of external clock at pin BFCLKO
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : value1
Equal to INT_CLK frequency.
#01 : value2
1/2 of INT_CLK frequency.
#10 : value3
1/3 of INT_CLK frequency.
#11 : value4
1/4 of INT_CLK frequency (default after reset).
End of enumeration elements list.
EXTDATA : Extended data
bits : 18 - 18 (1 bit)
access : read-write
Enumeration:
#00 : value1
external memory outputs data every BFCLK cycle
#01 : value2
external memory outputs data every two BFCLK cycles
#10 : value3
external memory outputs data every four BFCLK cycles
#11 : value4
external memory outputs data every eight BFCLK cycles
End of enumeration elements list.
CMDDELAY : Command Delay Cycles
bits : 20 - 22 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected.
#0001 : value2
1 clock cycle selected.
#1110 : value3
14 clock cycles selected.
#1111 : value4
15 clock cycles selected.
End of enumeration elements list.
AHOLDC : Address Hold Cycles
bits : 24 - 26 (3 bit)
access : read-write
Enumeration:
#0000 : value1
0 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
ADDRC : Address Cycles
bits : 28 - 30 (3 bit)
access : read-write
Enumeration:
#0000 : value1
1 clock cycle selected
#0001 : value2
1 clock cycle selected
#1110 : value3
14 clock cycles selected
#1111 : value4
15 clock cycles selected
End of enumeration elements list.
EBU SDRAM Control Register
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CRAS : Row to precharge delay counter
bits : 0 - 2 (3 bit)
access : read-write
CRFSH : Initialization refresh commands counter
bits : 4 - 6 (3 bit)
access : read-write
CRSC : Mode register set-up time
bits : 8 - 8 (1 bit)
access : read-write
CRP : Row precharge time counter
bits : 10 - 10 (1 bit)
access : read-write
AWIDTH : Width of column address
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0x0 : value1
do not use
0x1 : value2
Address(8:0)
0x2 : value3
Address(9:0)
0x3 : value4
Address(10:0)
End of enumeration elements list.
CRCD : Row to column delay counter
bits : 14 - 14 (1 bit)
access : read-write
CRC : Row cycle time counter
bits : 16 - 17 (2 bit)
access : read-write
ROWM : Mask for row tag
bits : 19 - 20 (2 bit)
access : read-write
Enumeration:
0x1 : value2
Address bit 26 to 9
0x2 : value3
Address bit 26 to 10
0x3 : value4
Address bit 26 to 11
0x4 : value5
Address bit 26 to 12
0x5 : value6
Address bit 26 to 13
End of enumeration elements list.
BANKM : Mask for bank tag
bits : 22 - 23 (2 bit)
access : read-write
Enumeration:
0x1 : value2
Address bit 21 to 20
0x2 : value3
Address bit 22 to 21
0x3 : value4
Address bit 23 to 22
0x4 : value5
Address bit 24 to 23
0x5 : value6
Address bit 25 to 24
0x6 : value7
Address bit 26 to 25
0x7 : value8
Address bit 26
End of enumeration elements list.
CRCE : Row cycle time counter extension
bits : 25 - 26 (2 bit)
access : read-write
CLKDIS : Disable SDRAM clock output
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
#0 : value1
clock enabled
#1 : value2
clock disabled
End of enumeration elements list.
PWR_MODE : Power Save Mode used for gated clock mode
bits : 29 - 29 (1 bit)
access : read-write
Enumeration:
0x0 : value1
precharge before clock stop (default after reset)
0x1 : value2
auto-precharge before clock stop
0x2 : value3
active power down (stop clock without precharge)
0x3 : value4
clock stop power down
End of enumeration elements list.
SDCMSEL : SDRAM clock mode select
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
#1 : value1
clock disabled between accesses
#0 : value2
clock continuously runs
End of enumeration elements list.
EBU SDRAM Mode Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BURSTL : Burst length
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : value1
1 (default after reset)
1 : value2
2
2 : value3
4
3 : value4
8
4 : value5
16
End of enumeration elements list.
BTYP : Burst type
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
Only this value should be written (default after reset)
End of enumeration elements list.
CASLAT : CAS latency
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
2 : value1
Two clocks (default after reset)
3 : value2
Three clocks
End of enumeration elements list.
OPMODE : Operation Mode
bits : 7 - 12 (6 bit)
access : read-write
Enumeration:
#000000 : value1
Only this value must be written (default after reset)
End of enumeration elements list.
COLDSTART : SDRAM coldstart
bits : 15 - 14 (0 bit)
access : write-only
XOPM : Extended Operation Mode
bits : 16 - 26 (11 bit)
access : read-write
XBA : Extended Operation Bank Select
bits : 28 - 30 (3 bit)
access : read-write
EBU SDRAM Refresh Control Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFRESHC : Refresh counter period
bits : 0 - 4 (5 bit)
access : read-write
REFRESHR : Number of refresh commands
bits : 6 - 7 (2 bit)
access : read-write
SELFREXST : Self Refresh Exit Status.
bits : 9 - 8 (0 bit)
access : read-only
SELFREX : Self Refresh Exit (Power Up).
bits : 10 - 9 (0 bit)
access : read-write
SELFRENST : Self Refresh Entry Status.
bits : 11 - 10 (0 bit)
access : read-only
SELFREN : Self Refresh Entry
bits : 12 - 11 (0 bit)
access : read-write
AUTOSELFR : Automatic Self Refresh
bits : 13 - 12 (0 bit)
access : read-write
ERFSHC : Extended Refresh Counter Period
bits : 14 - 14 (1 bit)
access : read-write
SELFREX_DLY : Self Refresh Exit Delay
bits : 16 - 22 (7 bit)
access : read-write
ARFSH : Auto Refresh on Self refresh Exit
bits : 24 - 23 (0 bit)
access : read-write
RES_DLY : Delay on Power Down Exit
bits : 25 - 26 (2 bit)
access : read-write
EBU SDRAM Status Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REFERR : SDRAM Refresh Error
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
#0 : value1
No refresh error.
#1 : value2
Refresh error occurred.
End of enumeration elements list.
SDRMBUSY : SDRAM Busy
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
#0 : value1
Power-up initialization sequence is not running
#1 : value2
Power-up initialization sequence is running
End of enumeration elements list.
SDERR : SDRAM read error
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
#0 : value1
Reads running successfully
#1 : value2
Read error condition has been detected
End of enumeration elements list.
EBU Module Identification Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MOD_REV : Module Revision
bits : 0 - 6 (7 bit)
access : read-only
MOD_TYPE : Module Type
bits : 8 - 14 (7 bit)
access : read-only
MOD_NUMBER : Module Number
bits : 16 - 30 (15 bit)
access : read-only
EBU Test/Control Configuration Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
DIP : Disable Internal Pipelining
bits : 0 - -1 (0 bit)
access : read-write
ADDIO : Address Pins to GPIO Mode
bits : 16 - 23 (8 bit)
access : read-write
Enumeration:
#0 : value1
Address Bit is required for addressing memory
#1 : value2
Address Bit is available for GPIO function
End of enumeration elements list.
ADVIO : ADV Pin to GPIO Mode
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
#0 : value1
ADV pin is required for controlling memory
#1 : value2
ADV pin is available for GPIO function
End of enumeration elements list.
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