\n
address_offset : 0x0 Bytes (0x0)
size : 0x100 byte (0x0)
mem_usage : registers
protection : not protected
Event Input Select
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXS0A : Event Source Select for A0 (ERS0)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
Input ERU_0A0 is selected
#01 : value2
Input ERU_0A1 is selected
#10 : value3
Input ERU_0A2 is selected
#11 : value4
Input ERU_0A3 is selected
End of enumeration elements list.
EXS0B : Event Source Select for B0 (ERS0)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#00 : value1
Input ERU_0B0 is selected
#01 : value2
Input ERU_0B1 is selected
#10 : value3
Input ERU_0B2 is selected
#11 : value4
Input ERU_0B3 is selected
End of enumeration elements list.
EXS1A : Event Source Select for A1 (ERS1)
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
Input ERU_1A0 is selected
#01 : value2
Input ERU_1A1 is selected
#10 : value3
Input ERU_1A2 is selected
#11 : value4
Input ERU_1A3 is selected
End of enumeration elements list.
EXS1B : Event Source Select for B1 (ERS1)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : value1
Input ERU_1B0 is selected
#01 : value2
Input ERU_1B1 is selected
#10 : value3
Input ERU_1B2 is selected
#11 : value4
Input ERU_1B3 is selected
End of enumeration elements list.
EXS2A : Event Source Select for A2 (ERS2)
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
Input ERU_2A0 is selected
#01 : value2
Input ERU_2A1 is selected
#10 : value3
Input ERU_2A2 is selected
#11 : value4
Input ERU_2A3 is selected
End of enumeration elements list.
EXS2B : Event Source Select for B2 (ERS2)
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
Input ERU_2B0 is selected
#01 : value2
Input ERU_2B1 is selected
#10 : value3
Input ERU_2B2 is selected
#11 : value4
Input ERU_2B3 is selected
End of enumeration elements list.
EXS3A : Event Source Select for A3 (ERS3)
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#00 : value1
Input ERU_3A0 is selected
#01 : value2
Input ERU_3A1 is selected
#10 : value3
Input ERU_3A2 is selected
#11 : value4
Input ERU_3A3 is selected
End of enumeration elements list.
EXS3B : Event Source Select for B3 (ERS3)
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
#00 : value1
Input ERU_3B0 is selected
#01 : value2
Input ERU_3B1 is selected
#10 : value3
Input ERU_3B2 is selected
#11 : value4
Input ERU_3B3 is selected
End of enumeration elements list.
Event Input Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE : Output Trigger Pulse Enable for ETLx
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The trigger pulse generation is disabled
#1 : value2
The trigger pulse generation is enabled
End of enumeration elements list.
LD : Rebuild Level Detection for Status Flag for ETLx
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software.
#1 : value2
The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0.
End of enumeration elements list.
RE : Rising Edge Detection Enable ETLx
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
A rising edge is not considered as edge event
#1 : value2
A rising edge is considered as edge event
End of enumeration elements list.
FE : Falling Edge Detection Enable ETLx
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
A falling edge is not considered as edge event
#1 : value2
A falling edge is considered as edge event
End of enumeration elements list.
OCS : Output Channel Select for ETLx Output Trigger Pulse
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
Trigger pulses are sent to OGU0
#001 : value2
Trigger pulses are sent to OGU1
#010 : value3
Trigger pulses are sent to OGU2
#011 : value4
Trigger pulses are sent to OGU3
End of enumeration elements list.
FL : Status Flag for ETLx
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
The enabled edge event has not been detected
#1 : value2
The enabled edge event has been detected
End of enumeration elements list.
SS : Input Source Select for ERSx
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
Input A without additional combination
#01 : value2
Input B without additional combination
#10 : value3
Input A OR input B
#11 : value4
Input A AND input B
End of enumeration elements list.
NA : Input A Negation Select for ERSx
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
Input A is used directly
#1 : value2
Input A is inverted
End of enumeration elements list.
NB : Input B Negation Select for ERSx
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : value1
Input B is used directly
#1 : value2
Input B is inverted
End of enumeration elements list.
Event Input Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE : Output Trigger Pulse Enable for ETLx
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The trigger pulse generation is disabled
#1 : value2
The trigger pulse generation is enabled
End of enumeration elements list.
LD : Rebuild Level Detection for Status Flag for ETLx
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software.
#1 : value2
The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0.
End of enumeration elements list.
RE : Rising Edge Detection Enable ETLx
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
A rising edge is not considered as edge event
#1 : value2
A rising edge is considered as edge event
End of enumeration elements list.
FE : Falling Edge Detection Enable ETLx
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
A falling edge is not considered as edge event
#1 : value2
A falling edge is considered as edge event
End of enumeration elements list.
OCS : Output Channel Select for ETLx Output Trigger Pulse
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
Trigger pulses are sent to OGU0
#001 : value2
Trigger pulses are sent to OGU1
#010 : value3
Trigger pulses are sent to OGU2
#011 : value4
Trigger pulses are sent to OGU3
End of enumeration elements list.
FL : Status Flag for ETLx
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
The enabled edge event has not been detected
#1 : value2
The enabled edge event has been detected
End of enumeration elements list.
SS : Input Source Select for ERSx
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
Input A without additional combination
#01 : value2
Input B without additional combination
#10 : value3
Input A OR input B
#11 : value4
Input A AND input B
End of enumeration elements list.
NA : Input A Negation Select for ERSx
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
Input A is used directly
#1 : value2
Input A is inverted
End of enumeration elements list.
NB : Input B Negation Select for ERSx
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : value1
Input B is used directly
#1 : value2
Input B is inverted
End of enumeration elements list.
Event Output Trigger Control
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISS : Internal Trigger Source Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
The peripheral trigger function is disabled
#01 : value2
Input ERU_OGUy1 is selected
#10 : value3
Input ERU_OGUy2 is selected
#11 : value4
Input ERU_OGUy3 is selected
End of enumeration elements list.
GEEN : Gating Event Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The event detection is disabled
#1 : value2
The event detection is enabled
End of enumeration elements list.
PDR : Pattern Detection Result Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
A pattern miss is detected
#1 : value2
A pattern match is detected
End of enumeration elements list.
GP : Gating Selection for Pattern Detection Result
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
ERU_GOUTy is always disabled and ERU_IOUTy can not be activated
#01 : value2
ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy
#10 : value3
ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1)
#11 : value4
ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0)
End of enumeration elements list.
IPEN0 : Pattern Detection Enable for ETL0
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
IPEN1 : Pattern Detection Enable for ETL1
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
IPEN2 : Pattern Detection Enable for ETL2
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
IPEN3 : Pattern Detection Enable for ETL3
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
Event Input Control
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE : Output Trigger Pulse Enable for ETLx
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The trigger pulse generation is disabled
#1 : value2
The trigger pulse generation is enabled
End of enumeration elements list.
LD : Rebuild Level Detection for Status Flag for ETLx
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software.
#1 : value2
The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0.
End of enumeration elements list.
RE : Rising Edge Detection Enable ETLx
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
A rising edge is not considered as edge event
#1 : value2
A rising edge is considered as edge event
End of enumeration elements list.
FE : Falling Edge Detection Enable ETLx
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
A falling edge is not considered as edge event
#1 : value2
A falling edge is considered as edge event
End of enumeration elements list.
OCS : Output Channel Select for ETLx Output Trigger Pulse
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
Trigger pulses are sent to OGU0
#001 : value2
Trigger pulses are sent to OGU1
#010 : value3
Trigger pulses are sent to OGU2
#011 : value4
Trigger pulses are sent to OGU3
End of enumeration elements list.
FL : Status Flag for ETLx
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
The enabled edge event has not been detected
#1 : value2
The enabled edge event has been detected
End of enumeration elements list.
SS : Input Source Select for ERSx
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
Input A without additional combination
#01 : value2
Input B without additional combination
#10 : value3
Input A OR input B
#11 : value4
Input A AND input B
End of enumeration elements list.
NA : Input A Negation Select for ERSx
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
Input A is used directly
#1 : value2
Input A is inverted
End of enumeration elements list.
NB : Input B Negation Select for ERSx
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : value1
Input B is used directly
#1 : value2
Input B is inverted
End of enumeration elements list.
Event Output Trigger Control
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISS : Internal Trigger Source Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
The peripheral trigger function is disabled
#01 : value2
Input ERU_OGUy1 is selected
#10 : value3
Input ERU_OGUy2 is selected
#11 : value4
Input ERU_OGUy3 is selected
End of enumeration elements list.
GEEN : Gating Event Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The event detection is disabled
#1 : value2
The event detection is enabled
End of enumeration elements list.
PDR : Pattern Detection Result Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
A pattern miss is detected
#1 : value2
A pattern match is detected
End of enumeration elements list.
GP : Gating Selection for Pattern Detection Result
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
ERU_GOUTy is always disabled and ERU_IOUTy can not be activated
#01 : value2
ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy
#10 : value3
ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1)
#11 : value4
ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0)
End of enumeration elements list.
IPEN0 : Pattern Detection Enable for ETL0
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
IPEN1 : Pattern Detection Enable for ETL1
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
IPEN2 : Pattern Detection Enable for ETL2
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
IPEN3 : Pattern Detection Enable for ETL3
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
Event Input Control
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PE : Output Trigger Pulse Enable for ETLx
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The trigger pulse generation is disabled
#1 : value2
The trigger pulse generation is enabled
End of enumeration elements list.
LD : Rebuild Level Detection for Status Flag for ETLx
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
#0 : value1
The status flag FL is not cleared by hardware and is used as "sticky" bit. Once set, it is not influenced by any edge until it becomes cleared by software.
#1 : value2
The status flag FL rebuilds a level detection of the desired event. It becomes automatically set with a rising edge if RE = 1 or with a falling edge if FE = 1. It becomes automatically cleared with a rising edge if RE = 0 or with a falling edge if FE = 0.
End of enumeration elements list.
RE : Rising Edge Detection Enable ETLx
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
A rising edge is not considered as edge event
#1 : value2
A rising edge is considered as edge event
End of enumeration elements list.
FE : Falling Edge Detection Enable ETLx
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
#0 : value1
A falling edge is not considered as edge event
#1 : value2
A falling edge is considered as edge event
End of enumeration elements list.
OCS : Output Channel Select for ETLx Output Trigger Pulse
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
#000 : value1
Trigger pulses are sent to OGU0
#001 : value2
Trigger pulses are sent to OGU1
#010 : value3
Trigger pulses are sent to OGU2
#011 : value4
Trigger pulses are sent to OGU3
End of enumeration elements list.
FL : Status Flag for ETLx
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
#0 : value1
The enabled edge event has not been detected
#1 : value2
The enabled edge event has been detected
End of enumeration elements list.
SS : Input Source Select for ERSx
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
Input A without additional combination
#01 : value2
Input B without additional combination
#10 : value3
Input A OR input B
#11 : value4
Input A AND input B
End of enumeration elements list.
NA : Input A Negation Select for ERSx
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
#0 : value1
Input A is used directly
#1 : value2
Input A is inverted
End of enumeration elements list.
NB : Input B Negation Select for ERSx
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
#0 : value1
Input B is used directly
#1 : value2
Input B is inverted
End of enumeration elements list.
Event Output Trigger Control
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISS : Internal Trigger Source Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
The peripheral trigger function is disabled
#01 : value2
Input ERU_OGUy1 is selected
#10 : value3
Input ERU_OGUy2 is selected
#11 : value4
Input ERU_OGUy3 is selected
End of enumeration elements list.
GEEN : Gating Event Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The event detection is disabled
#1 : value2
The event detection is enabled
End of enumeration elements list.
PDR : Pattern Detection Result Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
A pattern miss is detected
#1 : value2
A pattern match is detected
End of enumeration elements list.
GP : Gating Selection for Pattern Detection Result
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
ERU_GOUTy is always disabled and ERU_IOUTy can not be activated
#01 : value2
ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy
#10 : value3
ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1)
#11 : value4
ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0)
End of enumeration elements list.
IPEN0 : Pattern Detection Enable for ETL0
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
IPEN1 : Pattern Detection Enable for ETL1
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
IPEN2 : Pattern Detection Enable for ETL2
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
IPEN3 : Pattern Detection Enable for ETL3
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
Event Output Trigger Control
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ISS : Internal Trigger Source Selection
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
The peripheral trigger function is disabled
#01 : value2
Input ERU_OGUy1 is selected
#10 : value3
Input ERU_OGUy2 is selected
#11 : value4
Input ERU_OGUy3 is selected
End of enumeration elements list.
GEEN : Gating Event Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
#0 : value1
The event detection is disabled
#1 : value2
The event detection is enabled
End of enumeration elements list.
PDR : Pattern Detection Result Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
#0 : value1
A pattern miss is detected
#1 : value2
A pattern match is detected
End of enumeration elements list.
GP : Gating Selection for Pattern Detection Result
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
ERU_GOUTy is always disabled and ERU_IOUTy can not be activated
#01 : value2
ERU_GOUTy is always enabled and ERU_IOUTy becomes activated with each activation of ERU_TOUTy
#10 : value3
ERU_GOUTy is equal to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is detected (pattern match PDR = 1)
#11 : value4
ERU_GOUTy is inverted to ERU_PDOUTy and ERU_IOUTy becomes activated with an activation of ERU_TOUTy while the desired pattern is not detected (pattern miss PDR = 0)
End of enumeration elements list.
IPEN0 : Pattern Detection Enable for ETL0
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
IPEN1 : Pattern Detection Enable for ETL1
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
IPEN2 : Pattern Detection Enable for ETL2
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
IPEN3 : Pattern Detection Enable for ETL3
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
#0 : value1
Flag EXICONx.FL is excluded from the pattern detection
#1 : value2
Flag EXICONx.FL is included in the pattern detection
End of enumeration elements list.
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