Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0xC byte (0x0)
mem_usage : registers
protection : not protected
EtherCAT 0 Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ECATRSTEN : Enable EtherCAT Reset Request
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
#0 : value1
Reset request by EtherCAT Master disabled
#1 : value2
Reset request by EtherCAT Master enabled
End of enumeration elements list.
LATCHIN0SEL : LATCHIN0 Input Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input LATCHIN0A is selected
#01 : value2
Data input LATCHIN0B is selected
#10 : value3
Data input LATCHIN0C is selected
#11 : value4
Data input LATCHIN0D is selected
End of enumeration elements list.
LATCHIN0 : EtherCAT LATCH_IN0 Input Signal
bits : 11 - 10 (0 bit)
access : read-only
LATCHIN1SEL : LATCHIN1 Input Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input LATCHIN1A is selected
#01 : value2
Data input LATCHIN1B is selected
#10 : value3
Data input LATCHIN1C is selected
#11 : value4
Data input LATCHIN1D is selected
End of enumeration elements list.
LATCHIN1 : EtherCAT LATCH_IN1 Input Signal
bits : 15 - 14 (0 bit)
access : read-only
PHYOFFSET : Ethernet PHY Address Offset
bits : 16 - 19 (4 bit)
access : read-write
MDIO : MDIO Input Select
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input MDIA is selected
#01 : value2
Data input MDIB is selected
#10 : value3
Data input MDIC is selected
#11 : value4
Data input MDID is selected
End of enumeration elements list.
EtherCAT 0 Port 1 Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXD0 : PORT0 Receive Input 0 Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input RXD0A is selected
#01 : value2
Data input RXD0B is selected
#10 : value3
Data input RXD0C is selected
#11 : value4
Data input RXD0D is selected
End of enumeration elements list.
RXD1 : Port0 Receive Input 1 Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input RXD1A is selected
#01 : value2
Data input RXD1B is selected
#10 : value3
Data input RXD1C is selected
#11 : value4
Data input RXD1D is selected
End of enumeration elements list.
RXD2 : Port0 Receive Input 2 Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input RXD2A is selected
#01 : value2
Data input RXD2B is selected
#10 : value3
Data input RXD2C is selected
#11 : value4
Data input RXD2D is selected
End of enumeration elements list.
RXD3 : Port0 Receive Input 3 Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input RXD3A is selected
#01 : value2
Data input RXD3B is selected
#10 : value3
Data input RXD3C is selected
#11 : value4
Data input RXD3D is selected
End of enumeration elements list.
RX_ERR : Port0 MII RX ERROR Input Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input RX_ERRA is selected
#01 : value2
Data input RX_ERRB is selected
#10 : value3
Data input RX_ERRC is selected
#11 : value4
Data input RX_ERRD is selected
End of enumeration elements list.
RX_DV : Port0 MII RX DV Input Select
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input RX_DVA is selected
#01 : value2
Data input RX_DVB is selected
#10 : value3
Data input RX_DVC is selected
#11 : value4
Data input RX_DVD is selected
End of enumeration elements list.
RX_CLK : Port0 MII RX Clock Input Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#00 : value1
Clock input RX_CLKA
#01 : value2
Clock input RX_CLKB
#10 : value3
Clock input RX_CLKC
#11 : value4
Clock input RX_CLKD
End of enumeration elements list.
LINK : Port0 PHY Link Input Select
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : value1
PHY LINKA
#01 : value2
PHY LINKB
#10 : value3
PHY LINKC
#11 : value4
PHY LINKD
End of enumeration elements list.
TX_CLK : Port0 MII TX Clock Input Select
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#00 : value1
Clock input TX_CLKA
#01 : value2
Clock input TX_CLKB
#10 : value3
Clock input TX_CLKC
#11 : value4
Clock input TX_CLKD
End of enumeration elements list.
TX_SHIFT : Port0 Manual TX Shift configuration
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#00 : value1
0 ns
#01 : value2
10 ns
#10 : value3
20 ns
#11 : value4
30 ns
End of enumeration elements list.
EtherCAT 0 Port 1 Control Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RXD0 : Port1 Receive Input 0 Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input RXD0A is selected
#01 : value2
Data input RXD0B is selected
#10 : value3
Data input RXD0C is selected
#11 : value4
Data input RXD0D is selected
End of enumeration elements list.
RXD1 : Port1 Receive Input 1 Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input RXD1A is selected
#01 : value2
Data input RXD1B is selected
#10 : value3
Data input RXD1C is selected
#11 : value4
Data input RXD1D is selected
End of enumeration elements list.
RXD2 : Port1 Receive Input 2 Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input RXD2A is selected
#01 : value2
Data input RXD2B is selected
#10 : value3
Data input RXD2C is selected
#11 : value4
Data input RXD2D is selected
End of enumeration elements list.
RXD3 : Port1 Receive Input 3 Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input RXD3A is selected
#01 : value2
Data input RXD3B is selected
#10 : value3
Data input RXD3C is selected
#11 : value4
Data input RXD3D is selected
End of enumeration elements list.
RX_ERR : Port1 MII RX ERROR Input Select
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input RX_ERRA is selected
#01 : value2
Data input RX_ERRB is selected
#10 : value3
Data input RX_ERRC is selected
#11 : value4
Data input RX_ERRD is selected
End of enumeration elements list.
RX_DV : Port1 MII RX DV Input Select
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
#00 : value1
Data input RX_DVA is selected
#01 : value2
Data input RX_DVB is selected
#10 : value3
Data input RX_DVC is selected
#11 : value4
Data input RX_DVD is selected
End of enumeration elements list.
RX_CLK : Port1 MII RX Clock Input Select
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
#00 : value1
Clock input RX_CLKA
#01 : value2
Clock input RX_CLKB
#10 : value3
Clock input RX_CLKC
#11 : value4
Clock input RX_CLKD
End of enumeration elements list.
LINK : Port1 PHY Link Input Select
bits : 16 - 16 (1 bit)
access : read-write
Enumeration:
#00 : value1
PHY LINKA
#01 : value2
PHY LINKB
#10 : value3
PHY LINKC
#11 : value4
PHY LINKD
End of enumeration elements list.
TX_CLK : Port1 MII TX Clock Input Select
bits : 28 - 28 (1 bit)
access : read-write
Enumeration:
#00 : value1
Clock input TX_CLKA
#01 : value2
Clock input TX_CLKB
#10 : value3
Clock input TX_CLKC
#11 : value4
Clock input TX_CLKD
End of enumeration elements list.
TX_SHIFT : Port1 Manual TX Shift configuration
bits : 30 - 30 (1 bit)
access : read-write
Enumeration:
#00 : value1
0 ns
#01 : value2
10 ns
#10 : value3
20 ns
#11 : value4
30 ns
End of enumeration elements list.
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