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PMU

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

WAKE_STATUS

RESET_STS1

RESET_STS2

CNF_PMU_SETTINGS

CNF_CYC_WAKE

SystemStartConfig

MON_CNF

SUPPLY_STS

LIN_WAKE_EN

CNF_RST_TFB

SYS_FAIL_STS

VDDEXT_CTRL

WAKE_STS_MON

CNF_WAKE_FILTER

GPUDATA00

GPUDATA01

GPUDATA02

GPUDATA03

GPUDATA04

GPUDATA05

GPUDATA06

GPUDATA07

GPUDATA08

GPUDATA09

GPUDATA10

GPUDATA11


WAKE_STATUS

Main wake status register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKE_STATUS WAKE_STATUS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIN_WAKE MON_WAKE CYC_WAKE

LIN_WAKE : Wake-up via LIN- Message
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : value1

No Wake-up occurred

0b1 : value2

Wake-up occurred

End of enumeration elements list.

MON_WAKE : Wake-up via MON
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b0 : value1

No Wake-up occurred

0b1 : value2

Wake-up occurred

End of enumeration elements list.

CYC_WAKE : Wake-up caused by Cyclic Wake
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

0b0 : value1

No Wake-up occurred

0b1 : value2

Wake-up occurred

End of enumeration elements list.


RESET_STS1

Reset Status Hard Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESET_STS1 RESET_STS1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SYS_FAIL PMU_SleepEX PMU_LPR PMU_ClkWDT PMU_ExtWDT PMU_PIN PMU_1V5DidPOR

SYS_FAIL : Flag which indicates a reset caused by a System Fail reported in the corresponding Fail Register
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

No reset caused by System Fail executed

0b1 : value2

Reset caused by System Fail executed

End of enumeration elements list.

PMU_SleepEX : Flag which indicates a reset caused by Sleep-Exit
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

No reset caused by Sleep-Exit executed

0b1 : value2

Reset caused by Sleep-Exit executed

End of enumeration elements list.

PMU_LPR : Low Priority Resets (see PMU_RESET_STS2)
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Low Priority-Reset executed

0b1 : value2

Low Priority executed

End of enumeration elements list.

PMU_ClkWDT : Clock Watchdog (CLKWDT) Reset Flag
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : value1

No Clock Watchdog reset executed

0b1 : value2

Clock Watchdog reset executed

End of enumeration elements list.

PMU_ExtWDT : External Watchdog (WDT1) Reset Flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : value1

No External Watchdog reset executed

0b1 : value2

External Watchdog reset executed

End of enumeration elements list.

PMU_PIN : PIN-Reset Flag
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : value1

No PIN-Reset executed

0b1 : value2

PIN-Reset executed

End of enumeration elements list.

PMU_1V5DidPOR : Power-On Reset Flag
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : value1

No Power-On reset executed

0b1 : value2

Power-On reset executed

End of enumeration elements list.


RESET_STS2

Reset Status Soft Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RESET_STS2 RESET_STS2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMU_IntWDT PMU_SOFT LOCKUP

PMU_IntWDT : Internal Watchdog Reset Flag
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

No Internal Watchdog reset executed

0b1 : value2

Internal Watchdog reset executed

End of enumeration elements list.

PMU_SOFT : Soft-Reset Flag
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : value1

No Soft-Reset executed

0b1 : value2

Soft-Reset executed

End of enumeration elements list.

LOCKUP : Lockup-Reset Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

No Lockup-Reset executed

0b1 : value2

Lockup-Reset executed

End of enumeration elements list.


CNF_PMU_SETTINGS

PMU Settings Register
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNF_PMU_SETTINGS CNF_PMU_SETTINGS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CYC_WAKE_EN EN_VDDEXT_OC_OFF_N

CYC_WAKE_EN : Enabling Cyclic Wake
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Cyclic Wake disabled

0b1 : value2

Cyclic Wake enabled

End of enumeration elements list.

EN_VDDEXT_OC_OFF_N : Disabling VDDEXT Shutdown in Overload Condition
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Shutdown enabled

0b1 : value2

Shutdown disabled

End of enumeration elements list.


CNF_CYC_WAKE

Dead Time in Cyclic Wake Register
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNF_CYC_WAKE CNF_CYC_WAKE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 M03 E01

M03 : Mantissa
bits : 0 - 2 (3 bit)
access : read-write

Enumeration:

0b0000 : value1

Mantissa value is 1

0b1111 : value2

Mntissa value is 16

End of enumeration elements list.

E01 : Exponent
bits : 4 - 4 (1 bit)
access : read-write

Enumeration:

0b00 : value1

Exponent value is 0

0b01 : value2

Exponent value is 1

0b10 : value3

Exponent value is 2

0b11 : value4

Exponent value is 3

End of enumeration elements list.


SystemStartConfig

System Startup Config
address_offset : 0x2D4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SystemStartConfig SystemStartConfig read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MBIST_EN

MBIST_EN : System Startup Configuration Bit for RAM MBIST at Sleep Mode exit
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

No MBIST executed at Sleep Mode exit

0b1 : value2

MBIST executed at Sleep Mode exit

End of enumeration elements list.


MON_CNF

Settings Monitor 1
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

MON_CNF MON_CNF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN FALL RISE PD PU STS

EN : MON Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

MON disabled

0b1 : value2

MON enabled

End of enumeration elements list.

FALL : MON Wake-up on Falling Edge Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Wake-up disabled

0b1 : value2

Wake-up enabled

End of enumeration elements list.

RISE : MON Wake-up on Rising Edge Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Wake-up disabled

0b1 : value2

Wake-up enabled

End of enumeration elements list.

PD : Pull-Down Current Source for MON Input Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Pull-down source disabled

0b1 : value2

Pull-down source enabled

End of enumeration elements list.

PU : Pull-Up Current Source for MON Input Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Pull-up source disabled

0b1 : value2

Pull-up source enabled

End of enumeration elements list.

STS : MON Status Input
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

0b0 : value1

MON input has low status

0b1 : value2

MON input has high status

End of enumeration elements list.


SUPPLY_STS

Voltage Reg Status Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SUPPLY_STS SUPPLY_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMU_1V5_OVERVOLT PMU_1V5_OVERLOAD PMU_1V5_FAIL_EN PMU_5V_OVERVOLT PMU_5V_OVERLOAD PMU_5V_FAIL_EN

PMU_1V5_OVERVOLT : Overvoltage at VDDC regulator
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : value1

No overvoltage

0b1 : value2

Overvoltage

End of enumeration elements list.

PMU_1V5_OVERLOAD : Overload at VDDC regulator
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b0 : value1

No overload

0b1 : value2

Overload

End of enumeration elements list.

PMU_1V5_FAIL_EN : Enabling of VDDC status information as interrupt source
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

No interrupts are generated

0b1 : value2

Interrupts are generated

End of enumeration elements list.

PMU_5V_OVERVOLT : Overvoltage at VDDP regulator
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

0b0 : value1

No overvoltage

0b1 : value2

Overvoltage

End of enumeration elements list.

PMU_5V_OVERLOAD : Overload at VDDP regulator
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

0b0 : value1

No overload

0b1 : value2

Overload

End of enumeration elements list.

PMU_5V_FAIL_EN : Enabling of VDDP status information as interrupt source
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : value1

No interrupts are generated

0b1 : value2

Interrupts are generated

End of enumeration elements list.


LIN_WAKE_EN

LIN Wake Enable
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

LIN_WAKE_EN LIN_WAKE_EN read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIN_EN

LIN_EN : Lin Wake enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : Disable

LIN Wake disabled

0b1 : Enable

LIN Wake enabled

End of enumeration elements list.


CNF_RST_TFB

Reset Blind Time Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNF_RST_TFB CNF_RST_TFB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RST_TFB

RST_TFB : Reset Pin Blind Time Selection Bits
bits : 0 - 0 (1 bit)
access : read-write

Enumeration:

0b00 : RST_TFB_0

0,5 us typ.

0b01 : RST_TFB_1

1 us typ.

0b10 : RST_TFB_2

5 us typ.

0b11 : RST_TFB_3

31 us typ.

End of enumeration elements list.


SYS_FAIL_STS

System Fail Status Register
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_FAIL_STS SYS_FAIL_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SUPP_SHORT SUPP_TMOUT PMU_1V5_OVL PMU_5V_OVL SYS_OT WDT1_SEQ_FAIL

SUPP_SHORT : Supply Short
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : Main_Supply_ok

VDDP or VDDC are in expected range

0b1 : Main_Supply_short

VDDP or VDDC do not have stable operating point

End of enumeration elements list.

SUPP_TMOUT : Supply Time Out
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : Main_Supply_ok

VDDP or VDDC are in expected range

0b1 : Main_Supply_fail

VDDP or VDDC do not have stable operating point

End of enumeration elements list.

PMU_1V5_OVL : VDDC Overload Flag
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : No_Overload

VDDC ok

0b1 : Overload

Hall VDDC Overload

End of enumeration elements list.

PMU_5V_OVL : VDDP Overload Flag
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : No_Overload

VDDP ok

0b1 : Overload

VDDP Overload

End of enumeration elements list.

SYS_OT : System Overtemperature Indication Flag
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : No_Overtemperature

System ok

0b1 : Overtemperature

System Overtemperature

End of enumeration elements list.

WDT1_SEQ_FAIL : External Watchdog (WDT1) Sequential Fail
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : No_Fail

System working properly

0b1 : Sequential_Watchdog_Fail

5 consecutive watchdog fails

End of enumeration elements list.


VDDEXT_CTRL

VDDEXT Control
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

VDDEXT_CTRL VDDEXT_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENABLE FAIL_EN SHORT OVERVOLT OVERLOAD OK STABLE

ENABLE : VDDEXT Supply Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

VDDEXT Supply disabled

0b1 : value2

VDDEXT supply enabled

End of enumeration elements list.

FAIL_EN : Enabling of VDDEXT Supply status information as interrupt source
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

VDDEXT fail interrupts are disabled

0b1 : value2

VDDEXT fail Interrupts are enabled

End of enumeration elements list.

SHORT : VDDEXT Supply Shorted Output
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : value1

VDDEXT no short circuit

0b1 : value2

VDDEXT short circuit

End of enumeration elements list.

OVERVOLT : VDDEXT Supply Overvoltage
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : value1

VDDEXT not in overvoltage condition

0b1 : value2

VDDEXT in overvoltage condition

End of enumeration elements list.

OVERLOAD : VDDEXT Supply Overload
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : value1

VDDEXT not in overload condition

0b1 : value2

VDDEXT in overload condition

End of enumeration elements list.

OK : VDDEXT Supply works inside its specified range 2
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

0b1 : value1

VDDEXT in low drop mode

0b0 : value2

VDDEXT not in low drop mode

End of enumeration elements list.

STABLE : VDDEXT Supply works inside its specified range 1
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

0b1 : value1

VDDEXT Voltage inside of specified range

0b0 : value2

VDDEXT Voltage outside of specified range

End of enumeration elements list.


WAKE_STS_MON

Wake Source MON Input Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WAKE_STS_MON WAKE_STS_MON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WAKE_STS

WAKE_STS : Status of MON
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : No wake-up detected

.

0b1 : wake-up detected

.

End of enumeration elements list.


CNF_WAKE_FILTER

PMU Wake-up Timing Register
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CNF_WAKE_FILTER CNF_WAKE_FILTER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CNF_LIN_FT CNF_MON_FT

CNF_LIN_FT : Wake-up Filter time for LIN WAKE
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : 30_us

30 us filter time

0b1 : 50_us

50 us filter time

End of enumeration elements list.

CNF_MON_FT : Wake-up Filter time for Monitoring Inputs
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : 20_us

20 us filter time

0b1 : 40_us

40 us filter time

End of enumeration elements list.


GPUDATA00

General Purpose User DATA0
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPUDATA00 GPUDATA00 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA0

DATA0 : DATA0 Storage Byte
bits : 0 - 6 (7 bit)
access : read-write


GPUDATA01

General Purpose User DATA1
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPUDATA01 GPUDATA01 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA1

DATA1 : DATA1 Storage Byte
bits : 0 - 6 (7 bit)
access : read-write


GPUDATA02

General Purpose User DATA2
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPUDATA02 GPUDATA02 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA2

DATA2 : DATA2 Storage Byte
bits : 0 - 6 (7 bit)
access : read-write


GPUDATA03

General Purpose User DATA3
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPUDATA03 GPUDATA03 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA3

DATA3 : DATA3 Storage Byte
bits : 0 - 6 (7 bit)
access : read-write


GPUDATA04

General Purpose User DATA4
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPUDATA04 GPUDATA04 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA4

DATA4 : DATA4 Storage Byte
bits : 0 - 6 (7 bit)
access : read-write


GPUDATA05

General Purpose User DATA5
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPUDATA05 GPUDATA05 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA5

DATA5 : DATA5 Storage Byte
bits : 0 - 6 (7 bit)
access : read-write


GPUDATA06

General Purpose User DATA6
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPUDATA06 GPUDATA06 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA6

DATA6 : DATA6 Storage Byte
bits : 0 - 6 (7 bit)
access : read-write


GPUDATA07

General Purpose User DATA7
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPUDATA07 GPUDATA07 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA7

DATA7 : DATA7 Storage Byte
bits : 0 - 6 (7 bit)
access : read-write


GPUDATA08

General Purpose User DATA8
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPUDATA08 GPUDATA08 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA8

DATA8 : DATA8 Storage Byte
bits : 0 - 6 (7 bit)
access : read-write


GPUDATA09

General Purpose User DATA9
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPUDATA09 GPUDATA09 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA9

DATA9 : DATA9 Storage Byte
bits : 0 - 6 (7 bit)
access : read-write


GPUDATA10

General Purpose User DATA10
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPUDATA10 GPUDATA10 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA10

DATA10 : DATA10 Storage Byte
bits : 0 - 6 (7 bit)
access : read-write


GPUDATA11

General Purpose User DATA11
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GPUDATA11 GPUDATA11 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DATA11

DATA11 : DATA11 Storage Byte
bits : 0 - 6 (7 bit)
access : read-write



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