Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
NMI Clear Register, RESET_TYPE_3
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMIWDTC : Watchdog Timer NMI Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
WDT NMI is not cleared.
0b1 : value2
WDT NMI is cleared.
End of enumeration elements list.
NMIPLLC : PLL Loss of Lock NMI Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : value1
PLL Loss of Lock NMI is not cleared.
0b1 : value2
PLL Loss of Lock NMI is cleared.
End of enumeration elements list.
NMINVMC : NVM Operation Complete NMI Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
NVM operation complete NMI is not cleared.
0b1 : value2
NVM operation complete NMI is cleared.
End of enumeration elements list.
NMIOTC : NMI OT Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
0b0 : value1
NMI OT is not cleared.
0b1 : value2
NMI OT is cleared.
End of enumeration elements list.
NMIOWDC : Oscillator Watchdog NMI Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Oscillator watchdog NMI is not cleared.
0b1 : value2
Oscillator watchdog NMI is cleared.
End of enumeration elements list.
NMIMAPC : NVM Map Error NMI Clear
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
0b0 : value1
NVM Map Error NMI is not cleared.
0b1 : value2
NVM Map Error NMI is cleared.
End of enumeration elements list.
NMIECCC : ECC Error NMI Clear
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
0b0 : value1
ECC Error NMI is not cleared.
0b1 : value2
ECC Error NMI is cleared.
End of enumeration elements list.
NMISUPC : Supply Prewarning NMI Clear
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Supply NMI is not cleared.
0b1 : value2
Supply NMI is cleared.
End of enumeration elements list.
Interrupt Request Register 3, RESET_TYPE_3
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCU6SR0 : Interrupt Flag 0 for CCU6
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt event has not occurred.
0b1 : value2
Interrupt event has occurred.
End of enumeration elements list.
CCU6SR1 : Interrupt Flag 1 for CCU6
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt event has not occurred.
0b1 : value2
Interrupt event has occurred.
End of enumeration elements list.
Port Output Control Register, RESET_TYPE_3
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDM4 : P1.4 Port Driver Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0b000 : value1
Strong driver and sharp edge mode
0b001 : value2
Strong driver and medium edge mode
0b010 : value3
Strong driver and soft edge mode
0b011 : value4
Weak driver
0b100 : value5
Medium driver
0b101 : value6
Medium driver
0b110 : value7
Medium driver
0b111 : value8
Weak driver
End of enumeration elements list.
Error Detection and Correction Status Clear Register, RESET_TYPE_3
address_offset : 0x10C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDBEC : RAM Double Bit Error Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
A double bit error on RAM is not cleared.
0b1 : value2
A double bit error on RAM is cleared.
End of enumeration elements list.
NVMDBEC : NVM Double Bit Error Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
A double bit error on NVM is not cleared.
0b1 : value2
A double bit error on NVM is cleared.
End of enumeration elements list.
RSBEC : RAM Single Bit Error Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : value1
A single bit error on RAM is not cleared.
0b1 : value2
A single bit error on RAM is cleared.
End of enumeration elements list.
Interrupt Request Register 4, RESET_TYPE_3
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCU6SR2 : Interrupt Flag 2 for CCU6
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt event has not occurred.
0b1 : value2
Interrupt event has occurred.
End of enumeration elements list.
CCU6SR3 : Interrupt Flag 3 for CCU6
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt event has not occurred.
0b1 : value2
Interrupt event has occurred.
End of enumeration elements list.
General Purpose Timer 12 Interrupt Enable Register , RESET_TYPE_3
address_offset : 0x15C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T2IE : General Purpose Timer 12 T2 Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Interrupt is disabled
0b1 : value2
Interrupt is enabled
End of enumeration elements list.
T3IE : General Purpose Timer 12 T3 Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Interrupt is disabled
0b1 : value2
Interrupt is enabled
End of enumeration elements list.
T4IE : General Purpose Timer 12 T4 Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Interrupt is disabled
0b1 : value2
Interrupt is enabled
End of enumeration elements list.
T5IE : General Purpose Timer 12 T5 Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Interrupt is disabled
0b1 : value2
Interrupt is enabled
End of enumeration elements list.
T6IE : General Purpose Timer 12 T6 Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Interrupt is disabled
0b1 : value2
Interrupt is enabled
End of enumeration elements list.
CRIE : General Purpose Timer 12 Capture and Reload Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Interrupt is disabled
0b1 : value2
Interrupt is enabled
End of enumeration elements list.
Timer and Counter Control/Status Register, RESET_TYPE_3
address_offset : 0x160 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T2 : GPT Module 1 Timer 2 Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Timer 2 Interrupt has occurred.
0b1 : value2
Timer 2 Interrupt has occurred.
End of enumeration elements list.
T3 : GPT Module 1 Timer3 Interrupt Status
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Timer 3 Interrupt has occurred.
0b1 : value2
Timer 3 Interrupt has occurred.
End of enumeration elements list.
T4 : GPT Module 1 Timer4 Interrupt Status
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Timer 4 Interrupt has occurred.
0b1 : value2
Timer 4 Interrupt has occurred.
End of enumeration elements list.
T5 : GPT Module 2 Timer5 Interrupt Status
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Timer 5 Interrupt has occurred.
0b1 : value2
Timer 5 Interrupt has occurred.
End of enumeration elements list.
T6 : GPT Module 2Timer6 Interrupt Status
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Timer 6 Interrupt has occurred.
0b1 : value2
Timer 6 Interrupt has occurred.
End of enumeration elements list.
CR : GPT Module 2 Capture Reload Interrupt Status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Capture Reload Interrupt has occurred.
0b1 : value2
Capture Reload Interrupt has occurred.
End of enumeration elements list.
Timer and Counter Control/Status Clear Register, RESET_TYPE_3
address_offset : 0x164 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T2C : GPT Module 1 Timer 2 Interrupt Status Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
No Timer 2 Interrupt is cleared.
0b1 : value2
Timer 2 Interrupt is cleared.
End of enumeration elements list.
T3C : GPT Module 1 Timer3 Interrupt Status Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : value1
No Timer 3 Interrupt is cleared.
0b1 : value2
Timer 3 Interrupt is cleared.
End of enumeration elements list.
T4C : GPT Module 1 Timer4 Interrupt Status Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
No Timer 4 Interrupt is cleared.
0b1 : value2
Timer 4 Interrupt is cleared.
End of enumeration elements list.
T5C : GPT Module 2 Timer5 Interrupt Status Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
0b0 : value1
No Timer 5 Interrupt is cleared.
0b1 : value2
Timer 5 Interrupt is cleared.
End of enumeration elements list.
T6C : GPT Module 2Timer6 Interrupt Status Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : value1
No Timer 6 Interrupt is cleared.
0b1 : value2
Timer 6 Interrupt is cleared.
End of enumeration elements list.
CRC : GPT Module 2 Capture Reload Interrupt Status Clear
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
0b0 : value1
No Capture Reload Interrupt is cleared.
0b1 : value2
Capture Reload Interrupt is cleared.
End of enumeration elements list.
Interrupt Request 1 Clear Register, RESET_TYPE_3
address_offset : 0x178 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIRC : Error Interrupt Flag for SSC1 Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt event is not cleared.
0b1 : value2
Interrupt event is cleared.
End of enumeration elements list.
TIRC : Transmit Interrupt Flag for SSC1 Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt event is not cleared.
0b1 : value2
Interrupt event is cleared.
End of enumeration elements list.
RIRC : Receive Interrupt Flag for SSC1 Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt event is not cleared.
0b1 : value2
Interrupt event is cleared.
End of enumeration elements list.
Interrupt Request 2 Clear Register, RESET_TYPE_3
address_offset : 0x17C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIRC : Error Interrupt Flag for SSC2 Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt event is not cleared.
0b1 : value2
Interrupt event is cleared.
End of enumeration elements list.
TIRC : Transmit Interrupt Flag for SSC2 Clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt event is not cleared.
0b1 : value2
Interrupt event is cleared.
End of enumeration elements list.
RIRC : Receive Interrupt Flag for SSC2 Clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt event is not cleared.
0b1 : value2
Interrupt event is cleared.
End of enumeration elements list.
NMI Status Register, RESET_TYPE_4
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FNMIWDT : Watchdog Timer NMI Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No watchdog NMI has occurred.
0b1 : value2
WDT prewarning has occurred.
End of enumeration elements list.
FNMIPLL : PLL NMI Flag
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No PLL NMI has occurred.
0b1 : value2
PLL loss-of-lock has occurred.
End of enumeration elements list.
FNMINVM : NVM Operation Complete NMI Flag
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No NVM NMI has occurred.
0b1 : value2
NVM operation complete event has occurred.
End of enumeration elements list.
FNMIOT : Over-temperature NMI Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No OT NMI has occurred.
0b1 : value2
OT NMI event has occurred.
End of enumeration elements list.
FNMIOWD : Oscillator Watchdog or MI_CLK Watchdog NMI Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No oscillator / MI_CLK watchdog NMI has occurred.
0b1 : value2
Oscillator / MI_CLK watchdog event has occurred.
End of enumeration elements list.
FNMIMAP : NVM Map Error NMI Flag
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No NVM Map Error NMI has occurred.
0b1 : value2
NVM Map Error has occurred.
End of enumeration elements list.
FNMIECC : ECC Error NMI Flag
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No uncorrectable ECC error has occurred on NVM, XRAM.
0b1 : value2
Uncorrectable ECC error has occurred on NVM, RAM.
End of enumeration elements list.
FNMISUP : Supply Prewarning NMI Flag
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No supply prewarning NMI has occurred.
0b1 : value2
Supply prewarning has occurred.
End of enumeration elements list.
Interrupt Request 3 Clear Register, RESET_TYPE_3
address_offset : 0x190 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCU6SR0C : Interrupt Flag 0 for CCU6 Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt event is not cleared.
0b1 : value2
Interrupt event is cleared.
End of enumeration elements list.
CCU6SR1C : Interrupt Flag 1 for CCU6 Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt event is not cleared.
0b1 : value2
Interrupt event is cleared.
End of enumeration elements list.
Interrupt Request 4 Clear Register, RESET_TYPE_3
address_offset : 0x194 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CCU6SR2C : Interrupt Flag 2 for CCU6 Clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt event is not cleared.
0b1 : value2
Interrupt event is cleared.
End of enumeration elements list.
CCU6SR3C : Interrupt Flag 3 for CCU6 Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt event is not cleared.
0b1 : value2
Interrupt event is cleared.
End of enumeration elements list.
Interrupt Enable Register 0, RESET_TYPE_4
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EA : Global Interrupt Mask
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
All pending interrupt requests (except NMI) are blocked from the core.
0b1 : value2
Pending interrupt requests are not blocked from the core.
End of enumeration elements list.
NMI Control Register, RESET_TYPE_4
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NMIWDT : Watchdog Timer NMI Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
WDT NMI is disabled.
0b1 : value2
WDT NMI is enabled.
End of enumeration elements list.
NMIPLL : PLL Loss of Lock NMI Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
PLL Loss of Lock NMI is disabled.
0b1 : value2
PLL Loss of Lock NMI is enabled.
End of enumeration elements list.
NMINVM : NVM Operation Complete NMI Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
NVM operation complete NMI is disabled.
0b1 : value2
NVM operation complete NMI is enabled.
End of enumeration elements list.
NMIOT : NMI OT Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
NMI OT is disabled.
0b1 : value2
NMI OT is enabled.
End of enumeration elements list.
NMIOWD : Oscillator Watchdog NMI Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Oscillator watchdog NMI is disabled.
0b1 : value2
Oscillator watchdog NMI is enabled.
End of enumeration elements list.
NMIMAP : NVM Map Error NMI Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : value1
NVM Map Error NMI is disabled.
0b1 : value2
NVM Map Error NMI is enabled.
End of enumeration elements list.
NMIECC : ECC Error NMI Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : value1
ECC Error NMI is disabled.
0b1 : value2
ECC Error NMI is enabled.
End of enumeration elements list.
NMISUP : Supply Prewarning NMI Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Supply NMI is disabled.
0b1 : value2
Supply NMI is enabled.
End of enumeration elements list.
External Interrupt Control Register 0, RESET_TYPE_3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXINT0 : External Interrupt 0 Trigger Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : value1
external interrupt 0 is disabled.
0b01 : value2
Interrupt on rising edge.
0b10 : value3
Interrupt on falling edge.
0b11 : value4
Interrupt on both rising and falling edge.
End of enumeration elements list.
EXINT1 : External Interrupt 1 Trigger Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0b00 : value1
external interrupt 1 is disabled.
0b01 : value2
Interrupt on rising edge.
0b10 : value3
Interrupt on falling edge.
0b11 : value4
Interrupt on both rising and falling edge.
End of enumeration elements list.
EXINT2 : External Interrupt 2 Trigger Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0b00 : value1
external interrupt 2 is disabled.
0b01 : value2
Interrupt on rising edge.
0b10 : value3
Interrupt on falling edge.
0b11 : value4
Interrupt on both rising and falling edge.
End of enumeration elements list.
MON_Trig_Sel : MON Input Trigger Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0b00 : value1
external interrupt MON is disabled.
0b01 : value2
Interrupt on rising edge.
0b10 : value3
Interrupt on falling edge.
0b11 : value4
Interrupt on both rising and falling edge.
End of enumeration elements list.
Interrupt Request 0 Clear Register, RESET_TYPE_3
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXINT0RC : Interrupt Flag for External Interrupt 0x on rising edge clear
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt on rising edge event is not cleared.
0b1 : value2
Interrupt on rising edge event is cleared.
End of enumeration elements list.
EXINT0FC : Interrupt Flag for External Interrupt 0x on falling edge clear
bits : 1 - 0 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt on falling edge event is not cleared.
0b1 : value2
Interrupt on falling edge event is cleared.
End of enumeration elements list.
EXINT1RC : Interrupt Flag for External Interrupt 1x on rising edge clear
bits : 2 - 1 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt on rising edge event is not cleared.
0b1 : value2
Interrupt on rising edge event is cleared.
End of enumeration elements list.
EXINT1FC : Interrupt Flag for External Interrupt 1x on falling edge clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt on falling edge event is not cleared.
0b1 : value2
Interrupt on falling edge event is cleared.
End of enumeration elements list.
EXINT2RC : Interrupt Flag for External Interrupt 2x on rising edge clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt on rising edge event is not cleared.
0b1 : value2
Interrupt on rising edge event is cleared.
End of enumeration elements list.
EXINT2FC : Interrupt Flag for External Interrupt 2x on falling edge clear
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt on falling edge event is not cleared.
0b1 : value2
Interrupt on falling edge event is cleared.
End of enumeration elements list.
MONRC : Interrupt Flag for External Interrupt MON on rising edge clear
bits : 6 - 5 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt on rising edge event is not cleared.
0b1 : value2
Interrupt on rising edge event is cleared.
End of enumeration elements list.
MONFC : Interrupt Flag for External Interrupt MON on falling edge clear
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Interrupt on falling edge event is not cleared.
0b1 : value2
Interrupt on falling edge event is cleared.
End of enumeration elements list.
Peripheral Interrupt Enable Register 1, RESET_TYPE_3
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIREN1 : SSC 1 Error Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Error interrupt is disabled
0b1 : value2
Error interrupt is enabled
End of enumeration elements list.
TIREN1 : SSC 1 Transmit Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Transmit interrupt is disabled
0b1 : value2
Transmit interrupt is enabled
End of enumeration elements list.
RIREN1 : SSC 1 Receive Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Receive interrupt is disabled
0b1 : value2
Receive interrupt is enabled
End of enumeration elements list.
RIEN1 : UART 1 Receive Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Receive interrupt is disabled
0b1 : value2
Receive interrupt is enabled
End of enumeration elements list.
TIEN1 : UART 1 Transmit Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Transmit interrupt is disabled
0b1 : value2
Transmit interrupt is enabled
End of enumeration elements list.
Peripheral Interrupt Enable Register 2, RESET_TYPE_3
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIREN2 : SSC 2 Error Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Error interrupt is disabled
0b1 : value2
Error interrupt is enabled
End of enumeration elements list.
TIREN2 : SSC 2 Transmit Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Transmit interrupt is disabled
0b1 : value2
Transmit interrupt is enabled
End of enumeration elements list.
RIREN2 : SSC 2 Receive Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Receive interrupt is disabled
0b1 : value2
Receive interrupt is enabled
End of enumeration elements list.
EXINT2_EN : External Interrupt 2 Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : value1
External interrupt is disabled
0b1 : value2
External interrupt is enabled
End of enumeration elements list.
RIEN2 : UART 2 Receive Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Receive interrupt is disabled
0b1 : value2
Receive interrupt is enabled
End of enumeration elements list.
TIEN2 : UART 2 Transmit Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Transmit interrupt is disabled
0b1 : value2
Transmit interrupt is enabled
End of enumeration elements list.
Peripheral Interrupt Enable Register 3, RESET_TYPE_3
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IE0 : External Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
disabled
0b1 : value2
enabled
End of enumeration elements list.
MONIE : MON Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
disabled
0b1 : value2
enabled
End of enumeration elements list.
MONSTS : MON Input Status
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Status zero
0b1 : value2
Status one
End of enumeration elements list.
Peripheral Interrupt Enable Register 4, RESET_TYPE_3
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IE1 : External Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
disabled
0b1 : value2
enabled
End of enumeration elements list.
Interrupt Request Register 0, RESET_TYPE_3
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXINT0R : Interrupt Flag for External Interrupt 0x on rising edge
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt on rising edge event has not occurred.
0b1 : value2
Interrupt on rising edge event has occurred.
End of enumeration elements list.
EXINT0F : Interrupt Flag for External Interrupt 0x on falling edge
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt on falling edge event has not occurred.
0b1 : value2
Interrupt on falling edge event has occurred.
End of enumeration elements list.
EXINT1R : Interrupt Flag for External Interrupt 1x on rising edge
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt on rising edge event has not occurred.
0b1 : value2
Interrupt on rising edge event has occurred.
End of enumeration elements list.
EXINT1F : Interrupt Flag for External Interrupt 1x on falling edge
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt on falling edge event has not occurred.
0b1 : value2
Interrupt on falling edge event has occurred.
End of enumeration elements list.
EXINT2R : Interrupt Flag for External Interrupt 2x on rising edge
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt on rising edge event has not occurred.
0b1 : value2
Interrupt on rising edge event has occurred.
End of enumeration elements list.
EXINT2F : Interrupt Flag for External Interrupt 2x on falling edge
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt on falling edge event has not occurred.
0b1 : value2
Interrupt on falling edge event has occurred.
End of enumeration elements list.
MONR : Interrupt Flag for External Interrupt MON on rising edge
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt on rising edge event has not occurred.
0b1 : value2
Interrupt on rising edge event has occurred.
End of enumeration elements list.
MONF : Interrupt Flag for External Interrupt MON on falling edge
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt on falling edge event has not occurred.
0b1 : value2
Interrupt on falling edge event has occurred.
End of enumeration elements list.
Power Mode Control Register 0, RESET_TYPE_3
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTAL_ON : OSC_HP Operation in Power Down Mode
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
OSC_HP (XTAL) will be put to Power Down mode by hardware in power save mode.
0b1 : value2
OSC_HP (XTAL) continues to operate in Power Down mode, if enabled by SCU_OSC_CON.XPD.
End of enumeration elements list.
SL : Sleep Mode Enable. Active High.
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLED
Sleep Mode disabled
0b1 : ENABLED
Sleep Mode enabled
End of enumeration elements list.
SD : Slow Down Mode Enable. Active High.
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLED
Slow Down disabled
0b1 : ENABLED
Slow Down enabled
End of enumeration elements list.
PLL Control Register, RESET_TYPE_4
address_offset : 0x44 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCK : PLL Lock Status Flag
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
The frequency difference of fREF and fDIV is greater than allowed. The VCO part of the PLL can not lock on a target frequency.
0b1 : value2
The frequency difference of fREF and fDIV is small enough to enable a stable VCO operation.
End of enumeration elements list.
RESLD : Restart Lock Detection
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No effect.
0b1 : value2
Reset lock flag and restart lock detection.
End of enumeration elements list.
OSCDISC : Oscillator Disconnect
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Oscillator is connected to the PLL
0b1 : value2
Oscillator is disconnected to the PLL.
End of enumeration elements list.
VCOBYP : PLL VCO Bypass Mode Select
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Normal (or freerunning) operation (default)
0b1 : value2
Prescaler Mode VCO is bypassed (PLL output clock is derived from input clock divided by K1-divider)
End of enumeration elements list.
NDIV : PLL N-Divider
bits : 4 - 6 (3 bit)
access : read-write
Enumeration:
0b0000 : value1
N = 8
0b0001 : value2
N = 9
0b0010 : value3
N = 10
0b0011 : value4
N = 12
0b0100 : value5
N = 14
0b0101 : value6
N = 15
0b0110 : value7
N = 16 (default)
0b0111 : value8
N = 18
0b1000 : value9
N = 20
0b1001 : value10
N = 21
0b1010 : value11
N = 22
0b1011 : value12
N = 24
0b1100 : value13
N = 25
0b1101 : value14
N = 26
0b1110 : value15
N = 27
0b1111 : value16
N = 28
End of enumeration elements list.
Clock Control Register 1, RESET_TYPE_4
address_offset : 0x48 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CLKREL : Slow Down Clock Divider for fCCLK Generation
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0b0000 : value1
fsys
0b0001 : value2
fsys/2
0b0010 : value3
fsys/3
0b0011 : value4
fsys/4
0b0100 : value5
fsys/8
0b0101 : value6
fsys/16
0b0110 : value7
fsys/24
0b0111 : value8
fsys/32
0b1000 : value9
fsys/48
0b1001 : value10
fsys/64
0b1010 : value11
fsys/96
0b1011 : value12
fsys/128
0b1100 : value13
fsys/192
0b1101 : value14
fsys/256
0b1110 : value15
fsys/384
0b1111 : value16
fsys/512
End of enumeration elements list.
K2DIV : PLL K2-Divider
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0b00 : value1
K2 = 2
0b01 : value2
K2 = 3
0b10 : value3
K2 = 4
0b11 : value4
K2 = 5
End of enumeration elements list.
K1DIV : PLL K1-Divider
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : value1
K1 = 2
0b1 : value2
K1 = 1
End of enumeration elements list.
VCOSEL : VCOSEL Setting
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
VCOSEL = 0
0b1 : value2
VCOSEL = 1
End of enumeration elements list.
Clock Control Register 2, RESET_TYPE_4
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PBA0CLKREL : PBA0 Clock Divider
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
divide by 1
0b1 : value2
divide by 2
End of enumeration elements list.
Watchdog Timer Control Register, RESET_TYPE_3
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTIN : Watchdog Timer Input Frequency Selection
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Input frequency is fPCLK/2
0b1 : value2
Input frequency is fPCLK/128
End of enumeration elements list.
WDTRS : WDT Refresh Start
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : no_action
WDT not triggered
0b1 : refresh
WDT refresh is triggered
End of enumeration elements list.
WDTEN : WDT Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
WDT is disabled
0b1 : value2
WDT is enabled
End of enumeration elements list.
WDTPR : Watchdog Prewarning Mode Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Normal mode (default after reset)
0b1 : value2
The Watchdog is operating in Prewarning Mode
End of enumeration elements list.
WINBEN : Watchdog Window-Boundary Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Watchdog Window-Boundary feature is disabled. (default)
0b1 : value2
Watchdog Window-Boundary feature is enabled.
End of enumeration elements list.
Analog Peripheral Clock Control 1 Register, RESET_TYPE_4
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PLL_LOCK : PLL Lock Indicator
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b1 : locked
PLL has locked
0b0 : not_locked
PLL not locked
End of enumeration elements list.
APCLK_SET : Set and Overtake Flag for Clock Settings
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Clock Settings are ignored (previous values are hold)
0b1 : value2
Clock Settings Settings are overtaken
End of enumeration elements list.
T3CLK_SEL : Timer 3 Clock Selection
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
LP_CLK is selected
0b1 : value2
MI_CLK is selected
End of enumeration elements list.
CLKWDT_IE : Clock Watchdog Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Interrupt disabled
0b1 : value2
Interrupt enabled
End of enumeration elements list.
BGCLK_SEL : Bandgap Clock Selection
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
LP_CLK is selected
0b1 : value2
fsys is selected
End of enumeration elements list.
BGCLK_DIV : Bandgap Clock Divider
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : value1
divide by 2
0b1 : value2
divide by 1
End of enumeration elements list.
CPCLK_SEL : Charge Pump Clock Selection
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : value1
LP_CLK is selected
0b1 : value2
fsys is selected
End of enumeration elements list.
CPCLK_DIV : Charge Pump Clock Divider
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
divide by 2
0b1 : value2
divide by 1
End of enumeration elements list.
Analog Peripheral Clock Register 1, RESET_TYPE_4
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APCLK1FAC : Analog Module Clock Factor
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Divide by 1
0b01 : value2
Divide by 2
0b10 : value3
Divide by 3
0b11 : value4
Divide by 4
End of enumeration elements list.
APCLK1SCLR : Analog Peripherals Clock Status Clear
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : no_action
no change
0b1 : clear
clear status
End of enumeration elements list.
APCLK1STS : Analog Peripherals Clock Status
bits : 4 - 4 (1 bit)
access : read-only
Enumeration:
0b00 : value1
The MI_CLK clock is in the required range
0b01 : value2
The MI_CLK clock exceeds the higher limit
0b10 : value3
The MI_CLK clock exceeds the lower limit
0b11 : value4
The MI_CLK clock is not inside the specified limit.
End of enumeration elements list.
APCLK3STS : Loss of Clock Status
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No loss of clock
0b1 : value2
Loss of Lock occured
End of enumeration elements list.
APCLK3SCLR : Analog Peripherals Clock Status Clear
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : no_action
no change
0b1 : clear
clear status
End of enumeration elements list.
Analog Peripheral Clock Register 2, RESET_TYPE_4
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
APCLK2FAC : Slow Down Clock Divider for TFILT_CLK Generation
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
0b00000 : value1
fsys
0b00001 : value2
fsys/2
0b00010 : value3
fsys/3
0b00011 : value4
fsys/4
0b00100 : value5
fsys/5
0b00101 : value6
fsys/6
0b00110 : value7
fsys/7
0b00111 : value8
fsys/8
0b01000 : value9
fsys/9
0b01001 : value10
fsys/10
0b01010 : value11
fsys/11
0b01011 : value12
fsys/12
0b11110 : value13
fsys/31
0b11111 : value14
fsys/32
End of enumeration elements list.
APCLK2STS : Analog Peripherals Clock Status
bits : 5 - 5 (1 bit)
access : read-only
Enumeration:
0b00 : value1
The TFILT_CLK clock is in the required range
0b01 : value2
The TFILT_CLK clock exceeds the higher limit
0b10 : value3
The TFILT_CLK clock exceeds the lower limit
0b11 : value4
The TFILT_CLK clock is not inside the specified limit.
End of enumeration elements list.
APCLK2SCLR : Analog Peripherals Clock Status Clear
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : no_action
no change
0b1 : clear
clear status
End of enumeration elements list.
Peripheral Management Control Register 1, RESET_TYPE_3
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADC1_DIS : ADC1 Disable Request. Active high.
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
ADC1 is in normal operation. (default)
0b1 : value2
Request to disable the ADC.
End of enumeration elements list.
SSC1_DIS : SSC1 Disable Request. Active high.
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
SSC1 is in normal operation. (default)
0b1 : value2
Request to disable the SSC1.
End of enumeration elements list.
CCU6_DIS : CCU6 Disable Request. Active high.
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
CCU6 is in normal operation. (default)
0b1 : value2
Request to disable the CCU6.
End of enumeration elements list.
T2_DIS : T2 Disable Request. Active high.
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
T2 is in normal operation. (default)
0b1 : value2
Request to disable the T2.
End of enumeration elements list.
GPT12_DIS : General Purpose Timer 12 Disable Request. Active high.
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
GPT12is in normal operation. (default)
0b1 : value2
Request to disable the GPT12.
End of enumeration elements list.
Peripheral Management Control Register 2, RESET_TYPE_3
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SSC2_DIS : SSC2 Disable Request. Active high.
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
SSC2 is in normal operation. (default)
0b1 : value2
Request to disable the SSC2.
End of enumeration elements list.
T21_DIS : T21 Disable Request. Active high.
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
T21 is in normal operation. (default)
0b1 : value2
Request to disable the T21.
End of enumeration elements list.
T3_DIS : T3 Disable Request. Active high.
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : value1
T3is in normal operation. (default)
0b1 : value2
Request to disable the T3.
End of enumeration elements list.
Reset Control Register, RESET_TYPE_3
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOCKUP : Lockup Flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Lockup Status not active.
0b1 : value2
Lockup Status active.
End of enumeration elements list.
LOCKUP_EN : Lockup Reset Enable Flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Lockup is disabled.
0b1 : value2
Lockup is enabled.
End of enumeration elements list.
Analog Peripheral Clock Control 2 Register, RESET_TYPE_4
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SDADCCLK_DIV : SD-ADC Clock Divider
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : value1
divide by 1
0b01 : value2
divide by 2
0b10 : value3
divide by 4
0b11 : value4
divide by 8
End of enumeration elements list.
T3CLK_DIV : Timer 3 Clock Divider
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0b00 : value1
divide by 1
0b01 : value2
divide by 2
0b10 : value3
divide by 4
0b11 : value4
divide by 8
End of enumeration elements list.
System Control Register 0, RESET_TYPE_4
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVMCLKFAC : NVM Access Clock Factor
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Divide by 1
0b01 : value2
Divide by 2
0b10 : value3
Divide by 3
0b11 : value4
Divide by 4
End of enumeration elements list.
SYSCLKSEL : System Clock Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0b00 : value1
The PLL clock output signal fPLL is used
0b01 : value2
The direct clock input from fOSC is used
0b10 : value3
The direct low-precision clock input from fLP_CLK is used.
0b11 : value4
The direct low-precision clock input from fLP_CLK is used.
End of enumeration elements list.
System Startup Status Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INIT_FAIL : Initialization at startup failed
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : pass
no error during startup detected
0b1 : fail
at least one error during startup detected
End of enumeration elements list.
MRAMINITSTS : Map RAM Initialization Status
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : pass
Map RAM initialization pass
0b1 : fail
Map RAM initialization finished with fails
End of enumeration elements list.
PG100TP_CHKS_ERR : 100 TP Page Checksum Error
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : pass
no checksum error detected
0b1 : fail
100TP checksum error detected
End of enumeration elements list.
Watchdog Timer Reload Register, RESET_TYPE_3
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTREL : Watchdog Timer Reload Value
bits : 0 - 6 (7 bit)
access : read-write
Watchdog Window-Boundary Count, RESET_TYPE_3
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTWINB : Watchdog Window-Boundary Count Value
bits : 0 - 6 (7 bit)
access : read-write
Interrupt Request Register 1, RESET_TYPE_3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIR : Error Interrupt Flag for SSC1
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt event has not occurred.
0b1 : value2
Interrupt event has occurred.
End of enumeration elements list.
TIR : Transmit Interrupt Flag for SSC1
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt event has not occurred.
0b1 : value2
Interrupt event has occurred.
End of enumeration elements list.
RIR : Receive Interrupt Flag for SSC1
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt event has not occurred.
0b1 : value2
Interrupt event has occurred.
End of enumeration elements list.
Watchdog Timer, Low Byte, RESET_TYPE_3
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT : Watchdog Timer Current Value
bits : 0 - 6 (7 bit)
access : read-only
Watchdog Timer, High Byte, RESET_TYPE_3
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDT : Watchdog Timer Current Value
bits : 0 - 6 (7 bit)
access : read-only
Baud Rate Control Register 1, RESET_TYPE_3
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R : Baud Rate Generator Run Control Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Baud-rate generator disabled.
0b1 : value2
Baud-rate generator enabled.
End of enumeration elements list.
BRPRE : Prescaler Bit
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0b000 : value1
fDIV = fPCLK
0b001 : value2
fDIV = fPCLK/2
0b010 : value3
fDIV = fPCLK/4
0b011 : value4
fDIV = fPCLK/8
0b100 : value5
fDIV = fPCLK/16
0b101 : value6
fDIV = fPCLK/32
End of enumeration elements list.
Baud Rate Timer/Reload Register, Low Byte 1, RESET_TYPE_3
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FD_SEL : Fractional Divider Selection
bits : 0 - 3 (4 bit)
access : read-write
BR_VALUE : Baud Rate Timer/Reload Value
bits : 5 - 6 (2 bit)
access : read-write
Baud Rate Timer/Reload Register, High Byte, RESET_TYPE_3
address_offset : 0x90 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BR_VALUE : Baud Rate Timer/Reload Value
bits : 0 - 6 (7 bit)
access : read-write
LIN Status Register, RESET_TYPE_3
address_offset : 0x94 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRDIS : Baud Rate Detection Disable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Break/Synch detection is enabled.
0b1 : value2
Break/Synch detection is disabled.
End of enumeration elements list.
BGSEL : Baud Rate Select for Detection
bits : 1 - 1 (1 bit)
access : read-write
BRK : Break Field Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Break Field is not detected.
0b1 : value2
Break Field is detected.
End of enumeration elements list.
EOFSYN : End of SYN Byte Interrupt Flag
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
End of SYN Byte is not detected.
0b1 : value2
End of SYN Byte is detected.
End of enumeration elements list.
ERRSYN : SYN Byte Error Interrupt Flag
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Error is not detected in SYN Byte.
0b1 : value2
Error is detected in SYN Byte.
End of enumeration elements list.
SYNEN : End of SYN Byte and SYN Byte Error Interrupts Enable
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : value1
End of SYN Byte and SYN Byte Error Interrupts are not enabled.
0b1 : value2
End of SYN Byte and SYN Byte Error Interrupts are enabled.
End of enumeration elements list.
Baud Rate Control Register 2, RESET_TYPE_3
address_offset : 0x98 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
R : Baud Rate Generator Run Control Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Baud-rate generator disabled.
0b1 : value2
Baud-rate generator enabled.
End of enumeration elements list.
BRPRE : Prescaler Bit
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
0b000 : value1
fDIV = fPCLK
0b001 : value2
fDIV = fPCLK/2
0b010 : value3
fDIV = fPCLK/4
0b011 : value4
fDIV = fPCLK/8
0b100 : value5
fDIV = fPCLK/16
0b101 : value6
fDIV = fPCLK/32
End of enumeration elements list.
Baud Rate Timer/Reload Register, Low Byte 2, RESET_TYPE_3
address_offset : 0x9C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
FD_SEL : Fractional Divider Selection
bits : 0 - 3 (4 bit)
access : read-write
BR_VALUE : Baud Rate Timer/Reload Value
bits : 5 - 6 (2 bit)
access : read-write
Baud Rate Timer/Reload Register, High Byte, RESET_TYPE_3
address_offset : 0xA0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BR_VALUE : Baud Rate Timer/Reload Value
bits : 0 - 6 (7 bit)
access : read-write
LIN Status Clear Register, RESET_TYPE_3
address_offset : 0xA4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
BRKC : Break Field Flag Clear
bits : 3 - 2 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Break Field is not cleared.
0b1 : value2
Break Field is cleared.
End of enumeration elements list.
EOFSYNC : End of SYN Byte Interrupt Flag Clear
bits : 4 - 3 (0 bit)
access : write-only
Enumeration:
0b0 : value1
End of SYN Byte is not cleared.
0b1 : value2
End of SYN Byte is cleared.
End of enumeration elements list.
ERRSYNC : SYN Byte Error Interrupt Flag
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
0b0 : value1
Error in SYN Byte not cleared.
0b1 : value2
Error in SYN Byte cleared.
End of enumeration elements list.
Identity Register, RESET_TYPE_3
address_offset : 0xA8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VERID : Version ID
bits : 0 - 1 (2 bit)
access : read-only
PRODID : Product ID
bits : 3 - 6 (4 bit)
access : read-only
Password Register, RESET_TYPE_3
address_offset : 0xAC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MODE : Bit-Protection Scheme Control Bit
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Scheme Disabled
0b11 : value2
Scheme Enabled (default)
End of enumeration elements list.
PROTECT_S : Bit-Protection Signal Status Bit
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Software is able to write to all protected bits.
0b1 : value2
Software is unable to write to any protected bits.
End of enumeration elements list.
PASS : Password Bits
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0b11000 : value1
Enables writing of the bit field MODE.
0b10011 : value2
Opens access to writing of all protected bits.
0b10101 : value3
Closes access to writing of all protected bits.
End of enumeration elements list.
OSC Control Register, RESET_TYPE_4
address_offset : 0xB0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
OSCSS : Oscillator Source Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : value1
PLL internal oscillator OSC_PLL (fINT) is selected synchronously as fR.
0b01 : value2
XTAL (fOSC from OSC_HP) is selected synchronously as fR.
0b10 : value3
PLL internal oscillator OSC_PLL (fINT) is selected asynchronously as fR.
0b11 : value4
PLL internal oscillator OSC_PLL (fINT) is selected asynchronously as fR.
End of enumeration elements list.
OSCWDTRST : Oscillator Watchdog Reset
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No effect.
0b1 : value2
Reset OSC2L flag and restart the oscillator watchdog of the PLL.
End of enumeration elements list.
OSC2L : OSC-Too-Low Condition Flag
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : value1
fOSC is above threshold.
0b1 : value2
fOSC is below threshold.
End of enumeration elements list.
XPD : XTAL (OSC_HP) Power Down Control
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
XTAL (OSC_HP) is not powered down.
0b1 : value2
XTAL (OSC_HP) is powered down.
End of enumeration elements list.
OSCTRIM_8 : OSC_PLL Trim Configuration Bit [8]
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
trimming disabled
0b1 : value2
trimming enabled
End of enumeration elements list.
Clock Output Control Register, RESET_TYPE_4
address_offset : 0xB4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
COREL : Clock Output Divider
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0b0000 : value1
fsys
0b0001 : value2
fsys/2
0b0010 : value3
fsys/3
0b0011 : value4
fsys/4
0b0100 : value5
fsys/6
0b0101 : value6
fsys/8
0b0110 : value7
fsys/10
0b0111 : value8
fsys/12
0b1000 : value9
fsys/14
0b1001 : value10
fsys/16
0b1010 : value11
fsys/18
0b1011 : value12
fsys/20
0b1100 : value13
fsys/24
0b1101 : value14
fsys/32
0b1110 : value15
fsys/36
0b1111 : value16
fsys/40
End of enumeration elements list.
COUTS0 : Clock Out Source Select Bit 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Oscillator output frequency is selected.
0b1 : value2
Clock output frequency is chosen by the bit field COREL.
End of enumeration elements list.
TLEN : Toggle Latch Enable
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Toggle Latch is disabled. Clock output frequency is chosen by the bit field COREL.
0b1 : value2
Toggle Latch is enabled. Clock output frequency is half of the frequency that is chosen by the bit field COREL. The resulting output frequency has 50 percent70 duty cycle.
End of enumeration elements list.
COUTS1 : Clock Out Source Select Bit 1
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : value1
fCCLK is selected.
0b1 : value2
Based on setting of COUTS0.
End of enumeration elements list.
EN : CLKOUT Enable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No external clock signal is provided
0b1 : value2
The configured external clock signal is provided
End of enumeration elements list.
Peripheral Input Select Register, RESET_TYPE_3
address_offset : 0xB8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EXINT0IS : External Interrupt 0 Input Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : value1
External Interrupt Input EXINT0_0 is selected (P2.0).
0b01 : value2
External Interrupt Input EXINT0_1 is selected (P1.2).
0b10 : value3
External Interrupt Input EXINT0_2 is selected (P0.1).
0b11 : value4
External Interrupt Input EXINT0_3 is selected (P2.3).
End of enumeration elements list.
EXINT1IS : External Interrupt 1 Input Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0b00 : value1
External Interrupt Input EXINT1_0 is selected (P1.1).
0b01 : value2
External Interrupt Input EXINT1_1 is selected (P1.3).
0b10 : value3
External Interrupt Input EXINT1_2 is selected (P1.0).
0b11 : value4
External Interrupt Input EXINT1_3 is selected (P2.4).
End of enumeration elements list.
EXINT2IS : External Interrupt 2 Input Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0b00 : value1
External Interrupt Input EXINT2_0 is selected (P2.7).
0b01 : value2
External Interrupt Input EXINT2_1 is selected (P1.4).
0b10 : value3
External Interrupt Input EXINT2_2 is selected (P0.4).
0b11 : value4
External Interrupt Input EXINT2_3 is selected (P0.0).
End of enumeration elements list.
URIOS1 : UART1 Input/Output Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : value1
UART1 Receiver Input RXD1_0 (Connection to LIN is available).
0b1 : value2
UART1 Receiver Input RXD1_1 (Connection to LIN is not available).
End of enumeration elements list.
U_TX_CONDIS : UART1 TxD Connection Disable
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
UART1-TX-Output -LIN Transmitter TX Input Connection available.
0b1 : value2
UART1-TX-Output -LIN Transmitter TX Input Connection not available (can be stimulated by external port pin).
End of enumeration elements list.
Peripheral Input Select Register 1, RESET_TYPE_3
address_offset : 0xBC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPT12CAPINB : GPT12 CAPINB Input Control
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
GPT12 CAPINB Input is connected to P0.3
0b1 : value2
GPT12 CAPINB Input is connected to BEMF comparator
End of enumeration elements list.
T2EXCON : Timer 2 External Input Control
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Timer 2 Input T2EX is selected by bit field MODPISEL.T2EXIS.
0b1 : value2
Timer 2 Input T2EX is connected to signal from analog subsystem.
End of enumeration elements list.
T21EXCON : Timer 21 External Input Control
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Timer 21 Input T21EX is selected by bit field MODPISEL.T2EXIS.
0b1 : value2
Timer 21 Input T21EX is connected to signal from analog subsystem.
End of enumeration elements list.
Interrupt Request Register 2, RESET_TYPE_3
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
EIR : Error Interrupt Flag for SSC2
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt event has not occurred.
0b1 : value2
Interrupt event has occurred.
End of enumeration elements list.
TIR : Transmit Interrupt Flag for SSC2
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt event has not occurred.
0b1 : value2
Interrupt event has occurred.
End of enumeration elements list.
RIR : Receive Interrupt Flag for SSC2
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
Interrupt event has not occurred.
0b1 : value2
Interrupt event has occurred.
End of enumeration elements list.
Peripheral Input Select Register 2, RESET_TYPE_3
address_offset : 0xC0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T2IS : Timer 2 Input Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Timer 2 Input T2_0 is selected.
End of enumeration elements list.
T21IS : Timer 21 Input Select
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Timer 21 Input T21_0 is selected.
0b01 : value2
Timer 21 Input T21_1 is selected.
0b10 : value3
Timer 21 Input T21_2 is selected.
End of enumeration elements list.
T2EXIS : Timer 2 External Input Select
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Timer 2 Input T2EX_0 is selected.
0b01 : value2
Timer 2 Input T2EX_1 is selected.
End of enumeration elements list.
T21EXIS : Timer 21 External Input Select
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Timer 21 Input T21EX_0 is selected.
0b01 : value2
Timer 21 Input T21EX_1 is selected.
0b10 : value3
Timer 21 Input T21EX_2 is selected.
0b11 : value4
Timer 21 Input T21EX_3 is selected.
End of enumeration elements list.
Peripheral Input Select Register, RESET_TYPE_3
address_offset : 0xC4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
URIOS2 : UART2 Input/Output Select
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : value1
UART2 Receiver Input RXD2_0 and Transmitter Output TXD2_0 is selected.
0b1 : value2
UART2 Receiver Input RXD2_1 and Transmitter Output TXD2_1 is selected.
End of enumeration elements list.
Module Suspend Control Register 1, RESET_TYPE_3
address_offset : 0xC8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WDTSUSP : SCU Watchdog Timer Debug Suspend Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
WDT will not be suspended.
0b1 : value2
WDT will be suspended.
End of enumeration elements list.
T12SUSP : Timer 12 Debug Suspend Bit
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Timer 12 in Capture/Compare Unit will not be suspended.
0b1 : value2
Timer 12 in Capture/Compare Unit will be suspended.
End of enumeration elements list.
T13SUSP : Timer 13 Debug Suspend Bit
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Timer 13 in Capture/Compare Unit will not be suspended.
0b1 : value2
Timer 13 in Capture/Compare Unit will be suspended.
End of enumeration elements list.
T2_SUSP : Timer2 Debug Suspend Bit
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Timer2 will not be suspended.
0b1 : value2
Timer2 will be suspended.
End of enumeration elements list.
GPT12_SUSP : GPT12 Debug Suspend Bit
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
GPT12 will not be suspended.
0b1 : value2
GPT12 will be suspended.
End of enumeration elements list.
T21_SUSP : Timer21 Debug Suspend Bit
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Timer21 will not be suspended.
0b1 : value2
Timer21 will be suspended.
End of enumeration elements list.
Module Suspend Control Register 2, RESET_TYPE_3
address_offset : 0xCC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T3_SUSP : Measurement Unit Debug Suspend Bit
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Timer 3 will not be suspended.
0b1 : value2
Timer 3 will be suspended.
End of enumeration elements list.
MU_SUSP : Measurement Unit Debug Suspend Bit
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
MU will not be suspended.
0b1 : value2
MU will be suspended.
End of enumeration elements list.
ADC1_SUSP : ADC1 Unit Debug Suspend Bit
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
ADC1 will not be suspended.
0b1 : value2
ADC1 will be suspended.
End of enumeration elements list.
GPT12 Peripheral Input Select Register, RESET_TYPE_3
address_offset : 0xD0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
GPT12 : GPT12 TIN3B / TIN4D Input Select
bits : 0 - 2 (3 bit)
access : read-write
Enumeration:
0b0000 : value1
CC60
0b0001 : value2
CC61
0b0010 : value3
CC62
0b0011 : value4
T12 ZM.
0b0100 : value5
T12 PM.
0b0101 : value6
T12 CM0.
0b0110 : value7
T12 CM1.
0b0111 : value8
T12 CM2.
0b1000 : value9
T13 PM.
0b1001 : value10
T13 ZM.
0b1010 : value11
T13 CM.
0b1011 : value12
any pos or neg edge on CC60/61/62.
0b1100 : value13
RES.
0b1101 : value14
RES.
0b1110 : value15
RES.
0b1111 : value16
RES.
End of enumeration elements list.
TRIG_CONF : CCU6 Trigger Configuration.
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Trigger is just for one measurement (default)
0b1 : value2
Trigger is present until next input edge (selected by GPT12) - continuos measurement.
End of enumeration elements list.
T3_GPT12_SEL : CCU6_INT_SEL.
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : value1
CCU6_INT is triggered by Timer 3
0b1 : value2
CCU6_INT is triggered by GPT12PISEL.GPT12.
End of enumeration elements list.
Error Detection and Correction Control Register, RESET_TYPE_3
address_offset : 0xD4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RIE : RAM Double Bit ECC Error Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No NMI is generated when a double bit ECC error occurs reading RAM.
0b1 : value2
An NMI is generated when a double bit ECC error occurs reading RAM.
End of enumeration elements list.
NVMIE : NVM Double Bit ECC Error Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No NMI is generated when a double bit ECC error occurs reading NVM.
0b1 : value2
An NMI is generated when a double bit ECC error occurs reading NVM.
End of enumeration elements list.
Error Detection and Correction Status Register, RESET_TYPE_4
address_offset : 0xD8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RDBE : RAM Double Bit Error
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No double bit error on RAM has occured.
0b1 : value2
A double bit error on RAM has occured.
End of enumeration elements list.
NVMDBE : NVM Double Bit Error
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No double bit error on NVM has occured.
0b1 : value2
A double bit error on NVM has occured.
End of enumeration elements list.
RSBE : RAM Single Bit Error
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No single bit error on RAM has occured.
0b1 : value2
A single bit error on RAM has occured.
End of enumeration elements list.
Memory Status Register, RESET_TYPE_3
address_offset : 0xDC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SECTORINFO : Sector Information
bits : 0 - 4 (5 bit)
access : read-write
SASTATUS : Service Algorithm Status
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Depending on SECTORINFO, there are two possible outcomes: For SECTORINFO = 00H, NVM initialization is successful and no SA is executed. For SECTORINFO = values other than 00H, SA execution is successful and only one map error is fixed.
0b01 : value2
SA execution is successful. More than one mapping error is fixed.
0b10 : value3
SA execution is not successful. Map error exists in one sector.
0b11 : value4
SA execution is not successful. At least one sector failed (this includes also the case where a sector is repaired but another sector is still failing).
End of enumeration elements list.
NVM Protection Status Register, RESET_TYPE_4
address_offset : 0xE0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVMPROTSTSL_0 : NVM Protection Status Register Low Flags
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
The data in sectors of the non-linearly mapped area can not be changed
0b1 : value2
The data in sectors of the non-linearly mapped area can be changed
End of enumeration elements list.
NVMPROTSTSL_1 : NVM Protection Status Register Low Flags
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
The data in sectors of the linearly mapped area can not be changed
0b1 : value2
The data in sectors of the linearly mapped area can be changed
End of enumeration elements list.
NVMPROTSTSL_2 : NVM Protection Status Register Low Flags
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
The data in sectors of the non-linearly mapped area can not be read
0b1 : value2
The data in sectors of the non-linearly mapped area can be read
End of enumeration elements list.
NVMPROTSTSL_3 : NVM Protection Status Register Low Flags
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
The data in sectors of the linearly mapped area can not be read
0b1 : value2
The data in sectors of the linearly mapped area can be read
End of enumeration elements list.
Memory Access Status Register, RESET_TYPE_3
address_offset : 0xE4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NVM_PROT_ERR : NVM Access Protection
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Protection error
0b1 : value2
Protection error
End of enumeration elements list.
NVM_ADDR_ERR : NVM Address Protection
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Protection error
0b1 : value2
Protection error
End of enumeration elements list.
NVM_SFR_PROT_ERR : NVM SFR Access Protection
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Protection error
0b1 : value2
Protection error
End of enumeration elements list.
NVM_SFR_ADDR_ERR : NVM SFR Address Protection
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Protection error
0b1 : value2
Protection error
End of enumeration elements list.
ROM_PROT_ERR : ROM Access Protection
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Protection error
0b1 : value2
Protection error
End of enumeration elements list.
ROM_ADDR_ERR : ROM Address Protection
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Protection error
0b1 : value2
Protection error
End of enumeration elements list.
RAM_PROT_ERR : RAM Access Protection
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
0b0 : value1
No Protection error
0b1 : value2
Protection error
End of enumeration elements list.
Port Output Control Register, RESET_TYPE_3
address_offset : 0xE8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDM0 : P0.0 Port Driver Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0b000 : value1
Not used
0b001 : value2
Not used
0b010 : value3
Not Used
0b011 : value4
Weak driver
0b100 : value5
Medium driver
0b101 : value6
Medium driver
0b110 : value7
Medium driver
0b111 : value8
Weak driver
End of enumeration elements list.
PDM1 : P0.1 Port Driver Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0b000 : value1
Not used
0b001 : value2
Not used
0b010 : value3
Not Used
0b011 : value4
Weak driver
0b100 : value5
Medium driver
0b101 : value6
Medium driver
0b110 : value7
Medium driver
0b111 : value8
Weak driver
End of enumeration elements list.
Port Output Control Register, RESET_TYPE_3
address_offset : 0xEC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDM2 : P0.2 Port Driver Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0b000 : value1
Strong driver and sharp edge mode
0b001 : value2
Strong driver and medium edge mode
0b010 : value3
Strong driver and soft edge mode
0b011 : value4
Weak driver
0b100 : value5
Medium driver
0b101 : value6
Medium driver
0b110 : value7
Medium driver
0b111 : value8
Weak driver
End of enumeration elements list.
PDM3 : P0.3 Port Driver Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0b000 : value1
Not used
0b001 : value2
Not used
0b010 : value3
Not Used
0b011 : value4
Weak driver
0b100 : value5
Medium driver
0b101 : value6
Medium driver
0b110 : value7
Medium driver
0b111 : value8
Weak driver
End of enumeration elements list.
Port Output Control Register, RESET_TYPE_3
address_offset : 0xF0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDM4 : P0.4 Port Driver Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0b000 : value1
Not used
0b001 : value2
Not used
0b010 : value3
Not Used
0b011 : value4
Weak driver
0b100 : value5
Medium driver
0b101 : value6
Medium driver
0b110 : value7
Medium driver
0b111 : value8
Weak driver
End of enumeration elements list.
Temperature Compensation Control Register, RESET_TYPE_3
address_offset : 0xF4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TCC : Temperature Compensation Control
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : value1
TJ: -40 oC to 0 oC
0b01 : value2
TJ: 0 oC to 40 oC
0b10 : value3
TJ: 40 oC to 80 oC
0b11 : value4
TJ: 80 oC to 150 oC
End of enumeration elements list.
Port Output Control Register, RESET_TYPE_3
address_offset : 0xF8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDM0 : P1.0 Port Driver Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0b000 : value1
Not used
0b001 : value2
Not used
0b010 : value3
Not Used
0b011 : value4
Weak driver
0b100 : value5
Medium driver
0b101 : value6
Medium driver
0b110 : value7
Medium driver
0b111 : value8
Weak driver
End of enumeration elements list.
PDM1 : P1.1 Port Driver Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0b000 : value1
Not used
0b001 : value2
Not used
0b010 : value3
Not Used
0b011 : value4
Weak driver
0b100 : value5
Medium driver
0b101 : value6
Medium driver
0b110 : value7
Medium driver
0b111 : value8
Weak driver
End of enumeration elements list.
Port Output Control Register, RESET_TYPE_3
address_offset : 0xFC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PDM2 : P1.2 Port Driver Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0b000 : value1
Not used
0b001 : value2
Not used
0b010 : value3
Not Used
0b011 : value4
Weak driver
0b100 : value5
Medium driver
0b101 : value6
Medium driver
0b110 : value7
Medium driver
0b111 : value8
Weak driver
End of enumeration elements list.
PDM3 : P1.3 Port Driver Mode
bits : 4 - 5 (2 bit)
access : read-write
Enumeration:
0b000 : value1
Strong driver and sharp edge mode
0b001 : value2
Strong driver and medium edge mode
0b010 : value3
Strong driver and soft edge mode
0b011 : value4
Weak driver
0b100 : value5
Medium driver
0b101 : value6
Medium driver
0b110 : value7
Medium driver
0b111 : value8
Weak driver
End of enumeration elements list.
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