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SCUPM

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

AMCLK_FREQ_STS

SYS_ISCLR

SYS_IS

SYS_SUPPLY_IRQ_STS

SYS_SUPPLY_IRQ_CTRL

SYS_SUPPLY_IRQ_CLR

SYS_IRQ_CTRL

PCU_CTRL_STS

WDT1_TRIG

AMCLK_CTRL

BDRV_ISCLR

BDRV_IS

BDRV_IRQ_CTRL

STCALIB

BFSTS

DBFA

SBFA

BFSTS_CLR

AMCLK_TH_HYS


AMCLK_FREQ_STS

Analog Module Clock Frequency Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMCLK_FREQ_STS AMCLK_FREQ_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMCLK1_FREQ AMCLK2_FREQ

AMCLK1_FREQ : Current frequency of Analog Module Clock System Clock (MI_CLK)
bits : 0 - 4 (5 bit)
access : read-only

AMCLK2_FREQ : Current frequency of Analog Module Clock 2 (TFILT_CLK)
bits : 8 - 12 (5 bit)
access : read-only


SYS_ISCLR

System Interrupt Status Clear
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_ISCLR SYS_ISCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIN_OC_ICLR LIN_OT_ICLR LIN_TMOUT_ICLR PMU_OTWARN_ICLR PMU_OT_ICLR SYS_OTWARN_ICLR SYS_OT_ICLR REFBG_LOTHWARN_ICLR REFBG_UPTHWARN_ICLR VREF5V_LOWTH_ICLR VREF5V_UPTH_ICLR VREF5V_OVL_ICLR ADC2_ESM_ICLR ADC3_EOC_ICLR ADC4_EOC_ICLR

LIN_OC_ICLR : LIN Overcurrent interrupt status
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

LIN_OT_ICLR : LIN Overtemperature interrupt status
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

LIN Overtemperature occurred

End of enumeration elements list.

LIN_TMOUT_ICLR : LIN TXD timeout
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

LIN Overtemperature occurred

End of enumeration elements list.

PMU_OTWARN_ICLR : PMU Regulator Overtemperature Prewarning (ADC2, Channel 9) interrupt status
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

PMU_OT_ICLR : PMU Regulator Overtemperature Shutdown (ADC2, Channel 9) interrupt status
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

SYS_OTWARN_ICLR : System Overtemperature Prewarning (ADC2, Channel 8) interrupt status
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

SYS_OT_ICLR : System Overtemperature Shutdown (ADC2, Channel 8) interrupt status
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

REFBG_LOTHWARN_ICLR : 8 Bit ADC2 Reference Undervoltage (ADC2, Channel 5) interrupt status
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

REFBG_UPTHWARN_ICLR : 8 Bit ADC2 Reference Overvoltage (ADC2, Channel 5) interrupt status
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

VREF5V_LOWTH_ICLR : VREF5V ADC1 Reference Undervoltage (ADC2, Channel 4) Interrupt Status
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

VREF5V_UPTH_ICLR : VREF5V ADC1 Reference Overvoltage (ADC2, Channel 4) Interrupt Status
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

VREF5V_OVL_ICLR : VREF5V Overload Interrupt Status
bits : 14 - 13 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

ADC2_ESM_ICLR : ADC2 Exceptional Sequence Measurement Interrupt Status
bits : 15 - 14 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

ADC3_EOC_ICLR : ADC3 EOC Interrupt Status
bits : 22 - 21 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

ADC4_EOC_ICLR : ADC4 EOC Interrupt Status
bits : 23 - 22 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.


SYS_IS

System Interrupt Status
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IS SYS_IS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIN_OC_IS LIN_OT_IS LIN_TMOUT_IS PMU_OTWARN_IS PMU_OT_IS SYS_OTWARN_IS SYS_OT_IS REFBG_LOTHWARN_IS REFBG_UPTHWARN_IS VREF5V_LOWTH_IS VREF5V_UPTH_IS VREF5V_OVL_IS ADC2_ESM_IS ADC3_EOC_IS ADC4_EOC_IS

LIN_OC_IS : LIN Overcurrent interrupt status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

LIN Overcurrent occurred

End of enumeration elements list.

LIN_OT_IS : LIN Overtemperature interrupt status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

LIN Overtemperature occurred

End of enumeration elements list.

LIN_TMOUT_IS : LIN TXD timeout
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

LIN TXD timeout occurred

End of enumeration elements list.

PMU_OTWARN_IS : PMU Regulator Overtemperature Prewarning (ADC2, Channel 9) interrupt status
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

PMU_OT_IS : PMU Regulator Overtemperature Shutdown (ADC2, Channel 9) interrupt status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

SYS_OTWARN_IS : System Overtemperature Prewarning (ADC2, Channel 8) interrupt status
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

SYS_OT_IS : System Overtemperature Shutdown (ADC2, Channel 8) interrupt status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

REFBG_LOTHWARN_IS : 8 Bit ADC2 Reference Undervoltage (ADC2, Channel 5) interrupt status
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

REFBG_UPTHWARN_IS : 8 Bit ADC2 Reference Overvoltage (ADC2, Channel 5) interrupt status
bits : 11 - 10 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

VREF5V_LOWTH_IS : VREF5V ADC1 Reference Undervoltage (ADC2, Channel 4) Interrupt Status
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

VREF5V_UPTH_IS : VREF5V ADC1 Reference Overvoltage (ADC2, Channel 4) Interrupt Status
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

VREF5V_OVL_IS : VREF5V Overload Interrupt Status
bits : 14 - 13 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

ADC2_ESM_IS : ADC2 Exceptional Sequence Measurement Interrupt Status
bits : 15 - 14 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

ADC3_EOC_IS : ADC3 EOC Interrupt Status
bits : 22 - 21 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.

ADC4_EOC_IS : ADC4 EOC Interrupt Status
bits : 23 - 22 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

at least one interrupt status set

End of enumeration elements list.


SYS_SUPPLY_IRQ_STS

System Supply Interrupt Status
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SUPPLY_IRQ_STS SYS_SUPPLY_IRQ_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBAT_UV_IS VS_UV_IS VDD5V_UV_IS VDD1V5_UV_IS VBAT_OV_IS VS_OV_IS VDD5V_OV_IS VDD1V5_OV_IS VBAT_UV_STS VS_UV_STS VDD5V_UV_STS VDD1V5_UV_STS VBAT_OV_STS VS_OV_STS VDD5V_OV_STS VDD1V5_OV_STS

VBAT_UV_IS : VBAT Undervoltage Interrupt Status (ADC2 channel 0)
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : No_Undervoltage_Interrupt

occurred

0b1 : Undervoltage_Interrupt

occurred

End of enumeration elements list.

VS_UV_IS : VS Undervoltage Interrupt Status (ADC2 channel 1)
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b0 : No_Undervoltage_Interrupt

occurred

0b1 : Undervoltage_Interrupt

occurred

End of enumeration elements list.

VDD5V_UV_IS : VDDP Undervoltage Interrupt Status (ADC2 channel 5)
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

0b0 : No_Undervoltage_Interrupt

occurred

0b1 : Undervoltage_Interrupt

occurred

End of enumeration elements list.

VDD1V5_UV_IS : VDDC Undervoltage Interrupt Status (ADC2 channel 8)
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

0b0 : No_Undervoltage_Interrupt

occurred

0b1 : Undervoltage_Interrupt

occurred

End of enumeration elements list.

VBAT_OV_IS : VBAT Overvoltage Interrupt Status (ADC2 channel 0)
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

0b0 : No_Overvoltage_Interrupt

occurred

0b1 : Overvoltage_Interrupt

occurred

End of enumeration elements list.

VS_OV_IS : VS Overvoltage Interrupt Status (ADC2 channel 1)
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

0b0 : No_Overvoltage_Interrupt

occurred

0b1 : Overvoltage_Interrupt

occurred

End of enumeration elements list.

VDD5V_OV_IS : VDDP Overvoltage Interrupt Status (ADC2 channel 5)
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

0b0 : No_Overvoltage_Interrupt

occurred

0b1 : Overvoltage_Interrupt

occurred

End of enumeration elements list.

VDD1V5_OV_IS : VDDC Overvoltage Interrupt Status (ADC2 channel 8)
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

0b0 : No_Overvoltage_Interrupt

occurred

0b1 : Overvoltage_Interrupt

occurred

End of enumeration elements list.

VBAT_UV_STS : VBAT Undervoltage Status
bits : 16 - 15 (0 bit)
access : read-only

Enumeration:

0b0 : No_Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VS_UV_STS : VS Undervoltage Status
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0b0 : No_Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VDD5V_UV_STS : VDDP Undervoltage Status
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0b0 : No_Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VDD1V5_UV_STS : VDDC Undervoltage Status
bits : 19 - 18 (0 bit)
access : read-only

Enumeration:

0b0 : No_Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VBAT_OV_STS : VBAT Overvoltage Status
bits : 20 - 19 (0 bit)
access : read-only

Enumeration:

0b0 : No_Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.

VS_OV_STS : VS Overvoltage Interrupt Status
bits : 21 - 20 (0 bit)
access : read-only

Enumeration:

0b0 : No_Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.

VDD5V_OV_STS : VDDP Overvoltage Status
bits : 22 - 21 (0 bit)
access : read-only

Enumeration:

0b0 : No_Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.

VDD1V5_OV_STS : VDDC Overvoltage Status
bits : 23 - 22 (0 bit)
access : read-only

Enumeration:

0b0 : No_Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.


SYS_SUPPLY_IRQ_CTRL

System Supply Interrupt Control
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SUPPLY_IRQ_CTRL SYS_SUPPLY_IRQ_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBAT_UV_IE VS_UV_IE VDD5V_UV_IE VDD1V5_UV_IE VBAT_OV_IE VS_OV_IE VDD5V_OV_IE VDD1V5_OV_IE

VBAT_UV_IE : VBAT Undervoltage Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VS_UV_IE : VS Undervoltage Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VDD5V_UV_IE : VDD5V Undervoltage Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VDD1V5_UV_IE : VDD1V5 Undervoltage Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VBAT_OV_IE : VBAT Overvoltage Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VS_OV_IE : VS Overvoltage Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VDD5V_OV_IE : VDD5V Overvoltage Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VDD1V5_OV_IE : VDD1V5 Overvoltage Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.


SYS_SUPPLY_IRQ_CLR

System Supply Interrupt Status Clear
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_SUPPLY_IRQ_CLR SYS_SUPPLY_IRQ_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VBAT_UV_ICLR VS_UV_ICLR VDD5V_UV_ICLR VDD1V5_UV_ICLR VBAT_OV_ICLR VS_OV_ICLR VDD5V_OV_ICLR VDD1V5_OV_ICLR VBAT_UV_SCLR VS_UV_SCLR VDD5V_UV_SCLR VDD1V5_UV_SCLR VBAT_OV_SCLR VS_OV_SCLR VDD5V_OV_SCLR VDD1V5_OV_SCLR

VBAT_UV_ICLR : VBAT Undervoltage Interrupt Status (ADC2 channel 0)
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b0 : No_Undervoltage_Interrupt

occurred

0b1 : Undervoltage_Interrupt

occurred

End of enumeration elements list.

VS_UV_ICLR : VS Undervoltage Interrupt Status (ADC2 channel 1)
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b0 : No_Undervoltage_Interrupt

occurred

0b1 : Undervoltage_Interrupt

occurred

End of enumeration elements list.

VDD5V_UV_ICLR : VDDP Undervoltage Interrupt Status (ADC2 channel 5)
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

0b0 : No_Undervoltage_Interrupt

occurred

0b1 : Undervoltage_Interrupt

occurred

End of enumeration elements list.

VDD1V5_UV_ICLR : VDDC Undervoltage Interrupt Status (ADC2 channel 8)
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

0b0 : No_Undervoltage_Interrupt

occurred

0b1 : Undervoltage_Interrupt

occurred

End of enumeration elements list.

VBAT_OV_ICLR : VBAT Overvoltage Interrupt Status (ADC2 channel 0)
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

0b0 : No_Overvoltage_Interrupt

occurred

0b1 : Overvoltage_Interrupt

occurred

End of enumeration elements list.

VS_OV_ICLR : VS Overvoltage Interrupt Status (ADC2 channel 1)
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

0b0 : No_Overvoltage_Interrupt

occurred

0b1 : Overvoltage_Interrupt

occurred

End of enumeration elements list.

VDD5V_OV_ICLR : VDDP Overvoltage Interrupt Status (ADC2 channel 5)
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

0b0 : No_Overvoltage_Interrupt

occurred

0b1 : Overvoltage_Interrupt

occurred

End of enumeration elements list.

VDD1V5_OV_ICLR : VDDC Overvoltage Interrupt Status (ADC2 channel 8)
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

0b0 : No_Overvoltage_Interrupt

occurred

0b1 : Overvoltage_Interrupt

occurred

End of enumeration elements list.

VBAT_UV_SCLR : VBAT Undervoltage Status
bits : 16 - 15 (0 bit)
access : write-only

Enumeration:

0b0 : No_Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VS_UV_SCLR : VS Undervoltage Status
bits : 17 - 16 (0 bit)
access : write-only

Enumeration:

0b0 : No_Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VDD5V_UV_SCLR : VDDP Undervoltage Status
bits : 18 - 17 (0 bit)
access : write-only

Enumeration:

0b0 : No_Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VDD1V5_UV_SCLR : VDDC Undervoltage Status
bits : 19 - 18 (0 bit)
access : write-only

Enumeration:

0b0 : No_Undervoltage

occurred

0b1 : Undervoltage

occurred

End of enumeration elements list.

VBAT_OV_SCLR : VBAT Overvoltage Status
bits : 20 - 19 (0 bit)
access : write-only

Enumeration:

0b0 : No_Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.

VS_OV_SCLR : VS Overvoltage Interrupt Status
bits : 21 - 20 (0 bit)
access : write-only

Enumeration:

0b0 : No_Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.

VDD5V_OV_SCLR : VDDP Overvoltage Status
bits : 22 - 21 (0 bit)
access : write-only

Enumeration:

0b0 : No_Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.

VDD1V5_OV_SCLR : VDDC Overvoltage Status
bits : 23 - 22 (0 bit)
access : write-only

Enumeration:

0b0 : No_Overvoltage

occurred

0b1 : Overvoltage

occurred

End of enumeration elements list.


SYS_IRQ_CTRL

System Interrupt Control
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SYS_IRQ_CTRL SYS_IRQ_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIN_OC_IE LIN_OT_IE LIN_TMOUT_IE PMU_OTWARN_IE PMU_OT_IE SYS_OTWARN_IE SYS_OT_IE REFBG_LOTHWARN_IE REFBG_UPTHWARN_IE VREF5V_LOWTH_IE VREF5V_UPTH_IE VREF5V_OVL_IE ADC2_ESM_IE ADC3_EOC_IE ADC4_EOC_IE

LIN_OC_IE : LIN Overcurrent Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

LIN_OT_IE : LIN Overtemperature Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

LIN_TMOUT_IE : LIN TXD timeout Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

PMU_OTWARN_IE : PMU Regulator Overtemperature Warning Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

PMU_OT_IE : PMU Regulator Overtemperature Shutdown Interrupt Enable (leads to shutdown of System)
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

SYS_OTWARN_IE : System Overtemperature Warning Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

SYS_OT_IE : System Overtemperature Shutdown Interrupt Enable (leads to shutdown of System)
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

REFBG_LOTHWARN_IE : Reference Voltage Undervoltage Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

REFBG_UPTHWARN_IE : Reference Voltage Overvoltage Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VREF5V_LOWTH_IE : VREF5V ADC1 Reference Undervoltage (ADC2, Channel 4) Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VREF5V_UPTH_IE : VREF5V ADC1 Reference Overvoltage (ADC2, Channel 4) Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VREF5V_OVL_IE : VREF5V Overload Interrupt Enable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

ADC2_ESM_IE : ADC2 Exceptional Sequence Measurement Interrupt Enable
bits : 15 - 14 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

ADC3_EOC_IE : ADC3 EOC Interrupt Enable
bits : 22 - 21 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

ADC4_EOC_IE : ADC4 EOC Interrupt Enable
bits : 23 - 22 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.


PCU_CTRL_STS

Power Control Unit Control Status
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PCU_CTRL_STS PCU_CTRL_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKWDT_SD_DIS FAIL_PS_DIS LIN_VS_UV_SD_DIS SYS_VSD_OV_SLM_DIS SYS_OT_PS_DIS CLKLOSS_SD_DIS CLKWDT_RES_SD_DIS

CLKWDT_SD_DIS : Power Modules Clock Watchdog Shutdown Disable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : Shutdown_Enable

Power Devices will be switched off when Clock Watchdog occurs

0b1 : Shutdown_Disable

Power Devices will not be shutdown when Clock Watchog occurs

End of enumeration elements list.

FAIL_PS_DIS : Disable LIN, BDRV and CP because of Overtemperature
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : Switch_off_Enabled

LIN, BDRV and CP will be turned off when Overtemperature occurs

0b1 : Switch_off_Disabled

LIN, BDRV and CP will be kept on when Overtemperature occurs

End of enumeration elements list.

LIN_VS_UV_SD_DIS : LIN Module VS Undervoltage Transmitter Shutdown
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Automatic Shutdown for Power modules in case of VS Undervoltage enabled

0b1 : Disable

Automatic Shutdown for Power modules in case of VS Undervoltage disabled

End of enumeration elements list.

SYS_VSD_OV_SLM_DIS : VSD Overvoltage Shutdown for Peripherals Disable
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Automatic Shutdown for Power modules in case of VSD Overvoltage enabled

0b1 : Disable

Automatic Shutdown for Power modules in case of VSD Overvoltage disabled

End of enumeration elements list.

SYS_OT_PS_DIS : System Overtemperature Power Switches Shutdown Disable
bits : 24 - 23 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Automatic Shutdown Signal for Power Switches in case of system overtemperature preenable

0b1 : Disable

Automatic Shutdown Signal for Power Switches in case of system overtemperature enable

End of enumeration elements list.

CLKLOSS_SD_DIS : Power Switches Loss of Clock Shutdown Disable (AMCLK3)
bits : 25 - 24 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Automatic Shutdown Signal for Power Switches in case of loss of clock

0b1 : Disable

Automatic Shutdown Signal for Power Switches in case of loss of clock

End of enumeration elements list.

CLKWDT_RES_SD_DIS : Clock Watchdog Reset Disable
bits : 26 - 25 (0 bit)
access : read-write

Enumeration:

0b0 : Enable

Clock Watchdog Reset Enable

0b1 : Disable

Clock Watchdog Reset Disable

End of enumeration elements list.


WDT1_TRIG

WDT1 Watchdog Control
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

WDT1_TRIG WDT1_TRIG read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDP_SEL SOWCONF

WDP_SEL : Watchdog Period Selection and trigger
bits : 0 - 4 (5 bit)
access : read-write

Enumeration:

0x00 : SOW_TRIG

trigger short open window

0x01 : WP_1

Watchdog period 16 ms

0x02 : WP_2

Watchdog period 32 ms

0x03 : WP_3

Watchdog period 48 ms

0x3F : WP_63

Watchdog period 1008 ms

End of enumeration elements list.

SOWCONF : Short Open Window Configuration
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0b00 : DIS

Short Open Windows disabled

0b01 : SOW1

one successive Short Open Window allowed

0b10 : SOW2

two successive Short Open Windows allowed

0b11 : SOW3

three successive Short Open Windows allowed

End of enumeration elements list.


AMCLK_CTRL

Analog Module Clock Control
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMCLK_CTRL AMCLK_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKWDT_PD_N

CLKWDT_PD_N : Clock Watchdog Powerdown
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

Clock Watchdog disabled

0b1 : ENABLE

Clock Watchdog enabaled

End of enumeration elements list.


BDRV_ISCLR

Bridge Driver Interrrupt Status Clear
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDRV_ISCLR BDRV_ISCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS1_DS_ICLR LS2_DS_ICLR HS1_DS_ICLR HS2_DS_ICLR LS1_OC_ICLR LS2_OC_ICLR HS1_OC_ICLR HS2_OC_ICLR VCP_LOWTH2_ICLR VCP_LOWTH1_ICLR VCP_UPTH_ICLR VSD_LOWTH_ICLR VSD_UPTH_ICLR VCP_LOWTH2_SCLR VCP_LOWTH1_SCLR VCP_UPTH_SCLR VSD_LOWTH_SCLR VSD_UPTH_SCLR

LS1_DS_ICLR : Bridge Driver Low Side 1 Pre-Driver short Interrupt Status
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

LS2_DS_ICLR : Bridge Driver Low Side 2 Pre-Driver short Interrupt Status
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

HS1_DS_ICLR : Bridge Driver High Side 1 Pre-Driver short Interrupt Status
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

HS2_DS_ICLR : Bridge Driver High Side 2 Pre-Driver short Interrupt Status
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

LS1_OC_ICLR : External Low Side 1 FET Over-current Status
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set.

0b1 : ACTIVE

at least one interrupt status set.

End of enumeration elements list.

LS2_OC_ICLR : External Low Side 2 FET Over-current Status
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set.

0b1 : ACTIVE

at least one interrupt status set.

End of enumeration elements list.

HS1_OC_ICLR : External High 1 FET Over-current Status
bits : 12 - 11 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set.

0b1 : ACTIVE

at least one interrupt status set.

End of enumeration elements list.

HS2_OC_ICLR : External High Side 2 FET Over-current Status
bits : 13 - 12 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set.

0b1 : ACTIVE

at least one interrupt status set.

End of enumeration elements list.

VCP_LOWTH2_ICLR : Warning for VCP Lower Threshold 2 Measurement (VCP_LOW Signal from CP) Interrupt Status
bits : 16 - 15 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

VCP_LOWTH1_ICLR : Warning for VCP Lower Threshold 1 Measurement (ADC2 channel 3) Interrupt Status
bits : 17 - 16 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

VCP_UPTH_ICLR : Warning for VCP Upper Threshold Measurement (ADC2 channel 3) Interrupt Status
bits : 18 - 17 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

VSD_LOWTH_ICLR : Warning for VSD Lower Threshold Measurement (ADC2 channel 2) Interrupt Status
bits : 19 - 18 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

VSD_UPTH_ICLR : Warning for VSD Upper Threshold Measurement (ADC2 channel 2) Interrupt Status
bits : 20 - 19 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

VCP_LOWTH2_SCLR : Warning for VCP Lower Threshold 2 Measurement (VCP_LOW Signal from CP) Status
bits : 24 - 23 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no undervoltage status set

0b1 : ACTIVE

undervoltage status set

End of enumeration elements list.

VCP_LOWTH1_SCLR : Warning for VCP Lower Threshold 1 Measurement (ADC2 channel 3) Status
bits : 25 - 24 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no undervoltage status set

0b1 : ACTIVE

undervoltage status set

End of enumeration elements list.

VCP_UPTH_SCLR : Warning for VCP Upper Threshold Measurement (ADC2 channel 3) Status
bits : 26 - 25 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no overvoltage status set

0b1 : ACTIVE

overvoltage status set

End of enumeration elements list.

VSD_LOWTH_SCLR : Warning for VSD Lower Threshold Measurement (ADC2 channel 2) Status
bits : 27 - 26 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no undervoltage status set

0b1 : ACTIVE

undervoltage status set

End of enumeration elements list.

VSD_UPTH_SCLR : Warning for VSD Upper Threshold Measurement (ADC2 channel 2) Status
bits : 28 - 27 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

no overvoltage status set

0b1 : ACTIVE

overvoltage status set

End of enumeration elements list.


BDRV_IS

Bridge Driver Interrrupt Status
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDRV_IS BDRV_IS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS1_DS_IS LS2_DS_IS HS1_DS_IS HS2_DS_IS LS1_OC_IS LS2_OC_IS HS1_OC_IS HS2_OC_IS VCP_LOWTH2_IS VCP_LOWTH1_IS VCP_UPTH_IS VSD_LOWTH_IS VSD_UPTH_IS VCP_LOWTH2_STS VCP_LOWTH1_STS VCP_UPTH_STS VSD_LOWTH_STS VSD_UPTH_STS

LS1_DS_IS : Bridge Driver Low Side 1 Pre-Driver short Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

LS2_DS_IS : Bridge Driver Low Side 2 Pre-Driver short Interrupt Status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

HS1_DS_IS : Bridge Driver High Side 1 Pre-Driver short Interrupt Status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

HS2_DS_IS : Bridge Driver High Side 2 Pre-Driver short Interrupt Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

LS1_OC_IS : External Low Side 1 FET Over-current Status
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set.

0b1 : ACTIVE

at least one interrupt status set.

End of enumeration elements list.

LS2_OC_IS : External Low Side 2 FET Over-current Status
bits : 11 - 10 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set.

0b1 : ACTIVE

at least one interrupt status set.

End of enumeration elements list.

HS1_OC_IS : External High 1 FET Over-current Status
bits : 12 - 11 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set.

0b1 : ACTIVE

at least one interrupt status set.

End of enumeration elements list.

HS2_OC_IS : External High Side 2 FET Over-current Status
bits : 13 - 12 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set.

0b1 : ACTIVE

at least one interrupt status set.

End of enumeration elements list.

VCP_LOWTH2_IS : Warning for VCP Lower Threshold 2 Measurement (VCP_LOW Signal from CP) Interrupt Status
bits : 16 - 15 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

VCP_LOWTH1_IS : Warning for VCP Lower Threshold 1 Measurement (ADC2 channel 3) Interrupt Status
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

VCP_UPTH_IS : Warning for VCP Upper Threshold Measurement (ADC2 channel 3) Interrupt Status
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

VSD_LOWTH_IS : Warning for VSD Lower Threshold Measurement (ADC2 channel 2) Interrupt Status
bits : 19 - 18 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

VSD_UPTH_IS : Warning for VSD Upper Threshold Measurement (ADC2 channel 2) Interrupt Status
bits : 20 - 19 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no interrupt status set

0b1 : ACTIVE

interrupt status set

End of enumeration elements list.

VCP_LOWTH2_STS : Warning for VCP Lower Threshold 2 Measurement (VCP_LOW Signal from CP) Status
bits : 24 - 23 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no undervoltage status set

0b1 : ACTIVE

undervoltage status set

End of enumeration elements list.

VCP_LOWTH1_STS : Warning for VCP Lower Threshold 1 Measurement (ADC2 channel 3) Status
bits : 25 - 24 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no undervoltage status set

0b1 : ACTIVE

undervoltage status set

End of enumeration elements list.

VCP_UPTH_STS : Warning for VCP Upper Threshold Measurement (ADC2 channel 3) Status
bits : 26 - 25 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no overvoltage status set

0b1 : ACTIVE

overvoltage status set

End of enumeration elements list.

VSD_LOWTH_STS : Warning for VSD Lower Threshold Measurement (ADC2 channel 2) Status
bits : 27 - 26 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no undervoltage status set

0b1 : ACTIVE

undervoltage status set

End of enumeration elements list.

VSD_UPTH_STS : Warning for VSD Upper Threshold Measurement (ADC2 channel 2) Status
bits : 28 - 27 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

no overvoltage status set

0b1 : ACTIVE

overvoltage status set

End of enumeration elements list.


BDRV_IRQ_CTRL

Bridge Driver Interrupt Control
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BDRV_IRQ_CTRL BDRV_IRQ_CTRL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LS1_DS_IE LS2_DS_IE HS1_DS_IE HS2_DS_IE LS1_OC_IE LS2_OC_IE HS1_OC_IE HS2_OC_IE VCP_LOWTH2_IE VCP_LOWTH1_IE VCP_UPTH_IE VSD_LOWTH_IE VSD_UPTH_IE

LS1_DS_IE : Bridge Driver Low Side 1 Pre-Driver Short Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

LS2_DS_IE : Bridge Driver Low Side 2 Pre-Driver Short Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

HS1_DS_IE : Bridge Driver High Side 1 Pre-Driver Short Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

HS2_DS_IE : Bridge Driver High Side 2 Pre-Driver Short Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

LS1_OC_IE : External Low Side 1 FET Over-current Interrupt Enable
bits : 10 - 9 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

LS2_OC_IE : External Low Side 2 FET Over-current Interrupt Enable
bits : 11 - 10 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

HS1_OC_IE : External High Side 1 FET Over-current Interrupt Enable
bits : 12 - 11 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

HS2_OC_IE : External High Side 2 FET Over-current Interrupt Enable
bits : 13 - 12 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VCP_LOWTH2_IE : VCP Measurement Lower Threshold 2 Interrupt Enable
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VCP_LOWTH1_IE : VCP Measurement Lower Threshold 1 Interrupt Enable
bits : 17 - 16 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VCP_UPTH_IE : VCP Measurement Upper Threshold Interrupt Enable
bits : 18 - 17 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VSD_LOWTH_IE : VSD Measurement Lower Threshold Interrupt Enable
bits : 19 - 18 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.

VSD_UPTH_IE : VSD Measurement Upper Threshold Interrupt Enable
bits : 20 - 19 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Interrupt is disabled

0b1 : value2

Interrupt is enabled

End of enumeration elements list.


STCALIB

System Tick Calibration Register
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STCALIB STCALIB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STCALIB

STCALIB : System Tick Calibration
bits : 0 - 24 (25 bit)
access : read-write


BFSTS

Bus Fault Status
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BFSTS BFSTS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBFSTS SBFSTS

DBFSTS : Data Bus Fault Status Valid Flag
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b1 : Valid

Adress is valid

0b0 : not_valid

Adress is not valid

End of enumeration elements list.

SBFSTS : System Bus Fault Status Valid Flag
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b1 : Valid

Adress is valid

0b0 : not_valid

Adress is not valid

End of enumeration elements list.


DBFA

Data Bus Fault Address Register
address_offset : 0x84 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DBFA DBFA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBFA

DBFA : Data Bus Fault Address Register
bits : 0 - 30 (31 bit)
access : read-only


SBFA

System Bus Fault Address Register
address_offset : 0x88 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SBFA SBFA read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SBFA

SBFA : System Bus Fault Address Register
bits : 0 - 30 (31 bit)
access : read-only


BFSTS_CLR

Bus Fault Status Clear Register
address_offset : 0x8C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BFSTS_CLR BFSTS_CLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DBFSTSCLR SBFSTSCLR

DBFSTSCLR : Data Bus Fault Status Clear Flag
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b1 : Cleared

Adress is cleared

0b0 : not_cleared

Adress is not cleared

End of enumeration elements list.

SBFSTSCLR : System Bus Fault Status Clear Flag
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b1 : Cleared

Valid Adress is cleared

0b0 : not_cleared

Valid Adress is not cleared

End of enumeration elements list.


AMCLK_TH_HYS

Analog Module Clock Limit Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

AMCLK_TH_HYS AMCLK_TH_HYS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AMCLK1_UP_TH AMCLK1_UP_HYS AMCLK1_LOW_TH AMCLK1_LOW_HYS AMCLK2_UP_TH AMCLK2_UP_HYS AMCLK2_LOW_TH AMCLK2_LOW_HYS

AMCLK1_UP_TH : Analog Module Clock 1 (MI_CLK) Upper Limit Threshold
bits : 0 - 4 (5 bit)
access : read-write

AMCLK1_UP_HYS : Analog Module Clock 1 (MI_CLK) Upper Hysteresis
bits : 6 - 6 (1 bit)
access : read-write

AMCLK1_LOW_TH : Analog Module Clock 1 (MI_CLK) Lower Limit Threshold
bits : 8 - 12 (5 bit)
access : read-write

AMCLK1_LOW_HYS : Analog Module Clock 1 (MI_CLK) Lower Hysteresis
bits : 14 - 14 (1 bit)
access : read-write

AMCLK2_UP_TH : Analog Module Clock 2 (TFILT_CLK) Upper Limit Threshold
bits : 16 - 20 (5 bit)
access : read-write

AMCLK2_UP_HYS : Analog Module Clock 2 (TFILT_CLK) Upper Hysteresis
bits : 22 - 22 (1 bit)
access : read-write

AMCLK2_LOW_TH : Analog Module Clock 2 (TFILT_CLK) Lower Limit Threshold
bits : 24 - 28 (5 bit)
access : read-write

AMCLK2_LOW_HYS : Analog Module Clock 2 (TFILT_CLK) Lower Hysteresis
bits : 30 - 30 (1 bit)
access : read-write



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