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SSC2

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

PISEL

BR

ISRCLR

CON

TB

RB


PISEL

Port Input Select Register, RESET_TYPE_3
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

PISEL PISEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MIS_0 SIS CIS MIS_1

MIS_0 : Master Mode Receiver Input Select: 0b0=see (SSC1)., 0b1=see (SSC1)., 0b0=Receiver input (Port A: P1.2) is selected (SSC2)., 0b1=Receiver input (Port B: P2.5) is selected (SSC2).,
bits : 0 - -1 (0 bit)
access : read-write

SIS : Slave Mode Receiver Input Select: 0b0=Receiver input (Port A: P0.2) is selected (SSC1)., 0b1=Receiver input (Port B: P0.2) is selected (SSC1)., 0b0=Receiver input (Port A: P1.1) is selected (SSC2)., 0b1=Receiver input (Port B: P1.1) is selected (SSC2).,
bits : 1 - 0 (0 bit)
access : read-write

CIS : Slave Mode Clock Input Select: 0b0=Clock input (Port A: P0.3) is selected (SSC1)., 0b1=Clock input (Port B: P0.3) is selected (SSC1)., 0b0=Clock input (Port A: P1.0) is selected (SSC2)., 0b1=Clock input (Port B: P1.0) is selected (SSC2).,
bits : 2 - 1 (0 bit)
access : read-write

MIS_1 : Master Mode Receiver Input Select: 0b0=see (SSC1)., 0b1=see (SSC1)., 0b0=n/a (SSC2)., 0b1=n/a (SSC2).,
bits : 3 - 2 (0 bit)
access : read-write


BR

Baud Rate Timer Reload Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

BR BR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BR_VALUE

BR_VALUE : Baud Rate Timer/Reload Register Value
bits : 0 - 14 (15 bit)
access : read-write


ISRCLR

Interrupt Status Register Clear
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ISRCLR ISRCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TECLR RECLR PECLR BECLR

TECLR : Transmit Error Flag Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

0b0 : value1

No error clear.

0b1 : value2

Error clear.

End of enumeration elements list.

RECLR : Receive Error Flag Clear
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

0b0 : value1

No error clear.

0b1 : value2

Error clear.

End of enumeration elements list.

PECLR : Phase Error Flag Clear
bits : 10 - 9 (0 bit)
access : write-only

Enumeration:

0b0 : value1

No error clear.

0b1 : value2

Error clear.

End of enumeration elements list.

BECLR : Baud Rate Error Flag Clear
bits : 11 - 10 (0 bit)
access : write-only

Enumeration:

0b0 : value1

No error clear.

0b1 : value2

Error clear.

End of enumeration elements list.


CON

Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CON CON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BC TE RE PE BE BSY MS EN

BC : Bit Count Field
bits : 0 - 2 (3 bit)
access : read-only

TE : Transmit Error Flag
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

0b0 : value1

No error.

0b1 : value2

Transfer starts with the slave's transmit buffer not being updated.

End of enumeration elements list.

RE : Receive Error Flag
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

0b0 : value1

No error.

0b1 : value2

Reception completed before the receive buffer was read.

End of enumeration elements list.

PE : Phase Error Flag
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

0b0 : value1

No error.

0b1 : value2

Received data changes around sampling clock edge.

End of enumeration elements list.

BE : Baud Rate Error Flag
bits : 11 - 10 (0 bit)
access : read-only

Enumeration:

0b0 : value1

No error.

0b1 : value2

More than factor 2 or 0.5 between slave's actual and expected baud rate.

End of enumeration elements list.

BSY : Busy Flag
bits : 12 - 11 (0 bit)
access : read-only

MS : Master Select Bit
bits : 14 - 13 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Slave Mode. Operate on shift clock received via SCLK.

0b1 : value2

Master Mode. Generate shift clock and output it via SCLK.

End of enumeration elements list.

EN : Enable Bit = 1
bits : 15 - 14 (0 bit)
access : read-write


TB

Transmitter Buffer Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

TB TB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TB_VALUE

TB_VALUE : Transmit Data Register Value
bits : 0 - 14 (15 bit)
access : read-write


RB

Receiver Buffer Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RB RB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RB_VALUE

RB_VALUE : Receive Data Register Value
bits : 0 - 14 (15 bit)
access : read-only



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