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ADC1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected

Registers

CTRL_STS

SQ1_4

SQ5_8

DWSEL

STC_0_3

STC_4_7

GLOBCTR

RES_OUT_EIM

SQ_FB

RES_OUT7

RES_OUT6

RES_OUT5

RES_OUT4

RES_OUT3

RES_OUT2

RES_OUT1

RES_OUT0

GLOBSTR

IS

IE

CHx_EIM

ICLR

CHx_ESM


CTRL_STS

ADC1 Control and Status Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CTRL_STS CTRL_STS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD_N SOC EOC IN_MUX_SEL

PD_N : ADC1 Power Down Signal
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : POWER_DOWN

ADC1 is powered down

0b1 : ACTIVE

ADC1 is switched on

End of enumeration elements list.

SOC : ADC1 Start of Conversion (software mode)
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : Disable

no conversion is started

0b1 : Enable

conversion is started

End of enumeration elements list.

EOC : ADC1 End of Conversion (software mode)
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

0b0 : Pending

conversion still running

0b1 : Finished

conversion has finished

End of enumeration elements list.

IN_MUX_SEL : Channel for software mode
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0b000 : CH0_EN

Channel 0 enable

0b001 : CH1_EN

Channel 1 enable

0b010 : CH2_EN

Channel 2 enable

0b011 : CH3_EN

Channel 3 enable

0b100 : CH4_EN

Channel 4 enable

0b101 : CH5_EN

Channel 5 enable

0b110 : CH6_EN

Channel 6 enable

0b111 : CH7_EN

Channel 7 enable

End of enumeration elements list.


SQ1_4

Measurement Channel Enable Bits for Cycle 1 - 4
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQ1_4 SQ1_4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ1 SQ2 SQ3 SQ4

SQ1 : Sequence 1 channel enable
bits : 0 - 6 (7 bit)
access : read-write

SQ2 : Sequence 2 channel enable
bits : 8 - 14 (7 bit)
access : read-write

SQ3 : Sequence 3 channel enable
bits : 16 - 22 (7 bit)
access : read-write

SQ4 : Sequence 4 channel enable
bits : 24 - 30 (7 bit)
access : read-write


SQ5_8

Measurement Channel Enable Bits for Cycle 5 - 8
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQ5_8 SQ5_8 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ5 SQ6 SQ7 SQ8

SQ5 : Sequence 5 channel enable
bits : 0 - 6 (7 bit)
access : read-write

SQ6 : Sequence 6 channel enable
bits : 8 - 14 (7 bit)
access : read-write

SQ7 : Sequence 7 channel enable
bits : 16 - 22 (7 bit)
access : read-write

SQ8 : Sequence 8 channel enable
bits : 24 - 30 (7 bit)
access : read-write


DWSEL

Measurement Channel Data Width Selection
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

DWSEL DWSEL read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7

ch0 : Data Width channel 0
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : 10BIT

The result is 10 bits wide (bits 11 .. 2)

0b1 : 8BIT

The result is 8 bits wide (bits 9 .. 4)

End of enumeration elements list.

ch1 : Data Width channel 1
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : 10BIT

The result is 10 bits wide (bits 11 .. 2)

0b1 : 8BIT

The result is 8 bits wide (bits 9 .. 4)

End of enumeration elements list.

ch2 : Data Width channel 2
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : 10BIT

The result is 10 bits wide (bits 11 .. 2)

0b1 : 8BIT

The result is 8 bits wide (bits 9 .. 4)

End of enumeration elements list.

ch3 : Data Width channel 3
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : 10BIT

The result is 10 bits wide (bits 11 .. 2)

0b1 : 8BIT

The result is 8 bits wide (bits 9 .. 4)

End of enumeration elements list.

ch4 : Data Width channel 4
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : 10BIT

The result is 10 bits wide (bits 11 .. 2)

0b1 : 8BIT

The result is 8 bits wide (bits 9 .. 4)

End of enumeration elements list.

ch5 : Data Width channel 5
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : 10BIT

The result is 10 bits wide (bits 11 .. 2)

0b1 : 8BIT

The result is 8 bits wide (bits 9 .. 4)

End of enumeration elements list.

ch6 : Data Width channel 6
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : 10BIT

The result is 10 bits wide (bits 11 .. 2)

0b1 : 8BIT

The result is 8 bits wide (bits 9 .. 4)

End of enumeration elements list.

ch7 : Data Width channel 7
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : 10BIT

The result is 10 bits wide (bits 11 .. 2)

0b1 : 8BIT

The result is 8 bits wide (bits 9 .. 4)

End of enumeration elements list.


STC_0_3

Measurement Channel Sample Time Control 0 - 3
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STC_0_3 STC_0_3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch0 ch1 ch2 ch3

ch0 : Sample Time Control for Channel 0
bits : 0 - 6 (7 bit)
access : read-write

ch1 : Sample Time Control for Channel 1
bits : 8 - 14 (7 bit)
access : read-write

ch2 : Sample Time Control for Channel 2
bits : 16 - 22 (7 bit)
access : read-write

ch3 : Sample Time Control for Channel 3
bits : 24 - 30 (7 bit)
access : read-write


STC_4_7

Measurement Channel Sample Time Control 4 - 7
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

STC_4_7 STC_4_7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ch4 ch5 ch6 ch7

ch4 : Sample Time Control for Channel 4
bits : 0 - 6 (7 bit)
access : read-write

ch5 : Sample Time Control for Channel 5
bits : 8 - 14 (7 bit)
access : read-write

ch6 : Sample Time Control for Channel 6
bits : 16 - 22 (7 bit)
access : read-write

ch7 : Sample Time Control for Channel 7
bits : 24 - 30 (7 bit)
access : read-write


GLOBCTR

Global Control Register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GLOBCTR GLOBCTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DIVA ANON

DIVA : Divide Factor for the Analog internal clock: 0x00=Fadci = Fadc, 0x01=Fadci = Fadc/2, 0x02=Fadci = Fadc/3, 0x02=..., 0x3F=Fadci = Fadc/64,
bits : 0 - 4 (5 bit)
access : read-write

ANON : Analog Part Switched On
bits : 8 - 8 (1 bit)
access : read-write

Enumeration:

0b00 : OFF

ADC1 switched off

0b01 : S_STANDBY

Slow standby mode

0b10 : F_STANDBY

Fast standby mode

0b11 : NORMAL

Normal Operation

End of enumeration elements list.


RES_OUT_EIM

ADC1 Output Channel EIM
address_offset : 0x40 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES_OUT_EIM RES_OUT_EIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_CH_EIM WFR8 VF8 OF8

OUT_CH_EIM : ADC1 output result value EIM
bits : 0 - 10 (11 bit)
access : read-only

WFR8 : Wait for Read Mode
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

overwrite mode

0b1 : ENABLE

wait for read mode enabled

End of enumeration elements list.

VF8 : Valid Flag
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0b0 : NOT_VALID

No new valid data available

0b1 : VALID

Result register contains valid data and has not yet been read

End of enumeration elements list.

OF8 : Overrun Flag
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0b0 : NO_OVERRUN

Result register not overwritten

0b1 : OVERRUN

Result register overwritten

End of enumeration elements list.


SQ_FB

Sequencer Feedback Register
address_offset : 0x50 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SQ_FB SQ_FB read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SQ_RUN EIM_ACTIVE ESM_ACTIVE SQx CHx

SQ_RUN : ADC1 Sequencer RUN
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : SQ_Stopped

Postprocessing Sequencer in stopped / Software mode

0b1 : SQ_Running

Postprocessing Sequencer is running

End of enumeration elements list.

EIM_ACTIVE : ADC1 EIM active
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

0b0 : not_active

EIM not active

0b1 : active

EIM active

End of enumeration elements list.

ESM_ACTIVE : ADC1 ESM active
bits : 10 - 9 (0 bit)
access : read-only

Enumeration:

0b0 : not_active

ESM not active

0b1 : active

ESM active

End of enumeration elements list.

SQx : Current Active Sequence in Sequencer Mode
bits : 11 - 12 (2 bit)
access : read-only

Enumeration:

0b000 : SQ0

Sequence 0

0b001 : SQ1

Sequence 1

0b010 : SQ2

Sequence 2

0b011 : SQ3

Sequence 3

0b100 : SQ4

Sequence 4

0b101 : SQ5

Sequence 5

0b110 : SQ6

Sequence 6

0b111 : SQ7

Sequence 7

End of enumeration elements list.

CHx : Current Channel
bits : 16 - 17 (2 bit)
access : read-only

Enumeration:

0b000 : CH0

Channel 0

0b001 : CH1

Channel 1

0b010 : CH2

Channel 2

0b011 : CH3

Channel 3

0b100 : CH4

Channel 4

0b101 : CH5

Channel 5

0b110 : CH6

Channel 6

0b111 : CH7

Channel 7

End of enumeration elements list.


RES_OUT7

ADC1 Output Channel 7
address_offset : 0x54 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES_OUT7 RES_OUT7 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_CH7 WFR7 VF7 OF7

OUT_CH7 : ADC1 output result value channel 7
bits : 0 - 10 (11 bit)
access : read-only

WFR7 : Wait for Read Mode
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

overwrite mode

0b1 : ENABLE

wait for read mode enabled

End of enumeration elements list.

VF7 : Valid Flag
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0b0 : NOT_VALID

No new valid data available

0b1 : VALID

Result register contains valid data and has not yet been read

End of enumeration elements list.

OF7 : Overrun Flag
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0b0 : NO_OVERRUN

Result register not overwritten

0b1 : OVERRUN

Result register overwritten

End of enumeration elements list.


RES_OUT6

ADC1 Output Channel 6
address_offset : 0x58 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES_OUT6 RES_OUT6 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_CH6 WFR6 VF6 OF6

OUT_CH6 : ADC1 output result value channel 6
bits : 0 - 10 (11 bit)
access : read-only

WFR6 : Wait for Read Mode
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

overwrite mode

0b1 : ENABLE

wait for read mode enabled

End of enumeration elements list.

VF6 : Valid Flag
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0b0 : NOT_VALID

No new valid data available

0b1 : VALID

Result register contains valid data and has not yet been read

End of enumeration elements list.

OF6 : Overrun Flag
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0b0 : NO_OVERRUN

Result register not overwritten

0b1 : OVERRUN

Result register overwritten

End of enumeration elements list.


RES_OUT5

ADC1 Output Channel 5
address_offset : 0x5C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES_OUT5 RES_OUT5 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_CH5 WFR5 VF5 OF5

OUT_CH5 : ADC1 output result value channel 5
bits : 0 - 10 (11 bit)
access : read-only

WFR5 : Wait for Read Mode
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

overwrite mode

0b1 : ENABLE

wait for read mode enabled

End of enumeration elements list.

VF5 : Valid Flag
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0b0 : NOT_VALID

No new valid data available

0b1 : VALID

Result register contains valid data and has not yet been read

End of enumeration elements list.

OF5 : Overrun Flag
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0b0 : NO_OVERRUN

Result register not overwritten

0b1 : OVERRUN

Result register overwritten

End of enumeration elements list.


RES_OUT4

ADC1 Output Channel 4
address_offset : 0x60 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES_OUT4 RES_OUT4 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_CH4 WFR4 VF4 OF4

OUT_CH4 : ADC1 output result value channel 4
bits : 0 - 10 (11 bit)
access : read-only

WFR4 : Wait for Read Mode
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

overwrite mode

0b1 : ENABLE

wait for read mode enabled

End of enumeration elements list.

VF4 : Valid Flag
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0b0 : NOT_VALID

No new valid data available

0b1 : VALID

Result register contains valid data and has not yet been read

End of enumeration elements list.

OF4 : Overrun Flag
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0b0 : NO_OVERRUN

Result register not overwritten

0b1 : OVERRUN

Result register overwritten

End of enumeration elements list.


RES_OUT3

ADC1 Output Channel 3
address_offset : 0x64 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES_OUT3 RES_OUT3 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_CH3 WFR3 VF3 OF3

OUT_CH3 : ADC1 output result value channel 3
bits : 0 - 10 (11 bit)
access : read-only

WFR3 : Wait for Read Mode
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

overwrite mode

0b1 : ENABLE

wait for read mode enabled

End of enumeration elements list.

VF3 : Valid Flag
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0b0 : NOT_VALID

No new valid data available

0b1 : VALID

Result register contains valid data and has not yet been read

End of enumeration elements list.

OF3 : Overrun Flag
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0b0 : NO_OVERRUN

Result register not overwritten

0b1 : OVERRUN

Result register overwritten

End of enumeration elements list.


RES_OUT2

ADC1 Output Channel 2
address_offset : 0x68 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES_OUT2 RES_OUT2 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_CH2 WFR2 VF2 OF2

OUT_CH2 : ADC1 output result value channel 2
bits : 0 - 10 (11 bit)
access : read-only

WFR2 : Wait for Read Mode
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

overwrite mode

0b1 : ENABLE

wait for read mode enabled

End of enumeration elements list.

VF2 : Valid Flag
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0b0 : NOT_VALID

No new valid data available

0b1 : VALID

Result register contains valid data and has not yet been read

End of enumeration elements list.

OF2 : Overrun Flag
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0b0 : NO_OVERRUN

Result register not overwritten

0b1 : OVERRUN

Result register overwritten

End of enumeration elements list.


RES_OUT1

ADC1 Output Channel 1
address_offset : 0x6C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES_OUT1 RES_OUT1 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_CH1 WFR1 VF1 OF1

OUT_CH1 : ADC1 output result value channel 1
bits : 0 - 10 (11 bit)
access : read-only

WFR1 : Wait for Read Mode
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

overwrite mode

0b1 : ENABLE

wait for read mode enabled

End of enumeration elements list.

VF1 : Valid Flag
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0b0 : NOT_VALID

No new valid data available

0b1 : VALID

Result register contains valid data and has not yet been read

End of enumeration elements list.

OF1 : Overrun Flag
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0b0 : NO_OVERRUN

Result register not overwritten

0b1 : OVERRUN

Result register overwritten

End of enumeration elements list.


RES_OUT0

ADC1 Output Channel 0
address_offset : 0x70 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

RES_OUT0 RES_OUT0 read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OUT_CH0 WFR0 VF0 OF0

OUT_CH0 : ADC1 output reset value channel 0
bits : 0 - 10 (11 bit)
access : read-only

WFR0 : Wait for Read Mode
bits : 16 - 15 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLE

overwrite mode

0b1 : ENABLE

wait for read mode enabled

End of enumeration elements list.

VF0 : Valid Flag
bits : 17 - 16 (0 bit)
access : read-only

Enumeration:

0b0 : NOT_VALID

No new valid data available

0b1 : VALID

Result register contains valid data and has not yet been read

End of enumeration elements list.

OF0 : Overrun Flag
bits : 18 - 17 (0 bit)
access : read-only

Enumeration:

0b0 : NO_OVERRUN

Result register not overwritten

0b1 : OVERRUN

Result register overwritten

End of enumeration elements list.


GLOBSTR

Global Status Register
address_offset : 0x74 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

GLOBSTR GLOBSTR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUSY SAMPLE CHNR ANON_ST

BUSY : Analog Part Busy
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : IDLE

ADC1 idle

0b1 : ACTIVE

ADC1 Conversion is currently running

End of enumeration elements list.

SAMPLE : Sample Phase Indication
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b0 : IDLE

ADC1 is idle or converting

0b1 : ACTIVE

The Input signal is being sampled

End of enumeration elements list.

CHNR : Channel Number
bits : 3 - 4 (2 bit)
access : read-only

ANON_ST : Analog Part Switched On
bits : 8 - 8 (1 bit)
access : read-only

Enumeration:

0b00 : OFF

ADC1 switched off

0b01 : S_STANDBY

Slow standby mode

0b10 : F_STANDBY

Fast standby mode

0b11 : NORMAL

Normal Operation

End of enumeration elements list.


IS

ADC1 Interrupt Status Register
address_offset : 0x78 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IS IS read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0_STS CH1_STS CH2_STS CH3_STS CH4_STS CH5_STS CH6_STS CH7_STS EIM_STS ESM_STS

CH0_STS : ADC1 Channel 0 Interrupt Status
bits : 0 - -1 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

No Channel 0 Interrupt has occurred

0b1 : ACTIVE

Channel 0 Interrupt has occurred

End of enumeration elements list.

CH1_STS : ADC1 Channel 1 Interrupt Status
bits : 1 - 0 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

No Channel 1 Interrupt has occurred

0b1 : ACTIVE

Channel 1 Interrupt has occurred

End of enumeration elements list.

CH2_STS : ADC1 Channel 2 Interrupt Status
bits : 2 - 1 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

No Channel 2 Interrupt has occurred

0b1 : ACTIVE

Channel 2 Interrupt has occurred

End of enumeration elements list.

CH3_STS : ADC1 Channel 3 Interrupt Status
bits : 3 - 2 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

No Channel 3 Interrupt has occurred

0b1 : ACTIVE

Channel 3 Interrupt has occurred

End of enumeration elements list.

CH4_STS : ADC1 Channel 4 Interrupt Status
bits : 4 - 3 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

No Channel 4 Interrupt has occurred

0b1 : ACTIVE

Channel 4 Interrupt has occurred

End of enumeration elements list.

CH5_STS : ADC1 Channel 5 Interrupt Status
bits : 5 - 4 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

No Channel 5 Interrupt has occurred

0b1 : ACTIVE

Channel 5 Interrupt has occurred

End of enumeration elements list.

CH6_STS : ADC1 Channel 6 Interrupt Status
bits : 6 - 5 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

No Channel 6 Interrupt has occurred

0b1 : ACTIVE

Channel 6 Interrupt has occurred

End of enumeration elements list.

CH7_STS : ADC1 Channel 7 Interrupt Status
bits : 7 - 6 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

No Channel 7 Interrupt has occurred

0b1 : ACTIVE

Channel 7 Interrupt has occurred

End of enumeration elements list.

EIM_STS : Exceptional Interrupt Measurement (EIM) Status
bits : 8 - 7 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

No EIM occurred

0b1 : ACTIVE

EIM occurred

End of enumeration elements list.

ESM_STS : Exceptional Sequence Measurement (ESM) Status
bits : 9 - 8 (0 bit)
access : read-only

Enumeration:

0b0 : INACTIVE

No ESM has occurred

0b1 : ACTIVE

ESM occurred

End of enumeration elements list.


IE

ADC1 Interrupt Enable Register
address_offset : 0x7C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

IE IE read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0_IE CH1_IE CH2_IE CH3_IE CH4_IE CH5_IE CH6_IE CH7_IE EIM_IE ESM_IE

CH0_IE : ADC1 Channel 0 Interrupt Enable
bits : 0 - -1 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLED

Interrupt disabled

0b1 : ENABLED

Interrupt enabled

End of enumeration elements list.

CH1_IE : ADC1 Channel 1 Interrupt Enable
bits : 1 - 0 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLED

Interrupt disabled

0b1 : ENABLED

Interrupt enabled

End of enumeration elements list.

CH2_IE : ADC1 Channel 2 Interrupt Enable
bits : 2 - 1 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLED

Interrupt disabled

0b1 : ENABLED

Interrupt enabled

End of enumeration elements list.

CH3_IE : ADC1 Channel 3 Interrupt Enable
bits : 3 - 2 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLED

Interrupt disabled

0b1 : ENABLED

Interrupt enabled

End of enumeration elements list.

CH4_IE : ADC1 Channel 4 Interrupt Enable
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLED

Interrupt disabled

0b1 : ENABLED

Interrupt enabled

End of enumeration elements list.

CH5_IE : ADC1 Channel 5 Interrupt Enable
bits : 5 - 4 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLED

Interrupt disabled

0b1 : ENABLED

Interrupt enabled

End of enumeration elements list.

CH6_IE : ADC1 Channel 6 Interrupt Enable
bits : 6 - 5 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLED

Interrupt disabled

0b1 : ENABLED

Interrupt enabled

End of enumeration elements list.

CH7_IE : ADC1 Channel 7 Interrupt Enable
bits : 7 - 6 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLED

Interrupt disabled

0b1 : ENABLED

Interrupt enabled

End of enumeration elements list.

EIM_IE : Exceptional Interrupt Measurement (EIM) Interrupt Enable
bits : 8 - 7 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLED

Interrupt disabled

0b1 : ENABLED

Interrupt enabled

End of enumeration elements list.

ESM_IE : Exceptional Sequence Measurement (ESM) Interrupt Enable
bits : 9 - 8 (0 bit)
access : read-write

Enumeration:

0b0 : DISABLED

Interrupt disabled

0b1 : ENABLED

Interrupt enabled

End of enumeration elements list.


CHx_EIM

Channel Settings Bits for Exceptional Interrupt Measurement
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHx_EIM CHx_EIM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHx REP TRIG_SEL

CHx : Channel set for exceptional interrupt measurement (EIM)
bits : 0 - 1 (2 bit)
access : read-write

Enumeration:

0b000 : CH0_EN

Channel 0 enable

0b001 : CH1_EN

Channel 1 enable

0b010 : CH2_EN

Channel 2 enable

0b011 : CH3_EN

Channel 3 enable

0b100 : CH4_EN

Channel 4 enable

0b101 : CH5_EN

Channel 5 enable

0b110 : CH6_EN

Channel 6 enable

0b111 : CH7_EN

Channel 7 enable

End of enumeration elements list.

REP : Repeat count for exceptional interrupt measurement (EIM)
bits : 4 - 5 (2 bit)
access : read-write

Enumeration:

0b000 : 1

Measurement

0b001 : 2

Measurements

0b010 : 4

Measurements

0b011 : 8

Measurements

0b100 : 16

Measurements

0b101 : 32

Measurements

0b110 : 64

Measurements

0b111 : 128

Measurements

End of enumeration elements list.

TRIG_SEL : Trigger selection for exceptional interrupt measurement (EIM)
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0b000 : NONE

.

0b001 : COUT63

.

0b010 : GPT12_T6OUT

.

0b011 : GPT12_T3OUT

.

0b100 : T2

t2_adc_trigger

0b101 : T21

t21_adc_trigger

0b110 : CCU_6_INT

ccu6_int

End of enumeration elements list.


ICLR

ADC1 Interrupt Status Clear Register
address_offset : 0x80 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

ICLR ICLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CH0_ICLR CH1_ICLR CH2_ICLR CH3_ICLR CH4_ICLR CH5_ICLR CH6_ICLR CH7_ICLR EIM_ICLR ESM_ICLR

CH0_ICLR : ADC1 Channel 0 Interrupt Status Clear
bits : 0 - -1 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

interrupt status is not cleared

0b1 : ACTIVE

interrupt status is cleared

End of enumeration elements list.

CH1_ICLR : ADC1 Channel 1 Interrupt Status Clear
bits : 1 - 0 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

interrupt status is not cleared

0b1 : ACTIVE

interrupt status is cleared

End of enumeration elements list.

CH2_ICLR : ADC1 Channel 2 Interrupt Status Clear
bits : 2 - 1 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

interrupt status is not cleared

0b1 : ACTIVE

interrupt status is cleared

End of enumeration elements list.

CH3_ICLR : ADC1 Channel 3 Interrupt Status Clear
bits : 3 - 2 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

interrupt status is not cleared

0b1 : ACTIVE

interrupt status is cleared

End of enumeration elements list.

CH4_ICLR : ADC1 Channel 4 Interrupt Status Clear
bits : 4 - 3 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

interrupt status is not cleared

0b1 : ACTIVE

interrupt status is cleared

End of enumeration elements list.

CH5_ICLR : ADC1 Channel 5 Interrupt Status Clear
bits : 5 - 4 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

interrupt status is not cleared

0b1 : ACTIVE

interrupt status is cleared

End of enumeration elements list.

CH6_ICLR : ADC1 Channel 6 Interrupt Status Clear
bits : 6 - 5 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

interrupt status is not cleared

0b1 : ACTIVE

interrupt status is cleared

End of enumeration elements list.

CH7_ICLR : ADC1 Channel 7 Interrupt Status Clear
bits : 7 - 6 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

interrupt status is not cleared

0b1 : ACTIVE

interrupt status is cleared

End of enumeration elements list.

EIM_ICLR : Exceptional Interrupt Measurement (EIM) Status Clear
bits : 8 - 7 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

No EIM cleared

0b1 : ACTIVE

EIM cleared

End of enumeration elements list.

ESM_ICLR : Exceptional Sequence Measurement (ESM) Status Clear
bits : 9 - 8 (0 bit)
access : write-only

Enumeration:

0b0 : INACTIVE

No ESM has cleared

0b1 : ACTIVE

ESM cleared

End of enumeration elements list.


CHx_ESM

Channel Settings Bits for Exceptional Sequence Measurement
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

CHx_ESM CHx_ESM read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ESM_0 TRIG_SEL

ESM_0 : Channel Sequence for Exceptional Sequence Measurement (ESM)
bits : 0 - 6 (7 bit)
access : read-write

TRIG_SEL : Trigger selection for exceptional interrupt measurement (ESM)
bits : 16 - 17 (2 bit)
access : read-write

Enumeration:

0b000 : NONE

.

0b001 : COUT63

.

0b010 : GPT12_T6OUT

.

0b011 : GPT12_T3OUT

.

0b100 : T2

t2_adc_trigger

0b101 : T21

t21_adc_trigger

0b110 : CCU_6_INT

ccu6_int

End of enumeration elements list.



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