Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SysTick Control and Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ENABLE : Enable
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
counter disabled.
0b1 : value2
counter operates in a multi-shot way. That is, counter loads with the Reload value and then begins counting down. On reaching 0, it sets the COUNTFLAG to 1 and optionally pends the SysTick handler, based on TICKINT. It then loads the Reload value again, and begins counting.
End of enumeration elements list.
TICKINT : Enables SysTick exception request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLED
counting down to zero does not assert the SysTick exception request
0b1 : ENABLED
counting down to zero asserts the SysTick exception request
End of enumeration elements list.
CLKSOURCE : CLK Source
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
external reference clock (STCLK : 4:1 from hclk)
0b1 : value2
core clock (HCLK)
End of enumeration elements list.
COUNTFLAG : Count Flag
bits : 16 - 15 (0 bit)
access : read-write
Interrupt Set-Enable
address_offset : 0x100 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Int_GPT1 : Interrupt Set for GPT1
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_GPT2 : Interrupt Set for GPT2
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_ADC2 : Interrupt Set for MU, ADC2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_ADC1 : Interrupt Set for ADC1
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR0 : Interrupt Set for CCU6 SR0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR1 : Interrupt Set for CCU6 SR1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR2 : Interrupt Set for CCU6 SR2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR3 : Interrupt Set for CCU6 SR3
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_SSC1 : Interrupt Set for SSC1
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_SSC2 : Interrupt Set for SSC2
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_UART1 : Interrupt Set for UART1
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_UART2 : Interrupt Set for UART2
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_EXINT0 : Interrupt Set for External Int 0
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_EXINT1 : Interrupt Set for External Int 1
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_BDRV : Interrupt Set for Bridge Driver
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_DMA : Interrupt Set for DMA
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
SysTick Reload Value
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
RELOAD : Reload
bits : 0 - 22 (23 bit)
access : read-write
SysTick Current Value
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CURRENT : Current
bits : 0 - 22 (23 bit)
access : read-write
Interrupt Clear-Enable
address_offset : 0x180 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Int_GPT1 : Interrupt Clear for GPT1
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_GPT2 : Interrupt Clear for GPT2
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_ADC2 : Interrupt Clear for MU, ADC2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_ADC1 : Interrupt Clear for ADC1
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR0 : Interrupt Clear for CCU6 SR0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR1 : Interrupt Clear for CCU6 SR1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR2 : Interrupt Clear for CCU6 SR2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR3 : Interrupt Clear for CCU6 SR3
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_SSC1 : Interrupt Clear for SSC1
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_SSC2 : Interrupt Clear for SSC2
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_UART1 : Interrupt Clear for UART1
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_UART2 : Interrupt Clear for UART2
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_EXINT0 : Interrupt Clear for External Int 0
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_EXINT1 : Interrupt Clear for External Int 1
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_BDRV : Interrupt Clear for Bridge Driver
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_DMA : Interrupt Clr for DMA
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
SysTick Calibration Value
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TENMS : Tenms
bits : 0 - 22 (23 bit)
access : read-only
SKEW : Skew
bits : 30 - 29 (0 bit)
access : read-only
Enumeration:
0b0 : value1
n.u.
0b1 : value2
the calibration value is not exactly 10 ms because of clock frequency. This could affect its suitability as a software real time clock.
End of enumeration elements list.
NOREF : No Reference Clock
bits : 31 - 30 (0 bit)
access : read-only
Enumeration:
0b0 : value1
n.u.
0b1 : value2
the reference clock is not provided
End of enumeration elements list.
Interrupt Set-Pending
address_offset : 0x200 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Int_GPT1 : Interrupt Set Pending for GPT1
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_GPT2 : Interrupt Set Pending for GPT2
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_ADC2 : Interrupt Set Pending for MU, ADC2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_ADC1 : Interrupt Set Pending for ADC1
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR0 : Interrupt Set Pending for CCU6 SR0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR1 : Interrupt Set Pending for CCU6 SR1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR2 : Interrupt Set Pending for CCU6 SR2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR3 : Interrupt Set Pending for CCU6 SR3
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_SSC1 : Interrupt Set Pending for SSC1
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_SSC2 : Interrupt Set Pending for SSC2
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_UART1 : Interrupt Set Pending for UART1
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_UART2 : Interrupt Set Pending for UART2
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_EXINT0 : Interrupt Set Pending for External Int 0
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_EXINT1 : Interrupt Set Pending for External Int 1
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_BDRV : Interrupt Set Pending for Bridge Driver
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_DMA : Interrupt Set Pend for DMA
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Interrupt Clear-Pending
address_offset : 0x280 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Int_GPT1 : Interrupt Clear Pending for GPT1
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_GPT2 : Interrupt Clear Pending for GPT2
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_ADC2 : Interrupt Clear Pending for MU, ADC2
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_ADC1 : Interrupt Clear Pending for ADC1
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR0 : Interrupt Clear Pending for CCU6 SR0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR1 : Interrupt Clear Pending for CCU6 SR1
bits : 5 - 4 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR2 : Interrupt Clear Pending for CCU6 SR2
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR3 : Interrupt Clear Pending for CCU6 SR3
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_SSC1 : Interrupt Clear Pending for SSC1
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_SSC2 : Interrupt Clear Pending for SSC2
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_UART1 : Interrupt Clear Pending for UART1
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_UART2 : Interrupt Clear Pending for UART2
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_EXINT0 : Interrupt Clear Pending for External Int 0
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_EXINT1 : Interrupt Clear Pending for External Int 1
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_BDRV : Interrupt Clear Pending for Bridge Driver
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_DMA : Interrupt Clr Pend for DMA
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Active Bit Register Interrupt Active Flags
address_offset : 0x300 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Int_GPT1 : Interrupt Active for GPT1
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_GPT2 : Interrupt Active for GPT2
bits : 1 - 0 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_ADC2 : Interrupt Active for MU, ADC2
bits : 2 - 1 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_ADC1 : Interrupt Active for ADC1
bits : 3 - 2 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR0 : Interrupt Active for CCU6 SR0
bits : 4 - 3 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR1 : Interrupt Active for CCU6 SR1
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR2 : Interrupt Active for CCU6 SR2
bits : 6 - 5 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_CCU6SR3 : Interrupt Active for CCU6 SR3
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_SSC1 : Interrupt Active for SSC1
bits : 8 - 7 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_SSC2 : Interrupt Active for SSC2
bits : 9 - 8 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_UART1 : Interrupt Active for UART1
bits : 10 - 9 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_UART2 : Interrupt Active for UART2
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_EXINT0 : Interrupt Active for External Int 0
bits : 12 - 11 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_EXINT1 : Interrupt Active for External Int 1
bits : 13 - 12 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_BDRV : Interrupt Active for Bridge Driver
bits : 14 - 13 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Int_DMA : Interrupt Active for DMA
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLE
disables interrupt for read operation, no effect for write operation
0b1 : ENABLE
enables interrupt for read and write operation
End of enumeration elements list.
Interrupt Controller Type
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
INTLINESNUM : Interrupt Lines
bits : 0 - 3 (4 bit)
access : read-only
Enumeration:
0b00000 : value1
0 to 32
0b00001 : value2
33 to 64
0b00010 : value3
65 to 95
0b00011 : value4
97 to 128
0b00100 : value5
129 to 160
0b00101 : value6
161 to 192
0b00110 : value7
193 to 224
0b00111 : value8
225 to 256
End of enumeration elements list.
Interrupt Priority
address_offset : 0x400 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_GPT1 : Priority for GPT1
bits : 0 - 6 (7 bit)
access : read-write
PRI_GPT2 : Priority for GPT2
bits : 8 - 14 (7 bit)
access : read-write
PRI_ADC2 : Priority for MU, ADC2
bits : 16 - 22 (7 bit)
access : read-write
PRI_ADC1 : Priority for ADC1
bits : 24 - 30 (7 bit)
access : read-write
Interrupt Priority
address_offset : 0x404 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_CCU6SR0 : Priority for CCU6 SR0
bits : 0 - 6 (7 bit)
access : read-write
PRI_CCU6SR1 : Priority for CCU6 SR1
bits : 8 - 14 (7 bit)
access : read-write
PRI_CCU6SR2 : Priority for CCU6 SR2
bits : 16 - 22 (7 bit)
access : read-write
PRI_CCU6SR3 : Priority for CCU6 SR3
bits : 24 - 30 (7 bit)
access : read-write
Interrupt Priority
address_offset : 0x408 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_SSC1 : Priority for SSC1
bits : 0 - 6 (7 bit)
access : read-write
PRI_SSC2 : Priority for SSC2
bits : 8 - 14 (7 bit)
access : read-write
PRI_UART1 : Priority for UART1
bits : 16 - 22 (7 bit)
access : read-write
PRI_UART2 : Priority for UART2
bits : 24 - 30 (7 bit)
access : read-write
Interrupt Priority
address_offset : 0x40C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_EXINT0 : Priority for Ext. Int 0
bits : 0 - 6 (7 bit)
access : read-write
PRI_EXINT1 : Priority for Ext. Int 1
bits : 8 - 14 (7 bit)
access : read-write
PRI_BDRV : Priority for Bridge Driver
bits : 16 - 22 (7 bit)
access : read-write
PRI_DMA : Priority for DMA
bits : 24 - 30 (7 bit)
access : read-write
CPU ID Base Register
address_offset : 0xD00 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
REVISION : Revision Number
bits : 0 - 2 (3 bit)
access : read-only
PARTNO : Part Number
bits : 4 - 14 (11 bit)
access : read-only
ARCHITECTURE : Architecture
bits : 16 - 18 (3 bit)
access : read-only
VARIANT : Variant Number
bits : 20 - 22 (3 bit)
access : read-only
IMPLEMENTER : Implementer Code
bits : 24 - 30 (7 bit)
access : read-only
Interrupt Control State Register
address_offset : 0xD04 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTACTIVE : Active ISR number field
bits : 0 - 7 (8 bit)
access : read-only
RETTOBASE : RETTOBASE
bits : 11 - 10 (0 bit)
access : read-only
Enumeration:
0b0 : value1
There is an active exception other than the exception shown by IPSR.
0b1 : value2
There is no active exception other than any exception shown by IPSR.
End of enumeration elements list.
VECTPENDING : Pending ISR number field
bits : 12 - 19 (8 bit)
access : read-only
ISRPENDING : Interrupt pending flag. Excludes NMI and Faults
bits : 22 - 21 (0 bit)
access : read-only
Enumeration:
0b0 : value1
no external interrupt is pending
0b1 : value2
external interrupt is pending
End of enumeration elements list.
ISRPREEMPT : ISRPREEMPT
bits : 23 - 22 (0 bit)
access : read-only
Enumeration:
0b0 : value1
will not service
0b1 : value2
will service a pending exception
End of enumeration elements list.
PENDSTCLR : SysTick exception clear-pending bit
bits : 25 - 24 (0 bit)
access : write-only
Enumeration:
0b0 : value1
no effect
0b1 : value2
remove pending status
End of enumeration elements list.
PENDSTSET : SysTick exception set-pending bit
bits : 26 - 25 (0 bit)
access : read-write
Enumeration:
0b0 : value1
on writes, has no effect. On reads, SysTick is not pending.
0b1 : value2
on writes, make SysTick exception pending. On reads, SysTick is pending.
End of enumeration elements list.
PENDSVCLR : PendSV clear-pending bit
bits : 27 - 26 (0 bit)
access : write-only
Enumeration:
0b0 : value1
no effect
0b1 : value2
remove pending status
End of enumeration elements list.
PENDSVSET : PendSV set-pending bit
bits : 28 - 27 (0 bit)
access : read-write
Enumeration:
0b0 : value1
on writes, has no effect. On reads, PendSV is not pending.
0b1 : value2
on writes, make PendSV exception pending. On reads, PendSV is pending.
End of enumeration elements list.
NMIPENDSET : NMI PendSet
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
0b0 : value1
on writes, has no effect. On reads, NMI is active.
0b1 : value2
on writes, make the NMI exception active. On reads, NMI is active.
End of enumeration elements list.
Vector Table Offset Register
address_offset : 0xD08 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
TBLOFF : Vector Table Offset
bits : 7 - 30 (24 bit)
access : read-write
Application Interrupt/Reset Control Register
address_offset : 0xD0C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTRESET : VECTRESET for debug only
bits : 0 - -1 (0 bit)
access : read-write
VECTCLRACTIVE : VECTCLRACTIVE for debug only
bits : 1 - 0 (0 bit)
access : read-write
SYSRESETREQ : System Reset Request
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
do not request a reset
0b1 : value2
request a reset
End of enumeration elements list.
PRIGROUP : Priority Grouping
bits : 8 - 9 (2 bit)
access : read-write
ENDIANNESS : Memory System Endianness
bits : 15 - 14 (0 bit)
access : read-only
Enumeration:
0b0 : value1
little endian
0b1 : value2
big endian
End of enumeration elements list.
VECTKEY : Vector Key
bits : 16 - 30 (15 bit)
access : read-write
System Control Register
address_offset : 0xD10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SLEEPONEXIT : Sleep on Exit
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
do not enter sleep state
0b1 : value2
enter sleep state
End of enumeration elements list.
SLEEPDEEP : Sleep Deep
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
selected sleep state is not deep sleep
0b1 : value2
selected sleep state is deep sleep
End of enumeration elements list.
SEVONPEND : SEVONPEND
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
transitions from inactive to pending are not wake-up events
0b1 : value2
transitions from inactive to pending are wake-up events
End of enumeration elements list.
Configuration Control Register
address_offset : 0xD14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
NONBASETHRDENA : Indicates how the processor enters Thread mode
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
any attempt to enter Thread mode at an execution priority level of other than base level faults.
0b1 : value2
the processor can enter Thread mode at any execution priority level because of a controlled return value.
End of enumeration elements list.
USERSETMPEND : Enables unprivileged software access to the STIR
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
unprivileged software cannot access the STIR.
0b1 : value2
unprivileged software can access the STIR.
End of enumeration elements list.
UNALIGN_TRP : Enables unaligned access traps
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
trapping disabled
0b1 : value2
trapping enabled
End of enumeration elements list.
DIV_0_TRP : Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
trapping disabled
0b1 : value2
trapping enabled
End of enumeration elements list.
BFHFMIGN : Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : value1
precise data access fault causes a lockup
0b1 : value2
handler ignores the fault
End of enumeration elements list.
STKALIGN : stack alignment
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : value1
guaranteed SP alignment is 4-byte, no SP adjustment is performed.
0b1 : value2
8-byte alignment guaranteed, SP adjusted if necessary.
End of enumeration elements list.
System Handler Priority Register 1
address_offset : 0xD18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_4 : Priority of System Handler 4, MemManage
bits : 0 - 6 (7 bit)
access : read-write
PRI_5 : Priority of System Handler 5, BusFault
bits : 8 - 14 (7 bit)
access : read-write
PRI_6 : Priority of System Handler 6, UsageFault
bits : 16 - 22 (7 bit)
access : read-write
PRI_7 : Reserved for Priority of System Handler 7
bits : 24 - 30 (7 bit)
access : read-write
System Handler Priority Register 2
address_offset : 0xD1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_8 : Reserved for Priority of System Handler 8
bits : 0 - 6 (7 bit)
access : read-write
PRI_9 : Reserved for Priority of System Handler 9
bits : 8 - 14 (7 bit)
access : read-write
PRI_10 : Reserved for Priority of System Handler 10
bits : 16 - 22 (7 bit)
access : read-write
PRI_11 : Priority of System Handler 11, SVCall
bits : 24 - 30 (7 bit)
access : read-write
System Handler Priority Register 3
address_offset : 0xD20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
PRI_12 : Priority of System Handler 12, DebugMonitor
bits : 0 - 6 (7 bit)
access : read-write
PRI_13 : Reserved for Priority of System Handler 13
bits : 8 - 14 (7 bit)
access : read-write
PRI_14 : Priority of System Handler 14, PendSV
bits : 16 - 22 (7 bit)
access : read-write
PRI_15 : Priority of System Handler 15, SysTick
bits : 24 - 30 (7 bit)
access : read-write
System Handler Control and State Register
address_offset : 0xD24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MEMFAULTACT : MEMFAULTACT
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
MemManage is not active
0b1 : value2
MemManage is active
End of enumeration elements list.
BUSFAULTACT : BUSFAULTACT
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
BusFault is not active
0b1 : value2
BusFault is active
End of enumeration elements list.
USGFAULTACT : USGFAULTACT
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
UsageFault is not active
0b1 : value2
UsageFault is active
End of enumeration elements list.
SVCALLACT : SVCALLACT
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
SVCall is not active
0b1 : value2
SVCall is active
End of enumeration elements list.
MONITORACT : MONITORACT
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Monitor is not active
0b1 : value2
Monitor is active
End of enumeration elements list.
PENDSVACT : PENDSVACT
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
0b0 : value1
PendSV is not active
0b1 : value2
PendSV is active
End of enumeration elements list.
SYSTICKACT : SYSTICKACT
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
0b0 : value1
SysTick is not active
0b1 : value2
SysTick is active
End of enumeration elements list.
USGFAULTPENDED : USGFAULTPENDED
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : value1
UsageFault is not pending
0b1 : value2
UsageFault is pending
End of enumeration elements list.
MEMFAULTPENDED : MEMFAULTPENDED
bits : 13 - 12 (0 bit)
access : read-write
Enumeration:
0b0 : value1
MemManage is not pending
0b1 : value2
MemManage is pending
End of enumeration elements list.
BUSFAULTPENDED : BUSFAULTPENDED
bits : 14 - 13 (0 bit)
access : read-write
Enumeration:
0b0 : value1
BusFault is not pending
0b1 : value2
BusFault is pending
End of enumeration elements list.
SVCALLPENDED : SVCALLPENDED
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
0b0 : value1
SVCall is not pending
0b1 : value2
SVCall is pending
End of enumeration elements list.
MEMFAULTENA : MEMFAULTENA
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Disable MemManage fault
0b1 : value2
Enable MemManage fault
End of enumeration elements list.
BUSFAULTENA : BUSFAULTENA
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Disable BusFault
0b1 : value2
Enable BusFault
End of enumeration elements list.
USGFAULTENA : USGFAULTENA
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
0b0 : value1
Disable UsageFault
0b1 : value2
Enable UsageFault
End of enumeration elements list.
Configurable Fault Status Register
address_offset : 0xD28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
IACCVIOL : Instruction access violation flag
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No MPU or Execute Never (XN) default memory map access violation has occurred.
0b1 : value2
MPU or Execute Never (XN) default memory map access violation on an instruction fetch has occurred. The fault is signalled only if the instruction is issued.
End of enumeration elements list.
DACCVIOL : Data access violation flag
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No data access violation has occurred.
0b1 : value2
Data access violation. The MMAR shows the data address that the load or store tried to access.
End of enumeration elements list.
MUNSTKERR : MemManage fault on unstacking for a return from exception
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No derived MemManage fault occurred
0b1 : value2
A derived MemManage fault occurred on exception return
End of enumeration elements list.
MSTERR : MemManage fault on stacking for exception entry
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No derived MemManage fault occurred
0b1 : value2
A derived MemManage fault occurred on exception entry
End of enumeration elements list.
MMARVALID : MemManage Fault Address Register (MMFAR) valid flag
bits : 7 - 6 (0 bit)
access : read-write
Enumeration:
0b0 : value1
MMAR does not have valid contents.
0b1 : value2
MMAR has valid contents.
End of enumeration elements list.
IBUSERR : Instruction bus error
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No bus fault on an instruction prefetch has occurred.
0b1 : value2
A bus fault on an instruction prefetch has occurred. The fault is signalled only if the instruction is issued.
End of enumeration elements list.
PRECISERR : Precise data bus error
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No precise data access error has occurred
0b1 : value2
An imprecise data access error has occurred, and the processor has written the faulting address to the BFAR.
End of enumeration elements list.
IMPRECISERR : Imprecise data bus error
bits : 10 - 9 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No precise data access error has occurred
0b1 : value2
An imprecise data access error has occurred.
End of enumeration elements list.
UNSTKERR : BusFault on unstacking for a return from exception
bits : 11 - 10 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No derived bus fault occurred
0b1 : value2
A derived bus fault occurred on exception return
End of enumeration elements list.
STKERR : BusFault on stacking for exception entry
bits : 12 - 11 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No derived bus fault occurred
0b1 : value2
A derived bus fault occurred on exception entry
End of enumeration elements list.
BFARVALID : BFAR Valid
bits : 15 - 14 (0 bit)
access : read-write
Enumeration:
0b0 : value1
BFAR does not have valid contents.
0b1 : value2
BFAR has valid contents.
End of enumeration elements list.
UNDEFINSTR : Undefined instruction UsageFault
bits : 16 - 15 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No Undefined Instruction Usage fault has occurred.
0b1 : value2
The processor hat attempted to execute an undefined instruction. This might be an undefined instruction associated with an enabled coprocessor.
End of enumeration elements list.
INVSTATE : Invalid state UsageFault
bits : 17 - 16 (0 bit)
access : read-write
Enumeration:
0b0 : value1
EPSR.T bit and EPSR.IT bits are valid for instruction execution.
0b1 : value2
Instruction executed with invalid EPSR.T or EPSR.IT field.
End of enumeration elements list.
INVPC : Invalid PC load UsageFault
bits : 18 - 17 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No integrity check error has occurred.
0b1 : value2
A integrity check error has occurred.
End of enumeration elements list.
NOCP : No coprocessor UsageFault
bits : 19 - 18 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No coprocessor access error has occurred.
0b1 : value2
A coprocessor access error has occurred.
End of enumeration elements list.
UNALIGNED : Unaligned access UsageFault
bits : 24 - 23 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No unaligned access error has occurred.
0b1 : value2
A unaligned access error has occurred.
End of enumeration elements list.
DIVBYZERO : Divide by Zero
bits : 25 - 24 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No Divide by zero error has occurred.
0b1 : value2
A divide by zero error has occurred.
End of enumeration elements list.
Hard Fault Status Register
address_offset : 0xD2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
VECTTBL : VECTTBL
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No vector table read fault has occurred
0b1 : value2
Vector table read fault has occurred
End of enumeration elements list.
FORCED : Forced
bits : 30 - 29 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No priority escalation has occurred
0b1 : value2
Processor has escalated a configurable priority exception to HardFault
End of enumeration elements list.
DEBUGEVT : Debug Event
bits : 31 - 30 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No Debug event has occurred
0b1 : value2
Debug event has occurred. The Debug Fault Status Register has been updated.
End of enumeration elements list.
Debug Fault Status Register
address_offset : 0xD30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
HALTED : HALTED
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No active halt request debug event
0b1 : value2
Halt request debug event active
End of enumeration elements list.
BKPT : BKPT
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No current breakpoint debug event
0b1 : value2
At least one current breakpoint debug event
End of enumeration elements list.
DWTTRAP : DWTTRAP
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No current debug event generated by the DWT
0b1 : value2
At least one current debug event generated by the DWT
End of enumeration elements list.
VCATCH : Vector Catch
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No vector catch triggered
0b1 : value2
Vector catch triggered
End of enumeration elements list.
EXTERNAL : External
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : value1
No EDBGRQ debug event
0b1 : value2
EDBGRQ debug event
End of enumeration elements list.
MemManage Fault Status Register
address_offset : 0xD34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Data Address for an MPU Fault
bits : 0 - 30 (31 bit)
access : read-write
Bus Fault Status Register
address_offset : 0xD38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ADDRESS : Data Address for a precise BusFault
bits : 0 - 30 (31 bit)
access : read-write
Auxiliary Fault Status Register
address_offset : 0xD3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CP0 : Access Privileges for Coprocessor 0 (n= 0-7, 10, 11)
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Access denied. Any attempted access generates a NOCP UsageFault
0b01 : value2
Privileged access only. An unprivileged access generates a NOCP UsageFault
0b11 : value4
Full access
End of enumeration elements list.
CP1 : Access Privileges for Coprocessor 1 (n= 0-7, 10, 11)
bits : 2 - 2 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Access denied. Any attempted access generates a NOCP UsageFault
0b01 : value2
Privileged access only. An unprivileged access generates a NOCP UsageFault
0b11 : value4
Full access
End of enumeration elements list.
CP2 : Access Privileges for Coprocessor 2 (n= 0-7, 10, 11)
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Access denied. Any attempted access generates a NOCP UsageFault
0b01 : value2
Privileged access only. An unprivileged access generates a NOCP UsageFault
0b11 : value4
Full access
End of enumeration elements list.
CP3 : Access Privileges for Coprocessor 3 (n= 0-7, 10, 11)
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Access denied. Any attempted access generates a NOCP UsageFault
0b01 : value2
Privileged access only. An unprivileged access generates a NOCP UsageFault
0b11 : value4
Full access
End of enumeration elements list.
CP4 : Access Privileges for Coprocessor 4 (n= 0-7, 10, 11)
bits : 8 - 8 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Access denied. Any attempted access generates a NOCP UsageFault
0b01 : value2
Privileged access only. An unprivileged access generates a NOCP UsageFault
0b11 : value4
Full access
End of enumeration elements list.
CP5 : Access Privileges for Coprocessor 5 (n= 0-7, 10, 11)
bits : 10 - 10 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Access denied. Any attempted access generates a NOCP UsageFault
0b01 : value2
Privileged access only. An unprivileged access generates a NOCP UsageFault
0b11 : value4
Full access
End of enumeration elements list.
CP6 : Access Privileges for Coprocessor 6 (n= 0-7, 10, 11)
bits : 12 - 12 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Access denied. Any attempted access generates a NOCP UsageFault
0b01 : value2
Privileged access only. An unprivileged access generates a NOCP UsageFault
0b11 : value4
Full access
End of enumeration elements list.
CP7 : Access Privileges for Coprocessor 7 (n= 0-7, 10, 11)
bits : 14 - 14 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Access denied. Any attempted access generates a NOCP UsageFault
0b01 : value2
Privileged access only. An unprivileged access generates a NOCP UsageFault
0b11 : value4
Full access
End of enumeration elements list.
CP10 : Access Privileges for Coprocessor 10 (n= 0-7, 10, 11)
bits : 20 - 20 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Access denied. Any attempted access generates a NOCP UsageFault
0b01 : value2
Privileged access only. An unprivileged access generates a NOCP UsageFault
0b11 : value4
Full access
End of enumeration elements list.
CP11 : Access Privileges for Coprocessor 11 (n= 0-7, 10, 11)
bits : 22 - 22 (1 bit)
access : read-write
Enumeration:
0b00 : value1
Access denied. Any attempted access generates a NOCP UsageFault
0b01 : value2
Privileged access only. An unprivileged access generates a NOCP UsageFault
0b11 : value4
Full access
End of enumeration elements list.
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