\n
address_offset : 0x0 Bytes (0x0)
size : 0x50 byte (0x0)
mem_usage : registers
protection : not protected
DMA Status
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASTER_ENABLE : Enable Status of the Controller
bits : 0 - -1 (0 bit)
access : read-only
Enumeration:
0b0 : DISABLED
controller is disabled
0b1 : ENABLED
controller is enabled
End of enumeration elements list.
STATE : Current State of the Control State Machine
bits : 4 - 6 (3 bit)
access : read-only
Enumeration:
0b0000 : value1
idle
0b0001 : value2
reading channel controller date
0b0010 : value3
reading source data end pointer
0b0011 : value4
reading destination data end pointer
0b0100 : value5
reading source data
0b0101 : value6
writing destination data
0b0110 : value7
waiting for DMA request to clear
0b0111 : value8
writing channel controller data
0b1000 : value9
stalled
0b1001 : value10
done
0b1010 : value11
peripheral scatter-gather transition
End of enumeration elements list.
CHNLS_MINUS1 : Available Channels minus 1
bits : 16 - 19 (4 bit)
access : read-only
Enumeration:
0b1101 : value1
controller configured to use 14 DMA channels
End of enumeration elements list.
Channel Wait on Request Status
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
WAITONREQ_STATUS : Channel Wait on Request Status
bits : 0 - 12 (13 bit)
access : read-only
Channel Software Request
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_SW_REQUEST : CHNL_SW_REQUEST
bits : 0 - 12 (13 bit)
access : write-only
Channel Useburst Set
address_offset : 0x18 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_USEBURST_SET : CHNL_USEBURST_SET: 0b0=on read: DMA channel n responds to requests that it receives on dma_req[C] or dma_sreq[C]. The controller performs 2, or single, bus transfers., 0b1=on read: DMA channel n does not respond to requests that it receives on dma_req[C] or dma_sreq[C]. The controller only reponds to dma_req[C] requests and performs 2 transfers., 0b0=on write: No effect. Use the CHNL_USEBURST_CLR Register to set bit [C] to 0., 0b1=on write: Disables dma_sreq[C] from generating DMA requests. The controller performs 2 transfers.,
bits : 0 - 12 (13 bit)
access : read-write
Channel Useburst Clear
address_offset : 0x1C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_USEBURST_CLR : CHNL_USEBURST_CLR
bits : 0 - 12 (13 bit)
access : write-only
Channel Request Mask Set
address_offset : 0x20 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_REQ_MASK_SET : CHNL_REQ_MASK_SET: 0b0=on read: External requests are enabled for channel C., 0b1=on read: External requests are disabled for channel C., 0b0=on write: No effect. Use the CHNL_REQ_MASK_CLR Register to enable DMA requests., 0b1=on write: Disables dma_req[C] and dma_sreq[C] from generating DMA requests.,
bits : 0 - 12 (13 bit)
access : read-write
Channel Request Mask Clear
address_offset : 0x24 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_REQ_MASK_CLR : CHNL_REQ_MASK_CLR
bits : 0 - 12 (13 bit)
access : write-only
Channel Enable Set
address_offset : 0x28 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_ENABLE_SET : CHNL_ENABLE_SET: 0b0=on read: Channel C is disabled., 0b1=on read: Channel C is enabled., 0b0=on write: No effect. Use the CHNL_ENABLE_CLR Register to disable a channel., 0b1=on write: Enables channel C.,
bits : 0 - 12 (13 bit)
access : read-write
Channel Enable Clear
address_offset : 0x2C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_ENABLE_CLR : CHNL_ENABLE_CLR
bits : 0 - 12 (13 bit)
access : write-only
Channel Primary-Alternate Set
address_offset : 0x30 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_PRI_ALT_SET : CHNL_PRI_ALT_SET: 0b0=on read: DMA channel C is using the primary data structure., 0b1=on read: DMA channel C is using the alternate data structure., 0b0=on write: No effect. Use the CHNL_PRI_ALT_CLR Register to set bit [C] to 0., 0b1=on write: Selects the alternate data structure for channel C.,
bits : 0 - 12 (13 bit)
access : read-write
Channel Primary-Alternate Clear
address_offset : 0x34 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_PRI_ALT_CLR : CHNL_PRI_ALT_CLR
bits : 0 - 12 (13 bit)
access : write-only
Channel Priority Set
address_offset : 0x38 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_PRIORITY_SET : CHNL_PRIORITY_SET: 0b0=on read: DMA channel C is using the default priority level., 0b1=on read: DMA channel C is using a high priority level., 0b0=on write: No effect. Use the CHNL_ENABLE_CLR Register to set channel C to the default priority level., 0b1=on write: Channel C uses the high priority level.,
bits : 0 - 12 (13 bit)
access : read-write
Channel Priority Clear
address_offset : 0x3C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CHNL_PRIORITY_CLR : CHNL_PRIORITY_CLR
bits : 0 - 12 (13 bit)
access : write-only
DMA Configuration
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
MASTER_ENABLE : Enable for the Controller
bits : 0 - -1 (0 bit)
access : write-only
Enumeration:
0b0 : DISABLE
disables the controller
0b1 : ENABLE
enables the controller
End of enumeration elements list.
CHN1_PROT_CTRL : CHN1_PROT_CTRL
bits : 5 - 6 (2 bit)
access : write-only
Bus Error Clear
address_offset : 0x4C Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ERR_CLR : ERR_CLR: 0b0=on read: dma_err is LOW., 0b1=on read: dma_err is HIGH., 0b0=on write: No effect, status of dma_err is unchanged., 0b1=on write: Sets dma_err LOW.,
bits : 0 - -1 (0 bit)
access : read-write
Channel Control Data Base Pointer
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
CTRL_BASE_PTR : CTRL_BASE_PTR
bits : 9 - 30 (22 bit)
access : read-write
Channel Alternate Control Data Base Pointer
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ALT_CTRL_BASE_PTR : Base Address of the Alternate Data Structure
bits : 0 - 30 (31 bit)
access : read-only
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