\n
address_offset : 0x0 Bytes (0x0)
size : 0x21 byte (0x0)
mem_usage : registers
protection : not protected
T3 Trigger Control
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T3_TRIGG_INP_SEL : Timer 3 Trigger Input Event Selection (only in mode3b)
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0x0 : CCU6_CC6_0
Capture Compare Unit Channel 0 (CC60).
0x1 : CCU6_CC61
Capture Compare Unit Channel 1 (CC61).
0x2 : CCU6_CC62
Capture Compare Unit Channel 2 (CC62).
0x3 : CCU6_T12_ZM
Capture Compare Unit T12 Zero Match.
0x4 : CCU6_T12_PM
Capture Compare Unit T12 Period Match.
0x5 : CCU6_COUT6_0
Capture Compare Unit Channel 0 (COUT60).
0x6 : CCU6_COUT61
Capture Compare Unit Channel 1 (COUT61).
0x7 : CCU6_COUT62
Capture Compare Unit Channel 2 (COUT62).
End of enumeration elements list.
T3_RES_CONF : Timer 3 Trigger Reset Selection for Mode 1b
bits : 4 - 4 (1 bit)
access : read-write
Enumeration:
0x0 : No_Reset_on_PWM_Edge
Counter is not reset while PWM Module is running.
0x1 : Reset_On_Rising_Edge
Counter is reset on rising edge input
0x2 : Reset_On_Falling_Edge
Counter is reset on falling edge input.
0x3 : Reset_on_both_Edges
Counter is reset on both edge inputs.
End of enumeration elements list.
RETRIG : Retrigger Condition (in mode 1b) for CCU6-T12 ZM and CCU6 PM
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : DIS
Retrigger disabled
0b1 : EN
Retrigger enabled
End of enumeration elements list.
Timer 3 Mode Configuration Register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T3M : Mode Select Bits
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
0b00 : Mode_0
13-bit timer
0b01 : Mode_1
16-bit timer
0b10 : Mode_2
8-bit auto-reload timer
0b11 : Mode_3
Timer 3 is split into two halves. TL3 is an 8bit timer controlled by the standard Timer 3 low byte control bits, and TH3 is the other 8-bit timer controlled by the standard Timer 3 high byte control bits.
End of enumeration elements list.
T3_SUBM : Sub-Mode Select Bits
bits : 6 - 6 (1 bit)
access : read-write
Enumeration:
0b00 : No_Sub_Mode
no Sub-Mode enabled
0b01 : Mode_1b
enables 16 bit Timer triggered by an event. This mode has only an effect with Mode 1 (16 Bit Mode)
0b10 : Mode_3b
enables two 8-Bit Timers for clock measurement. This Mode has only an effect with Mode 3.
End of enumeration elements list.
Timer 3 Interrupt Status Clear Register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T3H_OVF_ICLR : Timer 3 Overflow Flag (High Byte Timer) Interrupt Clear
bits : 5 - 4 (0 bit)
access : write-only
Enumeration:
0b0 : no_action
Overflow not cleared.
0b1 : Clear
Overflow cleared. Set by software, cleared by hardware
End of enumeration elements list.
T3L_OVF_ICLR : Timer 3 Overflow Flag (Low Byte Timer) Interrupt Clear
bits : 7 - 6 (0 bit)
access : write-only
Enumeration:
0b0 : no_action
Overflow not cleared.
0b1 : Clear
Overflow cleared. Set by software, cleared by hardware.
End of enumeration elements list.
Timer 3 Compare Value
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LO : Timer 3 Compare Value Low Byte
bits : 0 - 6 (7 bit)
access : read-write
HI : Timer 3 Compare Value High Byte
bits : 8 - 14 (7 bit)
access : read-write
Timer 3
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LO : Timer 3 Low Register or Preload Value
bits : 0 - 6 (7 bit)
access : read-write
HI : Timer 3 High Register or Preload Value
bits : 8 - 14 (7 bit)
access : read-write
Timer 3 Control Register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T3_PD_N : Timer 3 Power Down
bits : 0 - -1 (0 bit)
access : read-write
Enumeration:
0b0 : Power_Down
Timer 3 is in Power Down
0b1 : no_Power_Down
Timer 3 is not in Power Down
End of enumeration elements list.
T3_RD_REQ : Timer 3 Value Read Request
bits : 1 - 0 (0 bit)
access : read-write
Enumeration:
0b0 : DISABLED
Timer value is not read from Timer 3
0b1 : ENABLED
Timer value is read from Timer 3
End of enumeration elements list.
T3_RD_REQ_CONF : Timer 3 Read Mode
bits : 2 - 1 (0 bit)
access : read-write
Enumeration:
0b0 : Software
Timer 3 Read Request can be triggered by software
0b1 : Hardware
Timer 3 Read Request can be triggered by hardware (in mode 3b)
End of enumeration elements list.
CNT_RDY : Timer 3 Count Ready
bits : 3 - 2 (0 bit)
access : read-write
Enumeration:
0b0 : Busy
Timer hasn't finished counting in Mode 1b, 3b
0b1 : Ready
Timer has finished counting in Mode 1b, 3b
End of enumeration elements list.
TR3H : Timer 3 Run Control (High Byte Timer)
bits : 4 - 3 (0 bit)
access : read-write
Enumeration:
0b0 : Stop
Timer is halted
0b1 : Run
Timer runs
End of enumeration elements list.
T3H_OVF_STS : Timer 3 Overflow Flag (High Byte Timer)
bits : 5 - 4 (0 bit)
access : read-only
Enumeration:
0b0 : clear
No Overflow occured.
0b1 : Set
Overflow occured. Set by hardware when High Byte of Timer 3 overflows. Cleared by software.
End of enumeration elements list.
TR3L : Timer 3 Run Control (Low Byte Timer)
bits : 6 - 5 (0 bit)
access : read-write
Enumeration:
0b0 : Stop
Timer is halted
0b1 : Run
Timer runs
End of enumeration elements list.
T3L_OVF_STS : Timer 3 Overflow Flag (Low Byte Timer)
bits : 7 - 6 (0 bit)
access : read-only
Enumeration:
0b0 : clear
No overflow occurred.
0b1 : Set
Overflow occured. Set by hardware when Low Byte of Timer 3 overflows. Cleared by software.
End of enumeration elements list.
T3L_OVF_IE : Timer 3 Overflow Interrupt Enable (Low Byte Timer)
bits : 8 - 7 (0 bit)
access : read-write
Enumeration:
0b0 : DIS
Interrupt disabled.
0b1 : EN
Interrupt enabled
End of enumeration elements list.
T3H_OVF_IE : Timer 3 Overflow Interrupt Enable (High Byte Timer)
bits : 9 - 8 (0 bit)
access : read-write
Enumeration:
0b0 : DIS
Interrupt disabled
0b1 : EN
Interrupt enabled
End of enumeration elements list.
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