\n

UART1

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x2000 byte (0x0)
mem_usage : registers
protection : not protected

Registers

SCON

SBUF

SCONCLR


SCON

Serial Channel Control Register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCON SCON read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RI TI RB8 TB8 REN SM2 SM1_SM0

RI : Receive Interrupt Flag
bits : 0 - -1 (0 bit)
access : read-write

TI : Transmit Interrupt Flag
bits : 1 - 0 (0 bit)
access : read-write

RB8 : Serial Port Receiver Bit 9
bits : 2 - 1 (0 bit)
access : read-write

TB8 : Serial Port Transmitter Bit 9
bits : 3 - 2 (0 bit)
access : read-write

REN : Enable Receiver of Serial Port
bits : 4 - 3 (0 bit)
access : read-write

Enumeration:

0b0 : value1

Serial reception is disabled.

0b1 : value2

Serial reception is enabled.

End of enumeration elements list.

SM2 : Enable Serial Port Multiprocessor Communication in Modes 2 and 3
bits : 5 - 4 (0 bit)
access : read-write

SM1_SM0 : Serial Port Operating Mode Selection
bits : 6 - 6 (1 bit)
access : read-write

Enumeration:

0b00 : value1

Mode 0: 8-bit shift register, fixed baud rate (fPCLK/2).

0b01 : value2

Mode 1: 8-bit UART, variable baud rate.

0b10 : value3

Mode 2: 9-bit UART, fixed baud rate (fPCLK/64 or fPCLK/32).

0b11 : value4

Mode 3: 9-bit UART, variable baud rate.

End of enumeration elements list.


SBUF

Serial Data Buffer
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SBUF SBUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VAL

VAL : Serial Interface Buffer Register
bits : 0 - 6 (7 bit)
access : read-write


SCONCLR

Serial Channel Control Clear Register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

SCONCLR SCONCLR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RICLR TICLR

RICLR : Receive Interrupt Clear Flag
bits : 0 - -1 (0 bit)
access : write-only

TICLR : Transmit Interrupt Clear Flag
bits : 1 - 0 (0 bit)
access : write-only



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