\n
address_offset : 0x0 Bytes (0x0)
size : 0x14 byte (0x0)
mem_usage : registers
protection : not protected
Frequency control register 01
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SYSC : -
bits : 0 - 2 (3 bit)
access : read-write
OSCM : -
bits : 3 - 7 (5 bit)
access : read-write
SYSCLK : -
bits : 8 - 16 (9 bit)
access : read-write
ENOSC : -
bits : 9 - 18 (10 bit)
access : read-write
ENPLL : -
bits : 10 - 20 (11 bit)
access : read-write
XSPEN : -
bits : 12 - 24 (13 bit)
access : read-write
LOSST : -
bits : 14 - 28 (15 bit)
access : read-only
LPLL : -
bits : 15 - 30 (16 bit)
access : read-only
Frequency control register 23
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
XTM : -
bits : 0 - 1 (2 bit)
access : read-write
OUTLC : -
bits : 3 - 6 (4 bit)
access : read-write
LFLTSEL : -
bits : 4 - 8 (5 bit)
access : read-write
CR16DC : -
bits : 8 - 16 (9 bit)
access : read-write
CR16ENC : -
bits : 9 - 18 (10 bit)
access : read-write
Frequency status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LOSCS : -
bits : 2 - 4 (3 bit)
access : read-only
C16MCDO : -
bits : 6 - 12 (7 bit)
access : read-only
C16MBS : -
bits : 7 - 14 (8 bit)
access : read-only
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