\n
address_offset : 0x0 Bytes (0x0)
size : 0x10 byte (0x0)
mem_usage : registers
protection : not protected
Low-speed time base counter register
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
T128HZ : -
bits : 0 - 0 (1 bit)
access : read-write
T64HZ : -
bits : 1 - 2 (2 bit)
access : read-write
T32HZ : -
bits : 2 - 4 (3 bit)
access : read-write
T16HZ : -
bits : 3 - 6 (4 bit)
access : read-write
T8HZ : -
bits : 4 - 8 (5 bit)
access : read-write
T4HZ : -
bits : 5 - 10 (6 bit)
access : read-write
T2HZ : -
bits : 6 - 12 (7 bit)
access : read-write
T1HZ : -
bits : 7 - 14 (8 bit)
access : read-write
Low-speed time base counter frequency adjustment register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LADJ : -
bits : 0 - 10 (11 bit)
access : read-write
Low-speed time base counter interrupt select resister
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTI0S : -
bits : 0 - 3 (4 bit)
access : read-write
LTI1S : -
bits : 4 - 11 (8 bit)
access : read-write
LTI2S : -
bits : 8 - 19 (12 bit)
access : read-write
Low-speed time base counter interrupt status register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0
LTBINT0 : -
bits : 0 - 0 (1 bit)
access : read-write
LTBINT1 : -
bits : 1 - 2 (2 bit)
access : read-write
LTBINT2 : -
bits : 2 - 4 (3 bit)
access : read-write
Is something missing? Is something wrong? can you help correct it ? Please contact us at info@chipselect.org !
This website is sponsored by Embeetle, an IDE designed from scratch for embedded software developers.