\n

UARTF

Peripheral Memory Blocks

address_offset : 0x0 Bytes (0x0)
size : 0x18 byte (0x0)
mem_usage : registers
protection : not protected

Registers

UAF0BUF

UAF0LSR

UAF0CAJ

UAF0IER

UAF0IIR

UAF0MOD


UAF0BUF

UARTF0 transmit/receive buffer
address_offset : 0x0 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UAF0BUF UAF0BUF read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF0B

UF0B : -
bits : 0 - 15 (16 bit)
access : read-write


UAF0LSR

UARTF0 line status register
address_offset : 0x10 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UAF0LSR UAF0LSR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF0DR UF0OER UF0PER UF0FER UF0BI UF0THRE UF0TEMT UF0RFE UF0TIDL

UF0DR : -
bits : 0 - 0 (1 bit)
access : read-only

UF0OER : -
bits : 1 - 2 (2 bit)
access : read-only

UF0PER : -
bits : 2 - 4 (3 bit)
access : read-only

UF0FER : -
bits : 3 - 6 (4 bit)
access : read-only

UF0BI : -
bits : 4 - 8 (5 bit)
access : read-only

UF0THRE : -
bits : 5 - 10 (6 bit)
access : read-only

UF0TEMT : -
bits : 6 - 12 (7 bit)
access : read-only

UF0RFE : -
bits : 7 - 14 (8 bit)
access : read-only

UF0TIDL : -
bits : 8 - 16 (9 bit)
access : read-only


UAF0CAJ

UARTF0 clock adjustment register
address_offset : 0x14 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UAF0CAJ UAF0CAJ read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF0CAJ UF0RMV

UF0CAJ : -
bits : 0 - 4 (5 bit)
access : read-write

UF0RMV : -
bits : 6 - 12 (7 bit)
access : read-write


UAF0IER

UARTF0 interrupt enable register
address_offset : 0x4 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UAF0IER UAF0IER read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF0ERBFI UF0ETBEI UF0ELSI UF0TEMTI

UF0ERBFI : -
bits : 0 - 0 (1 bit)
access : read-write

UF0ETBEI : -
bits : 1 - 2 (2 bit)
access : read-write

UF0ELSI : -
bits : 2 - 4 (3 bit)
access : read-write

UF0TEMTI : -
bits : 6 - 12 (7 bit)
access : read-write


UAF0IIR

UARTF0 interrupt status register
address_offset : 0x8 Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UAF0IIR UAF0IIR read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF0IRP UF0IRID UF0FMD

UF0IRP : -
bits : 0 - 0 (1 bit)
access : read-only

UF0IRID : -
bits : 1 - 4 (4 bit)
access : read-only

UF0FMD : -
bits : 6 - 13 (8 bit)
access : read-only


UAF0MOD

UARTF0 mode register
address_offset : 0xC Bytes (0x0)
size : 32 bit
access : read-write
reset_value : 0x0
reset_Mask : 0x0

UAF0MOD UAF0MOD read-write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Resets to Resets to 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UF0LG UF0STP UF0PT UF0BC UF0DLAB UF0FEN UF0RFR UF0TFR UF0FTL

UF0LG : -
bits : 0 - 1 (2 bit)
access : read-write

UF0STP : -
bits : 2 - 4 (3 bit)
access : read-write

UF0PT : -
bits : 3 - 8 (6 bit)
access : read-write

UF0BC : -
bits : 6 - 12 (7 bit)
access : read-write

UF0DLAB : -
bits : 7 - 14 (8 bit)
access : read-write

UF0FEN : -
bits : 8 - 16 (9 bit)
access : read-write

UF0RFR : -
bits : 9 - 18 (10 bit)
access : read-write

UF0TFR : -
bits : 10 - 20 (11 bit)
access : read-write

UF0FTL : -
bits : 12 - 27 (16 bit)
access : read-write



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