\n
address_offset : 0x0 Bytes (0x0)
size : 0x400 byte (0x0)
mem_usage : registers
protection : not protected
Wakeup Detect Mode Request Register 0 (P0/P1/P2/P3)
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wud_req_p0 : Wakeup Detect Request Mode: P0[7:0]
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
wud_req_p1 : Wakeup Detect Request Mode: P1[7:0]
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
End of enumeration elements list.
wud_req_p2 : Wakeup Detect Request Mode: P2[7:0]
bits : 16 - 39 (24 bit)
access : read-write
Enumeration:
End of enumeration elements list.
wud_req_p3 : Wakeup Detect Request Mode: P3[7:0]
bits : 24 - 55 (32 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Analog Input Request Register 0 (P0/P1/P2/P3)
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ali_req_p0 : Analog Input Mode Request: P0[7:0]
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ali_req_p1 : Analog Input Mode Request: P1[7:0]
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ali_req_p2 : Analog Input Mode Request: P2[7:0]
bits : 16 - 39 (24 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ali_req_p3 : Analog Input Mode Request: P3[7:0]
bits : 24 - 55 (32 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Analog Input Request Register 1 (P4/P5/P6)
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ali_req_p4 : Analog Input Mode Request: P4[7:0]
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ali_req_p5 : Analog Input Mode Request: P5[7:0]
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ali_req_p6 : Analog Input Mode Request: P6[0]
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Analog Input Acknowledge Register 0 (P0/P1/P2/P3)
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ali_ack_p0 : Analog In Mode Acknowledge: P0[7:0]
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ali_ack_p1 : Analog In Mode Acknowledge: P1[7:0]
bits : 8 - 23 (16 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ali_ack_p2 : Analog In Mode Acknowledge: P2[7:0]
bits : 16 - 39 (24 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ali_ack_p3 : Analog In Mode Acknowledge: P3[7:0]
bits : 24 - 55 (32 bit)
access : read-only
Enumeration:
End of enumeration elements list.
Analog Input Acknowledge Register 1 (P4/P5/P6)
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
ali_ack_p4 : Analog In Mode Acknowledge: P4[7:0]
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ali_ack_p5 : Analog In Mode Acknowledge: P5[7:0]
bits : 8 - 23 (16 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ali_ack_p6 : Analog In Mode Acknowledge: P6[0]
bits : 16 - 32 (17 bit)
access : read-only
Enumeration:
End of enumeration elements list.
Analog I/O Connection Control Register 0
address_offset : 0x20 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
Analog I/O Connection Control Register 1
address_offset : 0x24 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
SPIX I/O Mode Request
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
core_io_req : SPIX Core I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss0_io_req : SPIX SS[0] I/O Request
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss1_io_req : SPIX SS[1] I/O Request
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss2_io_req : SPIX SS[2] I/O Request
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
End of enumeration elements list.
quad_io_req : SPIX Quad I/O Request
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
End of enumeration elements list.
fast_mode : SPIX Fast Mode Request
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SPIX I/O Mode Acknowledge
address_offset : 0x2C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
core_io_ack : SPIX Core I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss0_io_ack : SPIX SS[0] I/O Acknowledge
bits : 8 - 16 (9 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss1_io_ack : SPIX SS[1] I/O Acknowledge
bits : 9 - 18 (10 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss2_io_ack : SPIX SS[2] I/O Acknowledge
bits : 10 - 20 (11 bit)
access : read-only
Enumeration:
End of enumeration elements list.
quad_io_ack : SPIX Quad I/O Acknowledge
bits : 12 - 24 (13 bit)
access : read-only
Enumeration:
End of enumeration elements list.
fast_mode : SPIX Fast Mode Acknowledge
bits : 16 - 32 (17 bit)
access : read-only
Enumeration:
End of enumeration elements list.
UART0 I/O Mode Request
address_offset : 0x30 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
io_map : UART0 TX/RX I/O Mapping Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
cts_map : UART0 CTS I/O Mapping Select
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rts_map : UART0 RTS I/O Mapping Select
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
io_req : UART0 TX/RX I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
cts_io_req : UART0 CTS I/O Request
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rts_io_req : UART0 RTS I/O Request
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
End of enumeration elements list.
UART0 I/O Mode Acknowledge
address_offset : 0x34 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
io_map : UART0 TX/RX I/O Mapping Acknowledge
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
cts_map : UART0 CTS I/O Mapping Acknowledge
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
End of enumeration elements list.
rts_map : UART0 RTS I/O Mapping Acknowledge
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
End of enumeration elements list.
io_req : UART0 TX/RX I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
cts_io_req : UART0 CTS I/O Acknowledge
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
End of enumeration elements list.
rts_io_req : UART0 RTS I/O Acknowledge
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
End of enumeration elements list.
UART1 I/O Mode Request
address_offset : 0x38 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
io_map : UART1 TX/RX I/O Mapping Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
cts_map : UART1 CTS I/O Mapping Select
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rts_map : UART1 RTS I/O Mapping Select
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
io_req : UART1 TX/RX I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
cts_io_req : UART1 CTS I/O Request
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rts_io_req : UART1 RTS I/O Request
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
End of enumeration elements list.
UART1 I/O Mode Acknowledge
address_offset : 0x3C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
io_map : UART1 TX/RX I/O Mapping Acknowledge
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
cts_map : UART1 CTS I/O Mapping Acknowledge
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
End of enumeration elements list.
rts_map : UART1 RTS I/O Mapping Acknowledge
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
End of enumeration elements list.
io_req : UART1 TX/RX I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
cts_io_req : UART1 CTS I/O Acknowledge
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
End of enumeration elements list.
rts_io_req : UART1 RTS I/O Acknowledge
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
End of enumeration elements list.
Wakeup Detect Mode Request Register 1 (P4/P5/P6)
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wud_req_p4 : Wakeup Detect Request Mode: P4[7:0]
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
wud_req_p5 : Wakeup Detect Request Mode: P5[7:0]
bits : 8 - 23 (16 bit)
access : read-write
Enumeration:
End of enumeration elements list.
wud_req_p6 : Wakeup Detect Request Mode: P6[0]
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
End of enumeration elements list.
UART2 I/O Mode Request
address_offset : 0x40 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
io_map : UART2 TX/RX I/O Mapping Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
cts_map : UART2 CTS I/O Mapping Select
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rts_map : UART2 RTS I/O Mapping Select
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
io_req : UART2 TX/RX I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
cts_io_req : UART2 CTS I/O Request
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rts_io_req : UART2 RTS I/O Request
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
End of enumeration elements list.
UART2 I/O Mode Acknowledge
address_offset : 0x44 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
io_map : UART2 TX/RX I/O Mapping Acknowledge
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
cts_map : UART2 CTS I/O Mapping Acknowledge
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
End of enumeration elements list.
rts_map : UART2 RTS I/O Mapping Acknowledge
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
End of enumeration elements list.
io_req : UART2 TX/RX I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
cts_io_req : UART2 CTS I/O Acknowledge
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
End of enumeration elements list.
rts_io_req : UART2 RTS I/O Acknowledge
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
End of enumeration elements list.
UART3 I/O Mode Request
address_offset : 0x48 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
io_map : UART3 TX/RX I/O Mapping Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
cts_map : UART3 CTS I/O Mapping Select
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rts_map : UART3 RTS I/O Mapping Select
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
io_req : UART3 TX/RX I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
cts_io_req : UART3 CTS I/O Request
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rts_io_req : UART3 RTS I/O Request
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
End of enumeration elements list.
UART3 I/O Mode Acknowledge
address_offset : 0x4C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
io_map : UART3 TX/RX I/O Mapping Acknowledge
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
cts_map : UART3 CTS I/O Mapping Acknowledge
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
End of enumeration elements list.
rts_map : UART3 RTS I/O Mapping Acknowledge
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
End of enumeration elements list.
io_req : UART3 TX/RX I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
cts_io_req : UART3 CTS I/O Acknowledge
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
End of enumeration elements list.
rts_io_req : UART3 RTS I/O Acknowledge
bits : 6 - 12 (7 bit)
access : read-only
Enumeration:
End of enumeration elements list.
I2C Master 0 I/O Request
address_offset : 0x50 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mapping_req : I2C Master 0 I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
I2C Master 0 I/O Acknowledge
address_offset : 0x54 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mapping_ack : I2C Master 0 I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
I2C Master 1 I/O Request
address_offset : 0x58 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mapping_req : I2C Master 1 I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
I2C Master 1 I/O Acknowledge
address_offset : 0x5C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mapping_ack : I2C Master 1 I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
I2C Master 2 I/O Request
address_offset : 0x60 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mapping_req : I2C Master 2 I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
I2C Master 2 I/O Acknowledge
address_offset : 0x64 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mapping_ack : I2C Master 2 I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
I2C Slave I/O Request
address_offset : 0x68 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
io_sel : I2C Slave I/O Mapping Select
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
mapping_req : I2C Slave I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
I2C Slave I/O Acknowledge
address_offset : 0x6C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
io_sel : I2C Slave I/O Mapping Acknowledge
bits : 0 - 1 (2 bit)
access : read-only
Enumeration:
End of enumeration elements list.
mapping_ack : I2C Slave I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
SPI Master 0 I/O Mode Request
address_offset : 0x70 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
core_io_req : SPI Master 0 Core I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss0_io_req : SPI Master 0 SS[0] I/O Request
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss1_io_req : SPI Master 0 SS[1] I/O Request
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss2_io_req : SPI Master 0 SS[2] I/O Request
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss3_io_req : SPI Master 0 SS[3] I/O Request
bits : 11 - 22 (12 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss4_io_req : SPI Master 0 SS[4] I/O Request
bits : 12 - 24 (13 bit)
access : read-write
Enumeration:
End of enumeration elements list.
quad_io_req : SPI Master 0 Quad I/O Request
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
End of enumeration elements list.
fast_mode : SPI Master 0 Fast Mode Request
bits : 24 - 48 (25 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SPI Master 0 I/O Mode Acknowledge
address_offset : 0x74 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
core_io_ack : SPI Master 0 Core I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss0_io_ack : SPI Master 0 SS[0] I/O Acknowledge
bits : 8 - 16 (9 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss1_io_ack : SPI Master 0 SS[1] I/O Acknowledge
bits : 9 - 18 (10 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss2_io_ack : SPI Master 0 SS[2] I/O Acknowledge
bits : 10 - 20 (11 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss3_io_ack : SPI Master 0 SS[3] I/O Acknowledge
bits : 11 - 22 (12 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss4_io_ack : SPI Master 0 SS[4] I/O Acknowledge
bits : 12 - 24 (13 bit)
access : read-only
Enumeration:
End of enumeration elements list.
quad_io_ack : SPI Master 0 Quad I/O Acknowledge
bits : 20 - 40 (21 bit)
access : read-only
Enumeration:
End of enumeration elements list.
fast_mode : SPI Master 0 Fast Mode Acknowledge
bits : 24 - 48 (25 bit)
access : read-only
Enumeration:
End of enumeration elements list.
SPI Master 1 I/O Mode Request
address_offset : 0x78 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
core_io_req : SPI Master 1 Core I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss0_io_req : SPI Master 1 SS[0] I/O Request
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss1_io_req : SPI Master 1 SS[1] I/O Request
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss2_io_req : SPI Master 1 SS[2] I/O Request
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
End of enumeration elements list.
quad_io_req : SPI Master 1 Quad I/O Request
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
End of enumeration elements list.
fast_mode : SPI Master 1 Fast Mode Request
bits : 24 - 48 (25 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SPI Master 1 I/O Mode Acknowledge
address_offset : 0x7C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
core_io_ack : SPI Master 1 Core I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss0_io_ack : SPI Master 1 SS[0] I/O Acknowledge
bits : 8 - 16 (9 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss1_io_ack : SPI Master 1 SS[1] I/O Acknowledge
bits : 9 - 18 (10 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss2_io_ack : SPI Master 1 SS[2] I/O Acknowledge
bits : 10 - 20 (11 bit)
access : read-only
Enumeration:
End of enumeration elements list.
quad_io_ack : SPI Master 1 Quad I/O Acknowledge
bits : 20 - 40 (21 bit)
access : read-only
Enumeration:
End of enumeration elements list.
fast_mode : SPI Master 1 Fast Mode Acknowledge
bits : 24 - 48 (25 bit)
access : read-only
Enumeration:
End of enumeration elements list.
Wakeup Detect Mode Acknowledge Register 0 (P0/P1/P2/P3)
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wud_ack_p0 : WUD Mode Acknowledge: P0[7:0]
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
End of enumeration elements list.
wud_ack_p1 : WUD Mode Acknowledge: P1[7:0]
bits : 8 - 23 (16 bit)
access : read-only
Enumeration:
End of enumeration elements list.
wud_ack_p2 : WUD Mode Acknowledge: P2[7:0]
bits : 16 - 39 (24 bit)
access : read-only
Enumeration:
End of enumeration elements list.
wud_ack_p3 : WUD Mode Acknowledge: P3[7:0]
bits : 24 - 55 (32 bit)
access : read-only
Enumeration:
End of enumeration elements list.
SPI Master 2 I/O Mode Request
address_offset : 0x80 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mapping_req : SPI Master 2 I/O Mapping Select
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
core_io_req : SPI Master 2 Core I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss0_io_req : SPI Master 2 SS[0] I/O Request
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss1_io_req : SPI Master 2 SS[1] I/O Request
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
End of enumeration elements list.
ss2_io_req : SPI Master 2 SS[2] I/O Request
bits : 10 - 20 (11 bit)
access : read-write
Enumeration:
End of enumeration elements list.
sr0_io_req : SPI Master 2 SR[0] I/O Request
bits : 16 - 32 (17 bit)
access : read-write
Enumeration:
End of enumeration elements list.
sr1_io_req : SPI Master 2 SR[1] I/O Request
bits : 17 - 34 (18 bit)
access : read-write
Enumeration:
End of enumeration elements list.
quad_io_req : SPI Master 2 Quad I/O Request
bits : 20 - 40 (21 bit)
access : read-write
Enumeration:
End of enumeration elements list.
fast_mode : SPI Master 2 Fast Mode Request
bits : 24 - 48 (25 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SPI Master 2 I/O Mode Acknowledge
address_offset : 0x84 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mapping_ack : SPI Master 2 I/O Mapping Acknowledge
bits : 0 - 0 (1 bit)
access : read-only
Enumeration:
End of enumeration elements list.
core_io_ack : SPI Master 2 Core I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss0_io_ack : SPI Master 2 SS[0] I/O Acknowledge
bits : 8 - 16 (9 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss1_io_ack : SPI Master 2 SS[1] I/O Acknowledge
bits : 9 - 18 (10 bit)
access : read-only
Enumeration:
End of enumeration elements list.
ss2_io_ack : SPI Master 2 SS[2] I/O Acknowledge
bits : 10 - 20 (11 bit)
access : read-only
Enumeration:
End of enumeration elements list.
sr0_io_req : SPI Master 2 SR[0] I/O Acknowledge
bits : 16 - 32 (17 bit)
access : read-only
Enumeration:
End of enumeration elements list.
sr1_io_req : SPI Master 2 SR[1] I/O Acknowledge
bits : 17 - 34 (18 bit)
access : read-only
Enumeration:
End of enumeration elements list.
quad_io_ack : SPI Master 2 Quad I/O Acknowledge
bits : 20 - 40 (21 bit)
access : read-only
Enumeration:
End of enumeration elements list.
fast_mode : SPI Master 2 Fast Mode Acknowledge
bits : 24 - 48 (25 bit)
access : read-only
Enumeration:
End of enumeration elements list.
SPI Bridge I/O Mode Request
address_offset : 0x88 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
core_io_req : SPI Bridge Core I/O Request
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
quad_io_req : SPI Bridge Quad I/O Request
bits : 8 - 16 (9 bit)
access : read-only
Enumeration:
End of enumeration elements list.
fast_mode : SPI Bridge Fast Mode Request
bits : 12 - 24 (13 bit)
access : read-only
Enumeration:
End of enumeration elements list.
SPI Bridge I/O Mode Acknowledge
address_offset : 0x8C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
core_io_ack : SPI Bridge Core I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
quad_io_ack : SPI Bridge Quad I/O Acknowledge
bits : 8 - 16 (9 bit)
access : read-only
Enumeration:
End of enumeration elements list.
fast_mode : SPI Bridge Fast Mode Acknowledge
bits : 12 - 24 (13 bit)
access : read-only
Enumeration:
End of enumeration elements list.
1-Wire Master I/O Mode Request
address_offset : 0x90 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mapping_req : 1-Wire Line I/O Request
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
epu_io_req : External Pullup Control Line I/O Request
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
1-Wire Master I/O Mode Acknowledge
address_offset : 0x94 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mapping_ack : 1-Wire Line I/O Acknowledge
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
epu_io_ack : External Pullup Control Line I/O Acknowledge
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Wakeup Detect Mode Acknowledge Register 1 (P4/P5/P6)
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
wud_ack_p4 : WUD Mode Acknowledge: P4[7:0]
bits : 0 - 7 (8 bit)
access : read-only
Enumeration:
End of enumeration elements list.
wud_ack_p5 : WUD Mode Acknowledge: P5[7:0]
bits : 8 - 23 (16 bit)
access : read-only
Enumeration:
End of enumeration elements list.
wud_ack_p6 : WUD Mode Acknowledge: P6[7:0]
bits : 16 - 32 (17 bit)
access : read-only
Enumeration:
End of enumeration elements list.
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