\n
address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
Full Speed SCL Clock Settings
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
fs_filter_clk_div : Full Speed Filter Clock Divisor
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
fs_scl_lo_cnt : Full Speed SCL Low Count
bits : 8 - 27 (20 bit)
access : read-write
Enumeration:
End of enumeration elements list.
fs_scl_hi_cnt : Full Speed SCL High Count
bits : 20 - 51 (32 bit)
access : read-write
Enumeration:
End of enumeration elements list.
I2C Master Control Register
address_offset : 0x10 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tx_fifo_en : Master Transaction FIFO Enable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rx_fifo_en : Master Results FIFO Enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
mstr_reset_en : Master Reset
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
I2C Master Transaction Start and Status Flags
address_offset : 0x14 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tx_start : Start Transaction
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_in_progress : Transaction In Progress
bits : 1 - 2 (2 bit)
access : read-only
Enumeration:
End of enumeration elements list.
tx_done : Transaction Done
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
End of enumeration elements list.
tx_nacked : Transaction Nacked
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
End of enumeration elements list.
tx_lost_arbitr : Transaction Lost Arbitration
bits : 4 - 8 (5 bit)
access : read-only
Enumeration:
End of enumeration elements list.
tx_timeout : Transaction Timed Out
bits : 5 - 10 (6 bit)
access : read-only
Enumeration:
End of enumeration elements list.
Interrupt Flags
address_offset : 0x18 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tx_done : Transaction Done Int Status
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_nacked : Transaction NACKed Int Status
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_lost_arbitr : Transaction Lost Arbitration Int Status
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_timeout : Transaction Timed Out Int Status
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_fifo_empty : Transaction FIFO Empty Int Status
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_fifo_3q_empty : Transaction FIFO 3Q Empty Int Status
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rx_fifo_empty : Results FIFO Empty Int Status
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rx_fifo_2q_full : Results FIFO 2Q Full Int Status
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rx_fifo_3q_full : Results FIFO 3Q Full Int Status
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rx_fifo_full : Results FIFO Full Int Status
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Interrupt Enable/Disable Controls
address_offset : 0x1C Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tx_done : Transaction Done Int Enable
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_nacked : Transaction NACKed Int Enable
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_lost_arbitr : Transaction Lost Arbitration IntEnable
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_timeout : Transaction Timed Out Int Enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_fifo_empty : Transaction FIFO Empty Int Enable
bits : 4 - 8 (5 bit)
access : read-write
Enumeration:
End of enumeration elements list.
tx_fifo_3q_empty : Transaction FIFO 3Q Empty Int Enable
bits : 5 - 10 (6 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rx_fifo_empty : Results FIFO Empty Int Enable
bits : 6 - 12 (7 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rx_fifo_2q_full : Results FIFO 2Q Full Int Enable
bits : 7 - 14 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rx_fifo_3q_full : Results FIFO 3Q Full Int Enable
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
End of enumeration elements list.
rx_fifo_full : Results FIFO Full Int Enable
bits : 9 - 18 (10 bit)
access : read-write
Enumeration:
End of enumeration elements list.
Bit-Bang Control Register
address_offset : 0x28 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
bb_scl_out : Bit Bang SCL Output
bits : 0 - 0 (1 bit)
access : read-write
Enumeration:
End of enumeration elements list.
bb_sda_out : Bit Bang SDA Output
bits : 1 - 2 (2 bit)
access : read-write
Enumeration:
End of enumeration elements list.
bb_scl_in_val : Bit Bang SCL Input Value
bits : 2 - 4 (3 bit)
access : read-only
Enumeration:
End of enumeration elements list.
bb_sda_in_val : Bit Bang SCL Input Value
bits : 3 - 6 (4 bit)
access : read-only
Enumeration:
End of enumeration elements list.
rx_fifo_cnt : Results FIFO Data Received Count
bits : 16 - 36 (21 bit)
access : read-only
Enumeration:
End of enumeration elements list.
Timeout and Auto-Stop Settings
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
tx_timeout : Transaction Timeout Limit
bits : 16 - 39 (24 bit)
access : read-write
Enumeration:
End of enumeration elements list.
auto_stop_en : Auto-Stop Enable
bits : 24 - 48 (25 bit)
access : read-write
Enumeration:
End of enumeration elements list.
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