Embeetle, an IDE designed from scratch for embedded software developers.address_offset : 0x0 Bytes (0x0)
size : 0x1000 byte (0x0)
mem_usage : registers
protection : not protected
SPIX Master Configuration
address_offset : 0x0 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
spi_mode : SPIX Mode
bits : 0 - 1 (2 bit)
access : read-write
Enumeration:
0 : SCK_HI_SAMPLE_RISING
SCK is active high, data is sampled on clock rising edge.
3 : SCK_LO_SAMPLE_FALLING
SCK is active low, data is sampled on clock rising edge.
End of enumeration elements list.
ss_act_lo : SPIX Slave Select Polarity
bits : 2 - 4 (3 bit)
access : read-write
Enumeration:
0 : ACTIVE_HIGH
Enabled slave select (SS) is active high.
1 : ACTIVE_LOW
Enabled slave select (SS) is active low.
End of enumeration elements list.
alt_timing_en : Alternate Timing Mode Enable
bits : 3 - 6 (4 bit)
access : read-write
Enumeration:
0 : DISABLED
Alternate timing is disabled.
1 : ENABLED_AS_NEEDED
Alternate timing will be enabled automatically when needed.
End of enumeration elements list.
slave_sel : SPIX Slave Select
bits : 4 - 10 (7 bit)
access : read-write
Enumeration:
End of enumeration elements list.
sck_hi_clk : SCK High Clocks
bits : 8 - 19 (12 bit)
access : read-write
Enumeration:
End of enumeration elements list.
sck_lo_clk : SCK Low Clocks
bits : 12 - 27 (16 bit)
access : read-write
Enumeration:
End of enumeration elements list.
act_delay : SS Active Timing
bits : 16 - 33 (18 bit)
access : read-write
Enumeration:
0 : OFF
No SS Active timing delay enabled.
1 : FOR_2_MOD_CLK
SS Active timing delay of 2 SPIX module clock cycles.
2 : FOR_4_MOD_CLK
SS Active timing delay of 4 SPIX module clock cycles.
3 : FOR_8_MOD_CLK
SS Active timing delay of 8 SPIX module clock cycles.
End of enumeration elements list.
inact_delay : SS Inactive Timing
bits : 18 - 37 (20 bit)
access : read-write
Enumeration:
0 : OFF
No SS Active timing delay enabled.
1 : FOR_2_MOD_CLK
SS Active timing delay of 2 SPIX module clock cycles.
2 : FOR_4_MOD_CLK
SS Active timing delay of 4 SPIX module clock cycles.
3 : FOR_8_MOD_CLK
SS Active timing delay of 8 SPIX module clock cycles.
End of enumeration elements list.
alt_sck_hi_clk : Alt SCK High Clocks
bits : 20 - 43 (24 bit)
access : read-write
Enumeration:
End of enumeration elements list.
alt_sck_lo_clk : Alt SCK Low Clocks
bits : 24 - 51 (28 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SPIX Fetch Control
address_offset : 0x4 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
cmd_value : Command Value
bits : 0 - 7 (8 bit)
access : read-write
Enumeration:
End of enumeration elements list.
cmd_width : Command Width
bits : 8 - 17 (10 bit)
access : read-write
Enumeration:
0 : SINGLE
Single I/O used for Tx/Rx.
1 : DUAL_IO
Dual I/O lines used for Tx/Rx.
2 : QUAD_IO
Quad I/O lines used for Tx/Rx.
End of enumeration elements list.
addr_width : Address Width
bits : 10 - 21 (12 bit)
access : read-write
Enumeration:
0 : SINGLE
Single I/O used for Tx/Rx.
1 : DUAL_IO
Dual I/O lines used for Tx/Rx.
2 : QUAD_IO
Quad I/O lines used for Tx/Rx.
End of enumeration elements list.
data_width : Data Width
bits : 12 - 25 (14 bit)
access : read-write
Enumeration:
0 : SINGLE
Single I/O used for Tx/Rx.
1 : DUAL_IO
Dual I/O lines used for Tx/Rx.
2 : QUAD_IO
Quad I/O lines used for Tx/Rx.
End of enumeration elements list.
SPIX Mode Control
address_offset : 0x8 Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mode_clocks : Mode Clocks
bits : 0 - 3 (4 bit)
access : read-write
Enumeration:
End of enumeration elements list.
no_cmd_mode : No Command Mode
bits : 8 - 16 (9 bit)
access : read-write
Enumeration:
End of enumeration elements list.
SPIX Mode Data
address_offset : 0xC Bytes (0x0)
access : read-write
reset_value : 0x0
reset_Mask : 0x0
mode_data_bits : Mode Data
bits : 0 - 15 (16 bit)
access : read-write
Enumeration:
End of enumeration elements list.
mode_data_oe : Mode Output Enable
bits : 16 - 47 (32 bit)
access : read-write
Enumeration:
End of enumeration elements list.
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